From patchwork Wed May 11 01:11:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 12845659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64DC9C433F5 for ; Wed, 11 May 2022 01:11:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BD6A710E212; Wed, 11 May 2022 01:11:50 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id A2C2210E212; Wed, 11 May 2022 01:11:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652231510; x=1683767510; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Eac7OTb5myQ/M0qm32GufZrULc5YHPWR/oDB0/s6kdQ=; b=HWKWuFg2GzlsP1marP1TR7wR3e8BpQuoAxvXEk15Caon11FgHlP/NxmF t04dw5X5sNn2zy2LFfSugc59wAQPGoYg9Q/n2ZnBPHzZvNViqb1tpuhCs ttbwKW+l7LjU1HTQyQytcxJ9RIrCS+LWb/UxZxvvJRsTimcV6T3FzXCJj +kS4MSKa3F5OabXAiI9ch/Snr7NxhtG6jM37A/xx3yPB/XHKOzSkKCC5h QHx6M9/QYH8lMFuLF7k3D1j76u757qauv976gsghppJ1R7eVipv/K2Z4x A61K2FLywQ1OfdeSwBtpTukTtGEhslQP196bPjE5T07tIDwVKBOyP5O0W Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="249446376" X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="249446376" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 18:11:41 -0700 X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="565924479" Received: from ymmonter-mobl.amr.corp.intel.com (HELO intel.com) ([10.249.32.19]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 18:11:38 -0700 From: Andi Shyti To: Intel GFX , DRI Devel Date: Wed, 11 May 2022 03:11:19 +0200 Message-Id: <20220511011121.114226-2-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511011121.114226-1-andi.shyti@linux.intel.com> References: <20220511011121.114226-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 1/3] drm/i915/gt: Ignore TLB invalidations on idle engines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Auld , Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Chris Wilson As an extension of the current skip TLB invalidations if the device is powered down, we recognised that prior to any engine activity, all the TLBs are explicitly invalidated. Thus anytime we know the engine is asleep, we can skip invalidating the TLBs on that engine. Signed-off-by: Chris Wilson Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_pm.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h index bc898df7a48cc..3b1fbce7ea369 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h @@ -55,6 +55,10 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt) for (tmp = 1, intel_gt_pm_get(gt); tmp; \ intel_gt_pm_put(gt), tmp = 0) +#define with_intel_gt_pm_if_awake(gt, tmp) \ + for (tmp = 1, intel_gt_pm_get_if_awake(gt); tmp; \ + intel_gt_pm_put(gt), tmp = 0) + static inline int intel_gt_pm_wait_for_idle(struct intel_gt *gt) { return intel_wakeref_wait_for_idle(>->wakeref); From patchwork Wed May 11 01:11:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 12845660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 48369C433EF for ; Wed, 11 May 2022 01:11:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1D23010E270; Wed, 11 May 2022 01:11:53 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 706CC10E270; Wed, 11 May 2022 01:11:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652231511; x=1683767511; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UyVcf5nZHWO8xkKbUWH9mwih+BrTrIcz4jn40EOW78E=; b=hEfb45cPvAlbXRVJ/qJtk0AsvVGfHeqZLELA5klKljXb0VlXTgN2g/fI 8UV+7vQta1uMbx0AXmPEfFuBXKgmTbLUEe8l5AMF+o0wUAiB0pdfZ/ifp MXFCcldy8e12mELItT2jh2HkVD0i2+FZ1ZttFLyXbSj+vnSHTq/yvglFm crYByTYkBwUrfK/9LuDoDdzb5gFVx/71Vvj0sWETBan5f6Clu4XNK3S4l xVpex1SQlccG1HeO3vuf6HhyQhihy5Gig0iL3Trb5cpKtP1k/dfAyGB3R +U55K5e+/7woUldriochs3akhdI/4rLrk60qPmu6fdvWG/7gxRJ/7Vsol w==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="249446395" X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="249446395" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 18:11:47 -0700 X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="542067952" Received: from ymmonter-mobl.amr.corp.intel.com (HELO intel.com) ([10.249.32.19]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 18:11:44 -0700 From: Andi Shyti To: Intel GFX , DRI Devel Date: Wed, 11 May 2022 03:11:20 +0200 Message-Id: <20220511011121.114226-3-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511011121.114226-1-andi.shyti@linux.intel.com> References: <20220511011121.114226-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 2/3] drm/i915/gem: Flush TLBs for all the tiles when clearing an obj X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Auld , Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During object cleanup we invalidate the TLBs but we do it only for gt0. Invalidate the caches for all the tiles. Reported-by: Chris Wilson Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c index 97c820eee115a..37d23e328bd0c 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -13,6 +13,7 @@ #include "i915_gem_mman.h" #include "gt/intel_gt.h" +#include "gt/intel_gt_pm.h" void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, struct sg_table *pages, @@ -217,10 +218,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj) if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) { struct drm_i915_private *i915 = to_i915(obj->base.dev); - intel_wakeref_t wakeref; + struct intel_gt *gt; + int i; - with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref) - intel_gt_invalidate_tlbs(to_gt(i915)); + for_each_gt(gt, i915, i) { + int tmp; + + with_intel_gt_pm_if_awake(gt, tmp) + intel_gt_invalidate_tlbs(gt); + } } return pages; From patchwork Wed May 11 01:11:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 12845661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B38C3C433F5 for ; Wed, 11 May 2022 01:12:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2816A10E2D5; Wed, 11 May 2022 01:11:57 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id C79A410E2D5; Wed, 11 May 2022 01:11:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652231515; x=1683767515; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I6FtYd8IWa0vizcHYBNqD6wELn3qIz9PbRheYsUhBH4=; b=UjfaUuzdJRtmI5I01XL7xZCUlv9QY0pyF3sSbr5kSYumTsbzhZIAiE0L RxBEraCPvBObABEF0GuPuoRf4Pa2Lx/3fR9XJrZxx82dipx19vpGzwY24 n5DsMVgTbQL3duyhI394cyn2vw9YUBVoB252iouP2BazcmnVHxoY2vnT6 m6ToUPJq/2ImxlKOmgWnEoR3Y1oMNZz29Tx1qGSXCsXP8CJN3vN+X2SIZ F5KbX+eUWVVYVyf3Kc1qDkP3mHaraLKDHAv+gk2wRnqQ68cit7ylFbYVZ 6ehyhVQyaxpSONsp1m32N+AAfOnnMAiyMrn9iFLVMnAI7QVBYTr9oV5hf w==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="249446416" X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="249446416" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 18:11:54 -0700 X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="738983106" Received: from ymmonter-mobl.amr.corp.intel.com (HELO intel.com) ([10.249.32.19]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 18:11:51 -0700 From: Andi Shyti To: Intel GFX , DRI Devel Date: Wed, 11 May 2022 03:11:21 +0200 Message-Id: <20220511011121.114226-4-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511011121.114226-1-andi.shyti@linux.intel.com> References: <20220511011121.114226-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 3/3] drm/i915/gt: Skip TLB invalidation if the engine is not awake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Auld , Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We want to check if the engine is awake first before invalidating its cache. Suggested-by: Chris Wilson Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 034182f85501b..a1dc9f4203c2b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -12,6 +12,7 @@ #include "i915_drv.h" #include "intel_context.h" #include "intel_engine_regs.h" +#include "intel_engine_pm.h" #include "intel_gt.h" #include "intel_gt_buffer_pool.h" #include "intel_gt_clock_utils.h" @@ -1219,6 +1220,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) const unsigned int timeout_ms = 4; struct reg_and_bit rb; + if (!intel_engine_pm_is_awake(engine)) + continue; + rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); if (!i915_mmio_reg_offset(rb.reg)) continue;