From patchwork Wed May 11 00:57:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 12845837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3757C433EF for ; Wed, 11 May 2022 06:30:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E20E610E977; Wed, 11 May 2022 06:30:34 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 59B2010F4A1; Wed, 11 May 2022 00:58:19 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="269480507" X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="269480507" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 17:58:18 -0700 X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="565919875" Received: from ymmonter-mobl.amr.corp.intel.com (HELO intel.com) ([10.249.32.19]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 17:58:15 -0700 From: Andi Shyti To: Intel GFX , DRI Devel Subject: [PATCH v3 1/3] drm/i915/gt: Ignore TLB invalidations on idle engines Date: Wed, 11 May 2022 02:57:54 +0200 Message-Id: <20220511005756.113245-2-andi.shyti@studenti.polito.it> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511005756.113245-1-andi.shyti@studenti.polito.it> References: <20220511005756.113245-1-andi.shyti@studenti.polito.it> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 11 May 2022 06:30:33 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tvrtko Ursulin , Andi Shyti , Matthew Auld , Andi Shyti , Chris Wilson Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chris Wilson As an extension of the current skip TLB invalidations if the device is powered down, we recognised that prior to any engine activity, all the TLBs are explicitly invalidated. Thus anytime we know the engine is asleep, we can skip invalidating the TLBs on that engine. Signed-off-by: Chris Wilson Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_pm.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h index bc898df7a48cc..3b1fbce7ea369 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h @@ -55,6 +55,10 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt) for (tmp = 1, intel_gt_pm_get(gt); tmp; \ intel_gt_pm_put(gt), tmp = 0) +#define with_intel_gt_pm_if_awake(gt, tmp) \ + for (tmp = 1, intel_gt_pm_get_if_awake(gt); tmp; \ + intel_gt_pm_put(gt), tmp = 0) + static inline int intel_gt_pm_wait_for_idle(struct intel_gt *gt) { return intel_wakeref_wait_for_idle(>->wakeref); From patchwork Wed May 11 00:57:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 12845838 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8852C433F5 for ; Wed, 11 May 2022 06:30:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E5EB10E9DD; Wed, 11 May 2022 06:30:35 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 74EFC10EBD7; Wed, 11 May 2022 00:58:26 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="355970994" X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="355970994" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 17:58:25 -0700 X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="542063008" Received: from ymmonter-mobl.amr.corp.intel.com (HELO intel.com) ([10.249.32.19]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 17:58:22 -0700 From: Andi Shyti To: Intel GFX , DRI Devel Subject: [PATCH v3 2/3] drm/i915/gem: Flush TLBs for all the tiles when clearing an obj Date: Wed, 11 May 2022 02:57:55 +0200 Message-Id: <20220511005756.113245-3-andi.shyti@studenti.polito.it> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511005756.113245-1-andi.shyti@studenti.polito.it> References: <20220511005756.113245-1-andi.shyti@studenti.polito.it> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 11 May 2022 06:30:33 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tvrtko Ursulin , Andi Shyti , Matthew Auld , Andi Shyti , Chris Wilson Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" During object cleanup we invalidate the TLBs but we do it only for gt0. Invalidate the caches for all the tiles. Reported-by: Chris Wilson Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c index 97c820eee115a..37d23e328bd0c 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -13,6 +13,7 @@ #include "i915_gem_mman.h" #include "gt/intel_gt.h" +#include "gt/intel_gt_pm.h" void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, struct sg_table *pages, @@ -217,10 +218,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj) if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) { struct drm_i915_private *i915 = to_i915(obj->base.dev); - intel_wakeref_t wakeref; + struct intel_gt *gt; + int i; - with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref) - intel_gt_invalidate_tlbs(to_gt(i915)); + for_each_gt(gt, i915, i) { + int tmp; + + with_intel_gt_pm_if_awake(gt, tmp) + intel_gt_invalidate_tlbs(gt); + } } return pages; From patchwork Wed May 11 00:57:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 12845840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8636EC433EF for ; Wed, 11 May 2022 06:30:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0758D10EA03; Wed, 11 May 2022 06:30:36 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id C0C9210EC83; Wed, 11 May 2022 00:58:32 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="251594241" X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="251594241" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 17:58:32 -0700 X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="565919919" Received: from ymmonter-mobl.amr.corp.intel.com (HELO intel.com) ([10.249.32.19]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 17:58:29 -0700 From: Andi Shyti To: Intel GFX , DRI Devel Subject: [PATCH v3 3/3] drm/i915/gt: Skip TLB invalidation if the engine is not awake Date: Wed, 11 May 2022 02:57:56 +0200 Message-Id: <20220511005756.113245-4-andi.shyti@studenti.polito.it> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220511005756.113245-1-andi.shyti@studenti.polito.it> References: <20220511005756.113245-1-andi.shyti@studenti.polito.it> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 11 May 2022 06:30:33 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tvrtko Ursulin , Andi Shyti , Matthew Auld , Andi Shyti , Chris Wilson Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Andi Shyti We want to check if the engine is awake first before invalidating its cache. Suggested-by: Chris Wilson Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 034182f85501b..a1dc9f4203c2b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -12,6 +12,7 @@ #include "i915_drv.h" #include "intel_context.h" #include "intel_engine_regs.h" +#include "intel_engine_pm.h" #include "intel_gt.h" #include "intel_gt_buffer_pool.h" #include "intel_gt_clock_utils.h" @@ -1219,6 +1220,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) const unsigned int timeout_ms = 4; struct reg_and_bit rb; + if (!intel_engine_pm_is_awake(engine)) + continue; + rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); if (!i915_mmio_reg_offset(rb.reg)) continue;