From patchwork Wed May 11 14:45:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12846273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF5F9C433F5 for ; Wed, 11 May 2022 14:49:04 +0000 (UTC) Received: from localhost ([::1]:60466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1noneB-0005Cn-SX for qemu-devel@archiver.kernel.org; Wed, 11 May 2022 10:49:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48748) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nonbk-0001zf-2A for qemu-devel@nongnu.org; Wed, 11 May 2022 10:46:33 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:37545) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nonbh-0001An-P1 for qemu-devel@nongnu.org; Wed, 11 May 2022 10:46:31 -0400 Received: by mail-pg1-x535.google.com with SMTP id 15so1999037pgf.4 for ; Wed, 11 May 2022 07:46:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Odlh7Y8iwGv1s0I3j3Ny/+JD8qBeRZdaKDHUoz/NXA8=; b=mSFbb0P22pT24Giufkp0x3HGTWI2I0M5Oxrz0uF5lxlHAW9gz/RU7EIvDjL49Ngz3g uBL7nHQhs/aA5q8+bpjW5v3fCITULZYL17RkmRHH0E0BjpHvWx3Z//SMwl/VjqrgrNeC 4y8Ru0Ytjb47EjylI92J0Ecde69sjkY3tSxDdPFUMbgYgDyA4/jc1wyv5c/ifSpoU3AJ +ZC7U07GJrccFiskDWLwrl0PncP1QMETZ2eBpQ5v5UwE2SigX72mQAOJc3R+loa53gjs x0XQs6u4oVhP4k0iZrm/XSXFxX/pG92LRjWvhXUvc4FP4JaaJ1ZA9nHwl6CkjR/LFbk9 jprQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Odlh7Y8iwGv1s0I3j3Ny/+JD8qBeRZdaKDHUoz/NXA8=; b=rUAAiQl4OlDIdkcZw1JTsrpW+HjjQsUBeHAuIHx4wYDW+TAsN+mXtUyMK5Pt0AgOGj NpMwOGV5RGthdM7Yk/noLiH6Ko/eyNI7/Ca7k27u0SYj+Kp64MMoPO9reqe9Gnw3EYaR 0eYh+JYRFOeL5vegD0vvgL80AQv/j9vSfXXz8U9f8YnmBcGSkiw+8oU74gH8QTTrHlk6 9T5SqDqzJzcbraHEZgHmOBaV9pLdPWrgUIdhpYtJ3F9FlGGGcvBjv6IjI7ZatbHSzN6D DFgTOPl22ttSvCnSO5KoitzfFor1vgLGnpvh1/ytu7LaPPGYcIobAdJAx+JLTGzm9OC8 Pwtg== X-Gm-Message-State: AOAM53242NA3lR6P3wGwPjDVlibavX8PeoJVMrv5Pu2P/d12VvyYjM6o /FBXOXRU56E3+YUfPbx2gi/2xA== X-Google-Smtp-Source: ABdhPJxXlBAlmRpS8Ogji5d5DP2JzCpdMEf3dhR/VkSISKk1gPFzo0B9LnDf4sBLtZfQDQZTuXy/Ig== X-Received: by 2002:a05:6a00:1acd:b0:50e:1872:c680 with SMTP id f13-20020a056a001acd00b0050e1872c680mr25877801pfv.16.1652280388454; Wed, 11 May 2022 07:46:28 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.113.90]) by smtp.gmail.com with ESMTPSA id x2-20020a170902820200b0015eafc485c8sm1958726pln.289.2022.05.11.07.46.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 07:46:27 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Alistair Francis , Frank Chang Subject: [PATCH v2 1/8] target/riscv: Fix csr number based privilege checking Date: Wed, 11 May 2022 20:15:21 +0530 Message-Id: <20220511144528.393530-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220511144528.393530-1-apatel@ventanamicro.com> References: <20220511144528.393530-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=apatel@ventanamicro.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" When hypervisor and VS CSRs are accessed from VS-mode or VU-mode, the riscv_csrrw_check() function should generate virtual instruction trap instead illegal instruction trap. Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/csr.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3500e07f92..2bf0a97196 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3139,7 +3139,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, int read_only = get_field(csrno, 0xC00) == 3; int csr_min_priv = csr_ops[csrno].min_priv_ver; #if !defined(CONFIG_USER_ONLY) - int effective_priv = env->priv; + int csr_priv, effective_priv = env->priv; if (riscv_has_ext(env, RVH) && env->priv == PRV_S && @@ -3152,7 +3152,11 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, effective_priv++; } - if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { + csr_priv = get_field(csrno, 0x300); + if (!env->debugger && (effective_priv < csr_priv)) { + if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } return RISCV_EXCP_ILLEGAL_INST; } #endif From patchwork Wed May 11 14:45:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12846274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C07CC433FE for ; Wed, 11 May 2022 14:50:28 +0000 (UTC) Received: from localhost ([::1]:36740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nonfX-00089V-7O for qemu-devel@archiver.kernel.org; Wed, 11 May 2022 10:50:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nonbo-00022T-50 for qemu-devel@nongnu.org; Wed, 11 May 2022 10:46:36 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:40956) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nonbm-0001BH-Ib for qemu-devel@nongnu.org; Wed, 11 May 2022 10:46:35 -0400 Received: by mail-pj1-x102b.google.com with SMTP id iq2-20020a17090afb4200b001d93cf33ae9so5140006pjb.5 for ; Wed, 11 May 2022 07:46:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cQC++Y+pGUPUs/8x3sQ/i/xqv7tFU+CkLDMWJDdpamI=; b=hwzEePzDD8eho2m/nLCG0OVoBNWJvhCW9mEOImuXTlg2+gf0ia7oAbKSM4BYyKtoTV 46H3mBulnlmepSbVJNRiKoTFIX0uYsgm2fQ3knSAaq0+0N4HPoFt2+21wMt52LvcCh2M Dj4D/tKbTxSZ24BepOtnGC7T1UqgFMRudYSJPcr4yDObe9+nIJ01oxCv2grAq8ZFKWtN yZaj9U033v+iImbt66uADoS2/Sk+mFl6P07mWLpSJY8hm3lGBYT7xHmNFa92zcmocyVA Eu/uxcDYg3YNaFLDQ1pmjIBVvAj1YK5HWwQv0lc+zV8kl3XTC441z6ZHzAxg4FWO+21r F6vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cQC++Y+pGUPUs/8x3sQ/i/xqv7tFU+CkLDMWJDdpamI=; b=1fLfpqUHF/i3VhCZgeGnUfzBWXauF/GeGYCUMHviBKK4fGjBbSOQqMuZAUnlqRjggp UpNQch8h13nQLqAqxIov9bfuahGen6BI758U06UEZKPoqWnFE+Oha+cW09K6vt5ihAkE sJkl7zSG9e2Gc7ZsW31PEm2wmtdCvmF8AQ2D844+F4eDcI/D7DWVjv0JOLjMYlBegtvE wC/6UJlVzmyOjGGu6J7rCoOa9CaRwU7v2LOIQIHX7e/F64+JeWvFZXeaHpA5DEKiiaNU MM+xO1Cgp0Sh0CNxBifAmNK1eCEVyKHCLcisS8Xv+M1oVFpUnIDDgnjdf3VsaOCVeruu nBSw== X-Gm-Message-State: AOAM532vexiTvQ+qAQuUcQt52zXBgyyrzwZdZtnvDPBxuD0Kyut+tEtz c2kT+XUqo+diVJy8w1vvID1m3g== X-Google-Smtp-Source: ABdhPJxrT/pDMXP3nE59GCBHnmvltIpmsxr/S2apkhSJ7ckpd3BwnxwXKpyopDWdlCxaXbLMY65+FA== X-Received: by 2002:a17:902:dac1:b0:15e:9faa:e926 with SMTP id q1-20020a170902dac100b0015e9faae926mr25449593plx.61.1652280392835; Wed, 11 May 2022 07:46:32 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.113.90]) by smtp.gmail.com with ESMTPSA id x2-20020a170902820200b0015eafc485c8sm1958726pln.289.2022.05.11.07.46.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 07:46:31 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v2 2/8] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode Date: Wed, 11 May 2022 20:15:22 +0530 Message-Id: <20220511144528.393530-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220511144528.393530-1-apatel@ventanamicro.com> References: <20220511144528.393530-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Currently, QEMU does not set hstatus.GVA bit for traps taken from HS-mode into HS-mode which breaks the Xvisor nested MMU test suite on QEMU. This was working previously. This patch updates riscv_cpu_do_interrupt() to fix the above issue. Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e1aa4f2097..b16bfe0182 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1367,7 +1367,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: - write_gva = true; + write_gva = env->two_stage_lookup; tval = env->badaddr; break; case RISCV_EXCP_ILLEGAL_INST: @@ -1434,7 +1434,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* Trap into HS mode */ env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); htval = env->guest_phys_fault_addr; - write_gva = false; } env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); } From patchwork Wed May 11 14:45:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12846280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D7A7C433F5 for ; Wed, 11 May 2022 14:51:46 +0000 (UTC) Received: from localhost ([::1]:40602 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nongn-0002ML-G1 for qemu-devel@archiver.kernel.org; Wed, 11 May 2022 10:51:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48846) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nonbs-00024j-Fv for qemu-devel@nongnu.org; Wed, 11 May 2022 10:46:42 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:40956) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nonbq-0001BH-6a for qemu-devel@nongnu.org; Wed, 11 May 2022 10:46:40 -0400 Received: by mail-pj1-x102b.google.com with SMTP id iq2-20020a17090afb4200b001d93cf33ae9so5140006pjb.5 for ; Wed, 11 May 2022 07:46:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R8kNWRVdB8QKUb/YAK/VeWct6HywF60TKnrrSENw248=; b=TeS089Qw51/OF6NAiGTP9/Kf0FMhj7hQ4DQytmEvC6bk7n8xYJGPGBI783X64WPBeB upamOCL0klq77rtHnzwOp72mKMugHNLD+hDJDf20PGK4Sa+JP2AQJ5l0JgvRLOqLkiAl tDrjxN6767gcMRYl0GAzxpIEo/Ys32oE25DAknxcSqZxEP+hoGKFdkjaNs45bT+z/Ep8 eaD+2OVgIeyHId02CnB3GORVgJYlvZg5iMUT+5iS/M47xKB6Zju2lU6bevwBjGSU5KCN mRhKGBZ5Jgs5WNSsrK76DvYB6quS0U7rwd5ba2JddohuAclGje5rzGS7HA02/ivbIzff NEYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R8kNWRVdB8QKUb/YAK/VeWct6HywF60TKnrrSENw248=; b=U9LsTbt6Ue7V3U9B2Yw4jVhD5YvyvM3t4+vM6dT2owE7Bv3f5TUomDfbgkSnVyIPjv QuXdsZboVu39O4wxkI8e7+cDgm0QN55OZkAeeONaejSWA83IsY4Y6ZO6TLFMFO+vVLp1 ay6XFcQuZ3HZhRsUpinD27wXvmiFrYI4WVPgn0gkfnMvlCVgp3TWzfHTVDHDovbjdGMy jgGzJVKBM6si4aAc4wIztfRxKju/7bZZpTd8LZAQhVux8mALBO3WJUKNlpXKqTbQehnc HExu0jetEV5L02ehBBQUZmDDcqQ8NkmaINKfs6I9q2m4nnf6pAuaXZDL8UmHjHKQ6p4p E/lQ== X-Gm-Message-State: AOAM53100/MnaY4blZSCTIhtc57YT7bUaQL8xI38LO1Rr36faUhoh6rg rOI5olu8fghq/B0Ne2qImdOnVA== X-Google-Smtp-Source: ABdhPJxUTuG38c2LLmQ/fertLUYy4gjzIVi0lQ4FdKqnHy87SVyaxtQwnT7aB7rMh4f88zG7lVd+qA== X-Received: by 2002:a17:902:e5c1:b0:15e:b847:2958 with SMTP id u1-20020a170902e5c100b0015eb8472958mr25342634plf.101.1652280397440; Wed, 11 May 2022 07:46:37 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.113.90]) by smtp.gmail.com with ESMTPSA id x2-20020a170902820200b0015eafc485c8sm1958726pln.289.2022.05.11.07.46.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 07:46:36 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Frank Chang , Alistair Francis Subject: [PATCH v2 3/8] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps Date: Wed, 11 May 2022 20:15:23 +0530 Message-Id: <20220511144528.393530-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220511144528.393530-1-apatel@ventanamicro.com> References: <20220511144528.393530-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Currently, the [m|s]tval CSRs are set with trapping instruction encoding only for illegal instruction traps taken at the time of instruction decoding. In RISC-V world, a valid instructions might also trap as illegal or virtual instruction based to trapping bits in various CSRs (such as mstatus.TVM or hstatus.VTVM). We improve setting of [m|s]tval CSRs for all types of illegal and virtual instruction traps. Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 8 +++++++- target/riscv/cpu_helper.c | 1 + target/riscv/translate.c | 17 +++++++++++++---- 4 files changed, 23 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..9a5be9732d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -406,6 +406,7 @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, } else { env->pc = data[0]; } + env->bins = data[1]; } static void riscv_cpu_reset(DeviceState *dev) @@ -445,6 +446,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mcause = 0; env->miclaim = MIP_SGEIP; env->pc = env->resetvec; + env->bins = 0; env->two_stage_lookup = false; /* Initialized default priorities of local interrupts. */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fe6c9a2c92..a55c918274 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -30,6 +30,12 @@ #define TCG_GUEST_DEFAULT_MO 0 +/* + * RISC-V-specific extra insn start words: + * 1: Original instruction opcode + */ +#define TARGET_INSN_START_EXTRA_WORDS 1 + #define TYPE_RISCV_CPU "riscv-cpu" #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU @@ -140,7 +146,7 @@ struct CPUArchState { target_ulong frm; target_ulong badaddr; - uint32_t bins; + target_ulong bins; target_ulong guest_phys_fault_addr; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b16bfe0182..d99fac9d2d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1371,6 +1371,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) tval = env->badaddr; break; case RISCV_EXCP_ILLEGAL_INST: + case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: tval = env->bins; break; default: diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0cd1d9ee94..55a4713af2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -107,6 +107,8 @@ typedef struct DisasContext { /* PointerMasking extension */ bool pm_mask_enabled; bool pm_base_enabled; + /* TCG of the current insn_start */ + TCGOp *insn_start; } DisasContext; static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -236,9 +238,6 @@ static void generate_exception_mtval(DisasContext *ctx, int excp) static void gen_exception_illegal(DisasContext *ctx) { - tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, - offsetof(CPURISCVState, bins)); - generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); } @@ -1017,6 +1016,13 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) /* Include decoders for factored-out extensions */ #include "decode-XVentanaCondOps.c.inc" +static inline void decode_save_opc(DisasContext *ctx, target_ulong opc) +{ + assert(ctx->insn_start != NULL); + tcg_set_insn_start_param(ctx->insn_start, 1, opc); + ctx->insn_start = NULL; +} + static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { /* @@ -1033,6 +1039,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) /* Check for compressed insn */ if (extract16(opcode, 0, 2) != 3) { + decode_save_opc(ctx, opcode); if (!has_ext(ctx, RVC)) { gen_exception_illegal(ctx); } else { @@ -1047,6 +1054,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) opcode32 = deposit32(opcode32, 16, 16, translator_lduw(env, &ctx->base, ctx->base.pc_next + 2)); + decode_save_opc(ctx, opcode32); ctx->opcode = opcode32; ctx->pc_succ_insn = ctx->base.pc_next + 4; @@ -1113,7 +1121,8 @@ static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0); + ctx->insn_start = tcg_last_op(); } static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) From patchwork Wed May 11 14:45:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12846272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21DEFC433EF for ; Wed, 11 May 2022 14:49:03 +0000 (UTC) Received: from localhost ([::1]:60140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1noneA-0004yB-3Z for qemu-devel@archiver.kernel.org; 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([171.76.113.90]) by smtp.gmail.com with ESMTPSA id x2-20020a170902820200b0015eafc485c8sm1958726pln.289.2022.05.11.07.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 07:46:41 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() Date: Wed, 11 May 2022 20:15:24 +0530 Message-Id: <20220511144528.393530-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220511144528.393530-1-apatel@ventanamicro.com> References: <20220511144528.393530-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel --- target/riscv/cpu_helper.c | 168 +++++++++++++++++++++++++++++++++++++- target/riscv/instmap.h | 41 ++++++++++ 2 files changed, 205 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d99fac9d2d..b24652eb8d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,6 +22,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/exec-all.h" +#include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" @@ -1318,6 +1319,158 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } #endif /* !CONFIG_USER_ONLY */ +static target_ulong riscv_transformed_insn(CPURISCVState *env, + target_ulong insn) +{ + target_ulong xinsn = 0; + + /* + * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to + * be uncompressed. The Quadrant 1 of RVC instruction space need + * not be transformed because these instructions won't generate + * any load/store trap. + */ + + if ((insn & 0x3) != 0x3) { + /* Transform 16bit instruction into 32bit instruction */ + switch (GET_C_OP(insn)) { + case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLD_LQ: + if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ + xinsn = OPC_RISC_FLD; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_I_IMM(xinsn, GET_C_LD_IMM(insn)); + } + break; + case OPC_RISC_C_FUNC_LW: /* C.LW */ + xinsn = OPC_RISC_LW; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_I_IMM(xinsn, GET_C_LW_IMM(insn)); + break; + case OPC_RISC_C_FUNC_FLW_LD: + if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ + xinsn = OPC_RISC_FLW; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_I_IMM(xinsn, GET_C_LW_IMM(insn)); + } else { /* C.LD (RV64/RV128) */ + xinsn = OPC_RISC_LD; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_I_IMM(xinsn, GET_C_LD_IMM(insn)); + } + break; + case OPC_RISC_C_FUNC_FSD_SQ: + if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ + xinsn = OPC_RISC_FSD; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_S_IMM(xinsn, GET_C_SD_IMM(insn)); + } + break; + case OPC_RISC_C_FUNC_SW: /* C.SW */ + xinsn = OPC_RISC_SW; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_S_IMM(xinsn, GET_C_SW_IMM(insn)); + break; + case OPC_RISC_C_FUNC_FSW_SD: + if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ + xinsn = OPC_RISC_FSW; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_S_IMM(xinsn, GET_C_SW_IMM(insn)); + } else { /* C.SD (RV64/RV128) */ + xinsn = OPC_RISC_SD; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_S_IMM(xinsn, GET_C_SD_IMM(insn)); + } + break; + default: + break; + } + break; + case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLDSP_LQSP: + if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ + xinsn = OPC_RISC_FLD; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_I_IMM(xinsn, GET_C_LDSP_IMM(insn)); + } + break; + case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ + xinsn = OPC_RISC_LW; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_I_IMM(xinsn, GET_C_LWSP_IMM(insn)); + break; + case OPC_RISC_C_FUNC_FLWSP_LDSP: + if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ + xinsn = OPC_RISC_FLW; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_I_IMM(xinsn, GET_C_LWSP_IMM(insn)); + } else { /* C.LDSP (RV64/RV128) */ + xinsn = OPC_RISC_LD; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_I_IMM(xinsn, GET_C_LDSP_IMM(insn)); + } + break; + case OPC_RISC_C_FUNC_FSDSP_SQSP: + if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ + xinsn = OPC_RISC_FSD; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_S_IMM(xinsn, GET_C_SDSP_IMM(insn)); + } + break; + case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ + xinsn = OPC_RISC_SW; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_S_IMM(xinsn, GET_C_SWSP_IMM(insn)); + break; + case 7: + if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ + xinsn = OPC_RISC_FSW; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_S_IMM(xinsn, GET_C_SWSP_IMM(insn)); + } else { /* C.SDSP (RV64/RV128) */ + xinsn = OPC_RISC_SD; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_S_IMM(xinsn, GET_C_SDSP_IMM(insn)); + } + break; + default: + break; + } + break; + default: + break; + } + + /* + * Clear Bit1 of transformed instruction to indicate that + * original insruction was a 16bit instruction + */ + xinsn &= ~((target_ulong)0x2); + } else { + /* No need to transform 32bit (or wider) instructions */ + xinsn = insn; + } + + return xinsn; +} + /* * Handle Traps * @@ -1340,6 +1493,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; uint64_t deleg = async ? env->mideleg : env->medeleg; target_ulong tval = 0; + target_ulong tinst = 0; target_ulong htval = 0; target_ulong mtval2 = 0; @@ -1355,18 +1509,22 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { - case RISCV_EXCP_INST_GUEST_PAGE_FAULT: case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_ADDR_MIS: - case RISCV_EXCP_INST_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: case RISCV_EXCP_STORE_AMO_ADDR_MIS: case RISCV_EXCP_LOAD_ACCESS_FAULT: case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: + write_gva = env->two_stage_lookup; + tval = env->badaddr; + tinst = riscv_transformed_insn(env, env->bins); + break; + case RISCV_EXCP_INST_GUEST_PAGE_FAULT: + case RISCV_EXCP_INST_ADDR_MIS: + case RISCV_EXCP_INST_ACCESS_FAULT: + case RISCV_EXCP_INST_PAGE_FAULT: write_gva = env->two_stage_lookup; tval = env->badaddr; break; @@ -1448,6 +1606,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->sepc = env->pc; env->stval = tval; env->htval = htval; + env->htinst = tinst; env->pc = (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S); @@ -1478,6 +1637,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mepc = env->pc; env->mtval = tval; env->mtval2 = mtval2; + env->mtinst = tinst; env->pc = (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h index 40b6d2b64d..f4ee686c78 100644 --- a/target/riscv/instmap.h +++ b/target/riscv/instmap.h @@ -316,6 +316,12 @@ enum { #define GET_RS2(inst) extract32(inst, 20, 5) #define GET_RD(inst) extract32(inst, 7, 5) #define GET_IMM(inst) sextract64(inst, 20, 12) +#define SET_RS1(inst, val) deposit32(inst, 15, 5, val) +#define SET_RS2(inst, val) deposit32(inst, 20, 5, val) +#define SET_RD(inst, val) deposit32(inst, 7, 5, val) +#define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val) +#define SET_S_IMM(inst, val) \ + deposit32(deposit32(inst, 7, 5, val), 25, 7, (val) >> 5) /* RVC decoding macros */ #define GET_C_IMM(inst) (extract32(inst, 2, 5) \ @@ -346,6 +352,8 @@ enum { | (extract32(inst, 5, 1) << 6)) #define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \ | (extract16(inst, 5, 2) << 6)) +#define GET_C_SW_IMM(inst) GET_C_LW_IMM(inst) +#define GET_C_SD_IMM(inst) GET_C_LD_IMM(inst) #define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \ | (extract32(inst, 11, 1) << 4) \ | (extract32(inst, 2, 1) << 5) \ @@ -366,4 +374,37 @@ enum { #define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3)) #define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3)) +#define GET_C_FUNC(inst) extract32(inst, 13, 3) +#define GET_C_OP(inst) extract32(inst, 0, 2) + +enum { + /* RVC Quadrants */ + OPC_RISC_C_OP_QUAD0 = 0x0, + OPC_RISC_C_OP_QUAD1 = 0x1, + OPC_RISC_C_OP_QUAD2 = 0x2 +}; + +enum { + /* RVC Quadrant 0 */ + OPC_RISC_C_FUNC_ADDI4SPN = 0x0, + OPC_RISC_C_FUNC_FLD_LQ = 0x1, + OPC_RISC_C_FUNC_LW = 0x2, + OPC_RISC_C_FUNC_FLW_LD = 0x3, + OPC_RISC_C_FUNC_FSD_SQ = 0x5, + OPC_RISC_C_FUNC_SW = 0x6, + OPC_RISC_C_FUNC_FSW_SD = 0x7 +}; + +enum { + /* RVC Quadrant 2 */ + OPC_RISC_C_FUNC_SLLI_SLLI64 = 0x0, + OPC_RISC_C_FUNC_FLDSP_LQSP = 0x1, + OPC_RISC_C_FUNC_LWSP = 0x2, + OPC_RISC_C_FUNC_FLWSP_LDSP = 0x3, + OPC_RISC_C_FUNC_JR_MV_EBREAK_JALR_ADD = 0x4, + OPC_RISC_C_FUNC_FSDSP_SQSP = 0x5, + OPC_RISC_C_FUNC_SWSP = 0x6, + OPC_RISC_C_FUNC_FSWSP_SDSP = 0x7 +}; + #endif From patchwork Wed May 11 14:45:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12846281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E65CC433EF for ; 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([171.76.113.90]) by smtp.gmail.com with ESMTPSA id x2-20020a170902820200b0015eafc485c8sm1958726pln.289.2022.05.11.07.46.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 07:46:46 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Frank Chang , Alistair Francis , Atish Patra Subject: [PATCH v2 5/8] target/riscv: Don't force update priv spec version to latest Date: Wed, 11 May 2022 20:15:25 +0530 Message-Id: <20220511144528.393530-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220511144528.393530-1-apatel@ventanamicro.com> References: <20220511144528.393530-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The riscv_cpu_realize() sets priv spec verion to v1.12 when it is when "env->priv_ver == 0" (i.e. default v1.10) because the enum value of priv spec v1.10 is zero. Due to above issue, the sifive_u machine will see priv spec v1.12 instead of priv spec v1.10. To fix this issue, we set latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Atish Patra Reviewed-by: Atish Patra --- target/riscv/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9a5be9732d..f3b61dfd63 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -169,6 +169,8 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } static void rv64_sifive_u_cpu_init(Object *obj) @@ -204,6 +206,8 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } static void rv32_sifive_u_cpu_init(Object *obj) @@ -509,7 +513,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); CPUClass *cc = CPU_CLASS(mcc); - int priv_version = 0; + int priv_version = -1; Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); @@ -533,10 +537,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (priv_version) { + if (priv_version >= PRIV_VERSION_1_10_0) { set_priv_version(env, priv_version); - } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_12_0); } if (cpu->cfg.mmu) { From patchwork Wed May 11 14:45:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12846283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8B94C433F5 for ; Wed, 11 May 2022 14:54:30 +0000 (UTC) Received: from localhost ([::1]:47958 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nonjR-0007Ft-OV for qemu-devel@archiver.kernel.org; Wed, 11 May 2022 10:54:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nonc7-0002M2-8v for qemu-devel@nongnu.org; Wed, 11 May 2022 10:46:55 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:44595) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nonc5-0001E7-Gq for qemu-devel@nongnu.org; Wed, 11 May 2022 10:46:54 -0400 Received: by mail-pj1-x1030.google.com with SMTP id c1-20020a17090a558100b001dca2694f23so2279096pji.3 for ; Wed, 11 May 2022 07:46:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1iSGUJg5LeK+SwRNsZyAMWnxdnzqHXlyp91PSTtCSdg=; b=Y/BxTS17kwZZ8UA81KmbddEexNP1tAOWEaFxhYU/JfRlf2kS+hpHUmRvPYAffBIAMu rHkih343wtV1hb0/sM4vyL8dEKWwZCmFQ4cJbj5SF9D3GstU7p0XToYEsHv+UJnQfxkz WXAQJrza7EjasBU+OApg+R5wo5RCMKBGDfmdfcWk2fW6fAj1dq5HRwdUS4la+QcKvft1 5zNhdM+krKRVqO4v4xvxWNBMICenRmr+G5XI9kDSuXuBPMWsxx3a32wS04DMWm9zD6Zj ti2bMupvXevRs2WxFHHl9U3ijB8tJBTVmBp/hDjj0yAbV2FN/q0jguVLL/vJjLkvBorX XzHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1iSGUJg5LeK+SwRNsZyAMWnxdnzqHXlyp91PSTtCSdg=; b=nSyKBJsdgRe4NUzni1m8P34aSmaRQBc1gyA7PJ3X82vlT6OkG3xNR5j0Y0pcOdZsz6 gwFWa+xJMixlTfDW05MsZJWyPP+Bjyba/2A3GVmAAvbgkFZTR4pj1SwdcUtXYY7rZJs0 Kd+mTtEXAKu6MpIpLjsQsfo8hyJPFWNjirRrX/jRZG2hw2mIRscitqpr3H5HkxfQsiBx //4wo9+jnTYunqdCWMapYs1C2RXujcXuRi41yvuEshR59eYEQgHiCycqGwt6z9ioybsQ 3qCYefcf31pdyfGpk6mOaymWmVq/17Ta1Wer0HVzdRwYkiP3M9T1DZra4vC6lGh2Pzyz Xyyw== X-Gm-Message-State: AOAM532PLo0ltuSnRYTkEgIoe843WdkckF8QZnOuyAMvhSruxghfMCMC 9DjAjz5F2C2RzR8nCuUS3wfvVA== X-Google-Smtp-Source: ABdhPJxU2d9qk9yRMUV1f1EJvXwvq0K0rPdZK85s/qi8KLPIVpJAa6Wt1BBH1JWYV7czFPVXA2H/pg== X-Received: by 2002:a17:902:d48d:b0:15e:a480:78b2 with SMTP id c13-20020a170902d48d00b0015ea48078b2mr25795028plg.19.1652280412200; Wed, 11 May 2022 07:46:52 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.113.90]) by smtp.gmail.com with ESMTPSA id x2-20020a170902820200b0015eafc485c8sm1958726pln.289.2022.05.11.07.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 07:46:51 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Frank Chang , Alistair Francis Subject: [PATCH v2 6/8] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher Date: Wed, 11 May 2022 20:15:26 +0530 Message-Id: <20220511144528.393530-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220511144528.393530-1-apatel@ventanamicro.com> References: <20220511144528.393530-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.") Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4d04b20d06..4a55c6a709 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -159,6 +159,9 @@ #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 +/* Machine Counter Setup */ +#define CSR_MCOUNTINHIBIT 0x320 + /* 32-bit only */ #define CSR_MSTATUSH 0x310 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2bf0a97196..e144ce7135 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3391,6 +3391,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, + [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_zero, write_ignore, + .min_priv_ver = PRIV_VERSION_1_11_0 }, [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, From patchwork Wed May 11 14:45:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12846282 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B669C433F5 for ; Wed, 11 May 2022 14:53:21 +0000 (UTC) Received: from localhost ([::1]:45114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1noniJ-0005LT-Rq for qemu-devel@archiver.kernel.org; Wed, 11 May 2022 10:53:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49008) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1noncB-0002Xl-GF for qemu-devel@nongnu.org; Wed, 11 May 2022 10:46:59 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:46924) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nonc9-0001G0-Tu for qemu-devel@nongnu.org; Wed, 11 May 2022 10:46:59 -0400 Received: by mail-pj1-x1031.google.com with SMTP id cq17-20020a17090af99100b001dc0386cd8fso2270837pjb.5 for ; Wed, 11 May 2022 07:46:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8aKYQlOfgr8kwzRZmB9IHhj7wjdwjcRTlkREKDsl0CY=; b=Filtk3IXaiT+bWGhkgi6gTE+KLYbyzVeOnPbq5wJC4EtZqvnaZ7+7Nz7oIeyR7fh+W LPYo+81K4sehGyb9XxWGRz99Sb5vNoRLidv8B6pthkaDtAmyd2aCOm1JNZvS0Wt9BI+C PtjzeYwBB0Me+plWOMRzLKCBbL3+4d900+mXy7iZ1yGAYVVKnFeOQnGolqldDE5uNXiP zt2XjFwxVnYvb7YZnlMm8IsJLBDwvRNVnu+l5sp0XAd1OhWlUHoW84ML9Prha44F4L9R e0IVe5RP0emlbM4HIoMmulv/sZs77EuJ9U7HrihAXDfCCf0/GD5Sa8573Z8u3Kt2jecL ac6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8aKYQlOfgr8kwzRZmB9IHhj7wjdwjcRTlkREKDsl0CY=; b=GvRXzW//KWSTzTyRuSSNSCoOoep903AmRXgq8nEiXL3uqcGC1hjWGK8zt0+SpWJfPs KUFL04iZzOeJIcoHdx2IEDWHywYkYKc5CiqV20cEQ7XqopZxFBEcPlZGJ+XnqZsNgQB1 zHAubwbw4lNiGOGeM08mEc2dk1ph/CZNiiLguSYrgR+hsUw78qy7tnnsTYSOXiCbF+hD jK4PtwzDaw7Zhj2vwb2en6bq3D4riQN9+l8vSjWoC/JduLpJ+i4H7JHi2e2KYH4GbKoQ 2UP2ZtBJM7nEDjxQTTF1eGQ/cFFuURLLzun6PX2gHD7cDhT2Dy6DzYQSgdUd3alkAKZ0 v+KQ== X-Gm-Message-State: AOAM533TyFlie4IpBq+ZWJMt5XY2TKqrAuO+ngOxaNwC+PbuSjlhnpTa kQpN8eUspFBy5oe47gCu7TfCbg== X-Google-Smtp-Source: ABdhPJyUYojtPApjLjgIHQ80yK2bCSIJKpzSwM02Vl8Qe/yZXfhsCentXDaswIKtsAjAk95wj/XjQA== X-Received: by 2002:a17:90b:30c3:b0:1dc:b6d7:58d3 with SMTP id hi3-20020a17090b30c300b001dcb6d758d3mr5718788pjb.172.1652280416536; Wed, 11 May 2022 07:46:56 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.113.90]) by smtp.gmail.com with ESMTPSA id x2-20020a170902820200b0015eafc485c8sm1958726pln.289.2022.05.11.07.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 07:46:55 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match Date: Wed, 11 May 2022 20:15:27 +0530 Message-Id: <20220511144528.393530-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220511144528.393530-1-apatel@ventanamicro.com> References: <20220511144528.393530-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We should disable extensions in riscv_cpu_realize() if minimum required priv spec version is not satisfied. This also ensures that machines with priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter extensions. Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the device tree") Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f3b61dfd63..25a4ba3e22 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -541,6 +541,40 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_priv_version(env, priv_version); } + /* Force disable extensions if priv spec version does not match */ + if (env->priv_ver < PRIV_VERSION_1_12_0) { + cpu->cfg.ext_h = false; + cpu->cfg.ext_v = false; + cpu->cfg.ext_zfh = false; + cpu->cfg.ext_zfhmin = false; + cpu->cfg.ext_zfinx = false; + cpu->cfg.ext_zhinx = false; + cpu->cfg.ext_zhinxmin = false; + cpu->cfg.ext_zdinx = false; + cpu->cfg.ext_zba = false; + cpu->cfg.ext_zbb = false; + cpu->cfg.ext_zbc = false; + cpu->cfg.ext_zbkb = false; + cpu->cfg.ext_zbkc = false; + cpu->cfg.ext_zbkx = false; + cpu->cfg.ext_zbs = false; + cpu->cfg.ext_zk = false; + cpu->cfg.ext_zkn = false; + cpu->cfg.ext_zknd = false; + cpu->cfg.ext_zkne = false; + cpu->cfg.ext_zknh = false; + cpu->cfg.ext_zkr = false; + cpu->cfg.ext_zks = false; + cpu->cfg.ext_zksed = false; + cpu->cfg.ext_zksh = false; + cpu->cfg.ext_zkt = false; + cpu->cfg.ext_zve32f = false; + cpu->cfg.ext_zve64f = false; + cpu->cfg.ext_svinval = false; + cpu->cfg.ext_svnapot = false; + cpu->cfg.ext_svpbmt = false; + } + if (cpu->cfg.mmu) { riscv_set_feature(env, RISCV_FEATURE_MMU); } From patchwork Wed May 11 14:45:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12846284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A982BC433F5 for ; Wed, 11 May 2022 14:54:37 +0000 (UTC) Received: from localhost ([::1]:48510 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nonjY-0007cN-Ka for qemu-devel@archiver.kernel.org; Wed, 11 May 2022 10:54:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49068) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1noncI-0002lN-UJ for qemu-devel@nongnu.org; Wed, 11 May 2022 10:47:06 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:41565) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1noncG-0001Iq-UZ for qemu-devel@nongnu.org; Wed, 11 May 2022 10:47:06 -0400 Received: by mail-pj1-x102f.google.com with SMTP id l20-20020a17090a409400b001dd2a9d555bso2323698pjg.0 for ; Wed, 11 May 2022 07:47:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZptIjeV5waNPqbOFw/xyPgubEKgJpD3XmAraBqSym9Q=; b=b9jEC1YAOrmvah5uCMh9Z8tq1mIcUoyZEfWmfzqYRIojx0OPVMAIEV+PFky/wBtxFz u0/nKHrjj532Ar9HWKFjZvfZ5ZbZHID14Ew6icO6DAamDQTe1WORHo/ZX2Ej7ggGwN8e jLyEDO8ywsUoV+vxsmjG+7ECN98LxYgh2TJmzomYX1W0f1Q2zYm+8WkyXCOrfvvouKy6 y3AxyLQxA6IYG/6xdHISxUa/b8Lu3jmULSGXM8fDD6sqen25rD1LwRivzVr5aimLGvs2 QYjf8HSwI6TRWH388z5+Qeg7T6rzPtXOywfe3ZQCm50CgMZ2u+gYaubQ+pHz9nHwD5Zf GBdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZptIjeV5waNPqbOFw/xyPgubEKgJpD3XmAraBqSym9Q=; b=G+uOwYtjjWQ+O2iCZKjCd0ar2k+YKNCvHmaOzEx34RxhabzdtY4Q7Qe97OOI+tdURQ ehoZ6p2x8drSGjgHf0d4n/xIX6P78KkFZPQuiJ7fZJ07N0aUv3I1RZdejaOkx8a5WeBb xyrgG8dvObrNneIhGYDI0SCOGfEz1XsGzUteYG75Rtjg2xPRgTIFcY0A5juGnuswQdQ+ 9cPF7tZJzsIrusEhMuOtyB8cXAqlRaMGkoV8Lc2BuU/n4LeuGY6JXOucC7nQs7q5OwQR H1ZspoujODfXYvJn7ByUovus5KiuXE02B7otFhJOjMu0Ax3lHeOXiSGB9UYiVsl+8S3u 4BYw== X-Gm-Message-State: AOAM531DQztDpvJlvQbXhzv2IgU5fougEfslA+2APtn5SWP2ALneFwHV xayz2/BC671xRXbB7biYcH9OzA== X-Google-Smtp-Source: ABdhPJyNMjymG2FSszqKzFZaxOGJov8rUL6gXLsv97IKSEK9UKk3zQ5B9EIooDp1SBBETqA190IExw== X-Received: by 2002:a17:903:22c1:b0:15e:c3b2:d632 with SMTP id y1-20020a17090322c100b0015ec3b2d632mr26362510plg.0.1652280420592; Wed, 11 May 2022 07:47:00 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.113.90]) by smtp.gmail.com with ESMTPSA id x2-20020a170902820200b0015eafc485c8sm1958726pln.289.2022.05.11.07.46.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 07:46:59 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v2 8/8] hw/riscv: virt: Fix interrupt parent for dynamic platform devices Date: Wed, 11 May 2022 20:15:28 +0530 Message-Id: <20220511144528.393530-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220511144528.393530-1-apatel@ventanamicro.com> References: <20220511144528.393530-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" When both APLIC and IMSIC are present in virt machine, the APLIC should be used as parent interrupt controller for dynamic platform devices. In case of multiple sockets, we should prefer interrupt controller of socket0 for dynamic platform devices. Fixes: 3029fab64309 ("hw/riscv: virt: Add support for generating platform FDT entries") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 3326f4db96..c576173815 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -478,10 +478,12 @@ static void create_fdt_socket_plic(RISCVVirtState *s, qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", plic_phandles[socket]); - platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, - memmap[VIRT_PLATFORM_BUS].base, - memmap[VIRT_PLATFORM_BUS].size, - VIRT_PLATFORM_BUS_IRQ); + if (!socket) { + platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, + memmap[VIRT_PLATFORM_BUS].base, + memmap[VIRT_PLATFORM_BUS].size, + VIRT_PLATFORM_BUS_IRQ); + } g_free(plic_name); @@ -561,11 +563,6 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); - platform_bus_add_all_fdt_nodes(mc->fdt, imsic_name, - memmap[VIRT_PLATFORM_BUS].base, - memmap[VIRT_PLATFORM_BUS].size, - VIRT_PLATFORM_BUS_IRQ); - g_free(imsic_name); /* S-level IMSIC node */ @@ -704,10 +701,12 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); - platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, - memmap[VIRT_PLATFORM_BUS].base, - memmap[VIRT_PLATFORM_BUS].size, - VIRT_PLATFORM_BUS_IRQ); + if (!socket) { + platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, + memmap[VIRT_PLATFORM_BUS].base, + memmap[VIRT_PLATFORM_BUS].size, + VIRT_PLATFORM_BUS_IRQ); + } g_free(aplic_name);