From patchwork Thu May 12 10:45:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12847529 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BB90C4167E for ; Thu, 12 May 2022 10:46:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352780AbiELKqR (ORCPT ); Thu, 12 May 2022 06:46:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352787AbiELKp6 (ORCPT ); Thu, 12 May 2022 06:45:58 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05F3A9FC6 for ; Thu, 12 May 2022 03:45:49 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id p10so8260386lfa.12 for ; Thu, 12 May 2022 03:45:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Sp0z0zbzm124r5VzMcThZA6X8OsGv4Biu665CesrsB8=; b=yHy8lDcaESw+p0BnPn5Wp8D+IXqpJLy+cudlOlL8rZlbcbrPYSwExMt3dNzEvQEoik kSYap/CQOsBLJCCGSWRfqEr1A+T3dH0U+iIWOJB1hxl9d+E71PC9CUbEHYwPEwWMvwwT I1DXyz262smDl19xwFJgEj80jS75/1fd3O+yiZcIHriA4+W/S2/P78lzCaWpsUDV5/Zv ZDp/2XL7vSoDXgzsj0hwiNFkhDBrnbWWkQKEhcVQyKhVvHTI1El8gTCejTas2JgrFHGz B+5sTdR46jLZPbpx1upviZmXycW7yFZr72Q/Ps4ZxJJ4K571+7g+2O/TJz9FYWEyD4hw /bjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Sp0z0zbzm124r5VzMcThZA6X8OsGv4Biu665CesrsB8=; b=AU0riQQBtqSbsHxm/jQD4kDQDzHq2xS/FKh6WZIjGb2xbMi2t4qL5QAuioC6dk/Yx+ jZ7zcZ2XRw9Jh58B9Z2EVy8SZvMbrRiEGvIjqndvMOqkttdlAyqdTiZe+7+gutlxEhbo jb4zhpEXSwi36zQUhbh9nSUv2NF982t4Cdrm95zFWgE4ZHwwUnX4YfhrUngOhlcghwQq vPBjZ+L1XwptDVQBXh2bX+zFoRxYovZsQAPZjUthvTgxMni+b7H1id14MdQ0TiV5wE3y zI+Rs5ei4hFhAzx1b9T3HvBKJBBLmG2lexR3Jll6Ykc403zQ0bVF+kB3HqrYW/10NbuJ wn2A== X-Gm-Message-State: AOAM530tF8EzNmGXFTWcceIJ2xxnTDTm+nghkZdxltu1q/OGrt8zc6ZS 4gICl046/jR9lof4wawzgOc3t16rnoz26w== X-Google-Smtp-Source: ABdhPJzBpQHNvP4008PtJVbgzpPEj2bON4D+wPPw5TC2qmcWG8mUhSWcM4scaj6nAOn5L+oCfczt7g== X-Received: by 2002:a05:6512:b07:b0:473:c26a:7095 with SMTP id w7-20020a0565120b0700b00473c26a7095mr23941683lfu.603.1652352347236; Thu, 12 May 2022 03:45:47 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q21-20020a2e9695000000b0024f3d1daeafsm831660lji.55.2022.05.12.03.45.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 03:45:46 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v8 01/10] PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" Date: Thu, 12 May 2022 13:45:36 +0300 Message-Id: <20220512104545.2204523-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org I have replied with my Tested-by to the patch at [2], which has landed in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: Add support for handling MSIs from 8 endpoints"). However lately I noticed that during the tests I still had 'pcie_pme=nomsi', so the device was not forced to use higher MSI vectors. After removing this option I noticed that high MSI vectors are not delivered on tested platforms. Additional research pointed to a patch in msm-4.14 ([1]), which describes that each group of MSI vectors is mapped to the separate interrupt. Without these changes specifying num_vectors can lead to missing MSI interrupts and thus to devices malfunction. Fixes: 20f1bfb8dd62 ("PCI: qcom: Add support for handling MSIs from 8 endpoints") Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index f9a61ad6d1f0..2e5464edc36e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1587,7 +1587,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) pci->dev = dev; pci->ops = &dw_pcie_ops; pp = &pci->pp; - pp->num_vectors = MAX_MSI_IRQS; pcie->pci = pci; From patchwork Thu May 12 10:45:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12847537 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20318C4321E for ; Thu, 12 May 2022 10:46:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352823AbiELKqa (ORCPT ); Thu, 12 May 2022 06:46:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352790AbiELKp6 (ORCPT ); Thu, 12 May 2022 06:45:58 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5251B45 for ; Thu, 12 May 2022 03:45:49 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id j4so8289364lfh.8 for ; Thu, 12 May 2022 03:45:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BBuu5KSSAl4LgdXTiciqOI62Z3+Z2tFwbFLkIDaMs1E=; b=irBM/I9sHiUXGDXRMw1EdRafCUofbpC6G5pKcBqlmJNrO3qWXV8A1vYDueazLYn2Tv CkLO29FJDBwoRRdgOAAsNL/h8t4fE0BQq1pXFIhlpM1n9RlXMhYUp/HCGaDUbrp6eyXt o/Tro3NI09h0XDeI0SBa85bFiIsXHNexUiJ3i59v2DvU3AVQamPZ/sQWMhxgSpGQdR9U 5xd1FrOPTy3ZK7xibutPB8N+QAisB5Ii144R4XkXAnZumBoGi5ATvEzATS1UzJZ+nEV6 OzwINkLDFtfsjvB55M2v8pWpWnCnDrHcePzJG+F4T5URDzjyoArR6fxKPLRXF3DugZVU qAgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BBuu5KSSAl4LgdXTiciqOI62Z3+Z2tFwbFLkIDaMs1E=; b=gTTMo2aUOZ1Yjj1A1iNq5/vZhXSeF88ClUKmco140MQsBv/cVXGi6+axtRfvKs81qr 4kwdWhbzlf+4cKc35Mpffi9QfXoCn8ZcyDe/Fgw7cSOMvP6y0O+wYu9PbojvIkSPjKHU 5vRWhHraKk9p3caEXeAraZwb2im7YjoZ8Uc3rnY5Dv4HdUXtcSdaQgZbLBQK2JIOswiI dPVSu5b/S0Hb6VQZ9J7A/0dT7gCPt4CAZhSkqFBjH3PjtlLEGo33Yo+KgEphMHOHS3NA qNvQACfAKwYpZW2nVyTl+V38DmJSX5C1v3t9U+XL7BdH9pNqNoBUWUODf3KerhVacTTK tgGg== X-Gm-Message-State: AOAM533YRZTr7cpIugzfj9xEGihm+VHvabbyTOk6aFWKrx6KzChlAAkH jvPMM2kaajxY7ghMoBmivwuNoA== X-Google-Smtp-Source: ABdhPJzEp0I958fl8aU2s5ysmp7q3dJCsrRANv9uYbwx+lhxmDFQsXYBWlOk9dFvlfMygJHyCBbSHQ== X-Received: by 2002:a05:6512:38a1:b0:475:9fee:b42d with SMTP id o1-20020a05651238a100b004759feeb42dmr40007lft.237.1652352348078; Thu, 12 May 2022 03:45:48 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q21-20020a2e9695000000b0024f3d1daeafsm831660lji.55.2022.05.12.03.45.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 03:45:47 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v8 02/10] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Date: Thu, 12 May 2022 13:45:37 +0300 Message-Id: <20220512104545.2204523-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The subdrivers pass -ESOMETHING if they do not want the core to touch MSI IRQ. dw_pcie_host_init() also checks if (msi_irq > 0) rather than just if (msi_irq). So let's make dw_pcie_free_msi() also check that msi_irq is greater than zero. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 2fa86f32d964..43d1d6116007 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -257,7 +257,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) static void dw_pcie_free_msi(struct pcie_port *pp) { - if (pp->msi_irq) + if (pp->msi_irq > 0) irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); irq_domain_remove(pp->msi_domain); From patchwork Thu May 12 10:45:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12847538 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B1F5C433EF for ; Thu, 12 May 2022 10:47:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241206AbiELKr4 (ORCPT ); Thu, 12 May 2022 06:47:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352793AbiELKp6 (ORCPT ); Thu, 12 May 2022 06:45:58 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6E7A631D for ; Thu, 12 May 2022 03:45:50 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id p10so8260495lfa.12 for ; Thu, 12 May 2022 03:45:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7Vzy2HaNwmiHrbRZfzP7ND8CKiJmDIZ1xiUpYxqHa28=; b=V4nx2EMo0EKrSj/PAbX9S4Qp/6WaeCcPQf0JyPDJZM+7o2WNyIv8DJz6EB4KRBtfSr OWaSbPYSJNkmyZKm93+/pTgGQT3hbh+EguGEP8zFmlpGCts2rZd1aqoJWHQ7w3KNBRAv vCzel3iaM4OmRjQwY0lFrLPUc49WDz5YvlEbi+PPd+rrpOr0/95zPKfx66LcTpsk+z9q zzkOfRoKtzU0pNvZXiXnoiFWh7WZ2b7oYwL72vwVGLayYM5ADHrGQjBjOPf2U5to530P Vmam8Cn3D4A2p9l7uB5Fi1GpE4Uv3+FO+/gU9SyqUcwCYtBTZYV+D1Gc3C52Yxq9PMJo b8fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7Vzy2HaNwmiHrbRZfzP7ND8CKiJmDIZ1xiUpYxqHa28=; b=MtKEGln3SmOTniuCITOzstWG3mRN+4WTsBj7CHiCB6n6U6ZJGYHxQw21tXNz5nVYZB 2pDFhbyAy0GG16aYXk9RC40KfVhwBjf/Fw8mX+9AQl+HPSAOdipqinaYXejjCo1RzjPi zA2lcb63jmJ51ZTZWhNw1ZVEEaJldPRNVwFxca1wSB6szhaXJiKDufjgxPsSanzn8rUo eZ4poDm0ISV6LTriVLFd8GQdmYwJnCiGx5rbLzyUqQ86VHKoyS+en7c1t3FYJnQkMJXl G99We4L1TQabxzW8KnJEcqbnNrhReGNPR7JrKWK38qTxEFtDAb2wMzEoGxFEsmlzELK0 UzIw== X-Gm-Message-State: AOAM530lyVZy1HuLkzUsAQv07C7233o13njXnV8KYd8G1hEFt/Llks+r dGZjaMEvcabgwo1Bqw3d1moMoA== X-Google-Smtp-Source: ABdhPJzGZjt2YCZKtKRyUCQd2SBMz0k6irOvY2/9FcXKIBjteb2vL5SBREw2GA49ZSfb/RHqoITp8A== X-Received: by 2002:a05:6512:3e11:b0:473:9f5f:feda with SMTP id i17-20020a0565123e1100b004739f5ffedamr22874872lfv.244.1652352348913; Thu, 12 May 2022 03:45:48 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q21-20020a2e9695000000b0024f3d1daeafsm831660lji.55.2022.05.12.03.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 03:45:48 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 03/10] PCI: dwc: Convert msi_irq to the array Date: Thu, 12 May 2022 13:45:38 +0300 Message-Id: <20220512104545.2204523-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Qualcomm version of DWC PCIe controller supports more than 32 MSI interrupts, but they are routed to separate interrupts in groups of 32 vectors. To support such configuration, change the msi_irq field into an array. Let the DWC core handle all interrupts that were set in this array. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pci-exynos.c | 2 +- .../pci/controller/dwc/pcie-designware-host.c | 30 +++++++++++-------- drivers/pci/controller/dwc/pcie-designware.h | 2 +- drivers/pci/controller/dwc/pcie-keembay.c | 2 +- drivers/pci/controller/dwc/pcie-spear13xx.c | 2 +- drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 7 files changed, 24 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index dfcdeb432dc8..0919c96dcdbd 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -483,7 +483,7 @@ static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, return pp->irq; /* MSI IRQ is muxed */ - pp->msi_irq = -ENODEV; + pp->msi_irq[0] = -ENODEV; ret = dra7xx_pcie_init_irq_domain(pp); if (ret < 0) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c index 467c8d1cd7e4..4f2010bd9cd7 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -292,7 +292,7 @@ static int exynos_add_pcie_port(struct exynos_pcie *ep, } pp->ops = &exynos_pcie_host_ops; - pp->msi_irq = -ENODEV; + pp->msi_irq[0] = -ENODEV; ret = dw_pcie_host_init(pp); if (ret) { diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 43d1d6116007..0d4f35c7560e 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -257,8 +257,11 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) static void dw_pcie_free_msi(struct pcie_port *pp) { - if (pp->msi_irq > 0) - irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); + u32 ctrl; + + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) + if (pp->msi_irq[ctrl] > 0) + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], NULL, NULL); irq_domain_remove(pp->msi_domain); irq_domain_remove(pp->irq_domain); @@ -368,13 +371,15 @@ int dw_pcie_host_init(struct pcie_port *pp) for (ctrl = 0; ctrl < num_ctrls; ctrl++) pp->irq_mask[ctrl] = ~0; - if (!pp->msi_irq) { - pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi"); - if (pp->msi_irq < 0) { - pp->msi_irq = platform_get_irq(pdev, 0); - if (pp->msi_irq < 0) - return pp->msi_irq; + if (!pp->msi_irq[0]) { + int irq = platform_get_irq_byname_optional(pdev, "msi"); + + if (irq < 0) { + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; } + pp->msi_irq[0] = irq; } pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; @@ -383,10 +388,11 @@ int dw_pcie_host_init(struct pcie_port *pp) if (ret) return ret; - if (pp->msi_irq > 0) - irq_set_chained_handler_and_data(pp->msi_irq, - dw_chained_msi_isr, - pp); + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + if (pp->msi_irq[ctrl] > 0) + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], + dw_chained_msi_isr, + pp); ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 7d6e9b7576be..9c1a38b0a6b3 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -187,7 +187,7 @@ struct pcie_port { u32 io_size; int irq; const struct dw_pcie_host_ops *ops; - int msi_irq; + int msi_irq[MAX_MSI_CTRLS]; struct irq_domain *irq_domain; struct irq_domain *msi_domain; u16 msi_msg; diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c index 1ac29a6eef22..297e6e926c00 100644 --- a/drivers/pci/controller/dwc/pcie-keembay.c +++ b/drivers/pci/controller/dwc/pcie-keembay.c @@ -338,7 +338,7 @@ static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie, int ret; pp->ops = &keembay_pcie_host_ops; - pp->msi_irq = -ENODEV; + pp->msi_irq[0] = -ENODEV; ret = keembay_pcie_setup_msi_irq(pcie); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c index 1569e82b5568..cc7776833810 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -172,7 +172,7 @@ static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie, } pp->ops = &spear13xx_pcie_host_ops; - pp->msi_irq = -ENODEV; + pp->msi_irq[0] = -ENODEV; ret = dw_pcie_host_init(pp); if (ret) { diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index b1b5f836a806..e75712db85b0 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2271,7 +2271,7 @@ static void tegra194_pcie_shutdown(struct platform_device *pdev) disable_irq(pcie->pci.pp.irq); if (IS_ENABLED(CONFIG_PCI_MSI)) - disable_irq(pcie->pci.pp.msi_irq); + disable_irq(pcie->pci.pp.msi_irq[0]); tegra194_pcie_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); From patchwork Thu May 12 10:45:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12847530 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7717C3527B for ; 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Thu, 12 May 2022 03:45:49 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 04/10] PCI: dwc: Propagate error from dma_mapping_error() Date: Thu, 12 May 2022 13:45:39 +0300 Message-Id: <20220512104545.2204523-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org If dma mapping fails, dma_mapping_error() will return an error. Propagate it to the dw_pcie_host_init() return value rather than incorrectly returning 0 in this case. Fixes: 07940c369a6b ("PCI: dwc: Fix MSI page leakage in suspend/resume") Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-designware-host.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 0d4f35c7560e..5f6590929319 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -402,8 +402,9 @@ int dw_pcie_host_init(struct pcie_port *pp) sizeof(pp->msi_msg), DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); - if (dma_mapping_error(pci->dev, pp->msi_data)) { - dev_err(pci->dev, "Failed to map MSI data\n"); + ret = dma_mapping_error(pci->dev, pp->msi_data); + if (ret) { + dev_err(pci->dev, "Failed to map MSI data: %d\n", ret); pp->msi_data = 0; goto err_free_msi; } From patchwork Thu May 12 10:45:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12847533 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C53FBC46467 for ; Thu, 12 May 2022 10:46:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352817AbiELKqV (ORCPT ); Thu, 12 May 2022 06:46:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352806AbiELKp7 (ORCPT ); Thu, 12 May 2022 06:45:59 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D52C6555 for ; Thu, 12 May 2022 03:45:51 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id bq30so8322497lfb.3 for ; Thu, 12 May 2022 03:45:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3wF9YjekVvBPStMNtaaCYjUE+D1MeDx6T+Vgrs7ULxM=; b=PTURU6LD1Dd/2fC0HgsiAqIybmcPY6A4vl/FAOMBGMdi3EtzdDKl6VGMxaZHj/nQcw xLc/UW1bcxmrvkA9oEGi4WKJ8tdt9laI11pQeQU6NZBWb6ZmsnXkjEn6H/ceuFs0OTv5 lOA2jW2uV/JoSfpZhN8ymZlq7TRW2mt5rMpPiX+NRLlpFYAPVxyn2wo9qND/UTyuGZ3c vfLpoeu6tYH0C5hBYdU+hxEa4f7CKqQ/zv5kn81TEtt/zbdqakOjH5PC4tDZCO+JdXm0 gP6jiXO2GV1XC9CWIZD0AMdET+akmVAt42joN3WonomyW3m7eTiTsRs41Hy2aGl9Az+f bS1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3wF9YjekVvBPStMNtaaCYjUE+D1MeDx6T+Vgrs7ULxM=; b=R9GG3BLtA5eEr1luSNUnCHlrFtx0P3RIj9ISXhqMdMFToX+3au9dj9EZ6PWFYK07JN H/T4wht+tQteON2VBDRJhUz0aQtxyWwabh5zQpPgfL6opzqqKh2xzneT/edLnSD4TjDa AbsE5Htotheva9X5XAxxi6QgM9pAVBqpNahtGzanmcIuu9EuzQxG8UnnGhPStD2NWr/v vvuuhYc9jH18DNvhFDxH/mcJPB4qW9MkddapEBeTkUHsmVGXb0l19ovFE6GeBmIDKx9p 8L1OpR9ec9hWwSW1GV0it7andnCS2cG3TC/Vi98Uok8xbFCnNTfHPtxjBo6xHlipxX0M QCww== X-Gm-Message-State: AOAM533n0gcYz+ZrWpVqSTJuejM7IJSaNShLNl9Q/cSaQNXxZ+GCDNe6 DCIIBzVQoIA9ExPML3x4/bSeTw== X-Google-Smtp-Source: ABdhPJwM88XVMOaQoSLikx5hnEIB5r1T5RsQHlc0QWhLeZWw2GbojxDDTRAGB4OuEI/ZZpOpxl2rSg== X-Received: by 2002:a05:6512:3184:b0:472:6042:7c2b with SMTP id i4-20020a056512318400b0047260427c2bmr24294977lfe.606.1652352350302; Thu, 12 May 2022 03:45:50 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q21-20020a2e9695000000b0024f3d1daeafsm831660lji.55.2022.05.12.03.45.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 03:45:50 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 05/10] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Date: Thu, 12 May 2022 13:45:40 +0300 Message-Id: <20220512104545.2204523-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init() function. The code is complex enough to warrant a separte function. Adding another bit to support multiple host MSI IRQs would make it overcomplicated. Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 97 +++++++++++-------- 1 file changed, 55 insertions(+), 42 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 5f6590929319..6b0c7b75391f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -288,6 +288,59 @@ static void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } +static int dw_pcie_msi_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct platform_device *pdev = to_platform_device(pci->dev); + int ret; + u32 ctrl, num_ctrls; + + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + pp->irq_mask[ctrl] = ~0; + + if (!pp->msi_irq[0]) { + int irq = platform_get_irq_byname_optional(pdev, "msi"); + + if (irq < 0) { + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + } + pp->msi_irq[0] = irq; + } + + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + + ret = dw_pcie_allocate_domains(pp); + if (ret) + return ret; + + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + if (pp->msi_irq[ctrl] > 0) + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], + dw_chained_msi_isr, + pp); + + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); + if (ret) + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); + + pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, + sizeof(pp->msi_msg), + DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(pci->dev, pp->msi_data); + if (ret) { + dev_err(pci->dev, "Failed to map MSI data: %d\n", ret); + pp->msi_data = 0; + dw_pcie_free_msi(pp); + return ret; + } + + return 0; +} + int dw_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -365,49 +418,9 @@ int dw_pcie_host_init(struct pcie_port *pp) if (ret < 0) return ret; } else if (pp->has_msi_ctrl) { - u32 ctrl, num_ctrls; - - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - for (ctrl = 0; ctrl < num_ctrls; ctrl++) - pp->irq_mask[ctrl] = ~0; - - if (!pp->msi_irq[0]) { - int irq = platform_get_irq_byname_optional(pdev, "msi"); - - if (irq < 0) { - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - } - pp->msi_irq[0] = irq; - } - - pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; - - ret = dw_pcie_allocate_domains(pp); - if (ret) + ret = dw_pcie_msi_host_init(pp); + if (ret < 0) return ret; - - for (ctrl = 0; ctrl < num_ctrls; ctrl++) - if (pp->msi_irq[ctrl] > 0) - irq_set_chained_handler_and_data(pp->msi_irq[ctrl], - dw_chained_msi_isr, - pp); - - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); - if (ret) - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); - - pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, - sizeof(pp->msi_msg), - DMA_FROM_DEVICE, - DMA_ATTR_SKIP_CPU_SYNC); - ret = dma_mapping_error(pci->dev, pp->msi_data); - if (ret) { - dev_err(pci->dev, "Failed to map MSI data: %d\n", ret); - pp->msi_data = 0; - goto err_free_msi; - } } } From patchwork Thu May 12 10:45:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12847531 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 718A6C352AA for ; Thu, 12 May 2022 10:46:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352795AbiELKqT (ORCPT ); Thu, 12 May 2022 06:46:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352815AbiELKqA (ORCPT ); Thu, 12 May 2022 06:46:00 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D83BE0C7 for ; Thu, 12 May 2022 03:45:53 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id l19so5951091ljb.7 for ; Thu, 12 May 2022 03:45:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xqH3lMsIdJoyn/K/QdA0FeBPly9c4ZNuS3iENff/SNc=; b=RPZDYcGtFCRcUKdxgQMpvumyPKuxmmW5leF4ZiZSH4XauoQako7anGJYzFJNnPuOMr DZJVPtXi923JLpmUSAHJsqBi+h7MqOUZtdDcaHtRBgGtkiBZuneqTxm2DOVsYC/1/D+g Cqwuq7lckiQ5XCOiRjgrDXNLhlwLa7H8eV5X358M2jZdtpMXORtfJwkyNl4dyE1NLjP9 MHDlqA6rlG1lF7UEax8BHlapM2/yJaVy34YXJZNAMCkzfYqBK+AMhP/tvCN+6ae6J7fA 2649AskWKErSvmD7uhmERIPgkZqJ7DvtETc6Pjzq7ZXPe1liyS1Y2Y95il7/Ov9z7PZF 1gBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xqH3lMsIdJoyn/K/QdA0FeBPly9c4ZNuS3iENff/SNc=; b=3o5sizFQoq4Fp8q+R2xLxuUTxQMn/NUArpJIg+xTcxmR7g7u20cxZsFvRMIwoVuIsQ 87Z19Z4hOpsIsOHfVfkqI8KXlCL3f8kLpkInPTn8K74jKCBkR5fpebx8W3Cl4SxujC10 Xki2RJD4bft10GClHrAcOKwC63IYFK1rXUvCmHt7ABNkoszqN8ORIVwFvY7zHJqy9xng aZBYPaHtyQWOmjbLi/gogFBoy/z7rtFtYVC/rl9BbPEh5N/l2SAzt+iqlBmMg4uKcpeK pUwYDixTZneyi02ItryT+CAPGNL/e4N6W4J638BsO1eti9HKo9o2Ttn23mlSicEsI6OH Kraw== X-Gm-Message-State: AOAM532mSaBdnGa3XGZLpGWW5qJHVcQONaWfijYpOCFUWxMWwGdMSHTJ P5DXH3Up/vFLf4VYERwHwpIb+BuEVEH/6g== X-Google-Smtp-Source: ABdhPJwOsmW27eNFpS6JDpKruKlgEVsG/Q3fheqYkd4h7U954k0Bh4umlOnIt0mQD6V//CRVBfyfbg== X-Received: by 2002:a2e:8e84:0:b0:24f:1d40:ceb0 with SMTP id z4-20020a2e8e84000000b0024f1d40ceb0mr20910905ljk.292.1652352350928; Thu, 12 May 2022 03:45:50 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q21-20020a2e9695000000b0024f3d1daeafsm831660lji.55.2022.05.12.03.45.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 03:45:50 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 06/10] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Date: Thu, 12 May 2022 13:45:41 +0300 Message-Id: <20220512104545.2204523-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On some of Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Implement support for such configuraions by parsing "msi0" ... "msi7" interrupts and attaching them to the chained handler. Note, that if DT doesn't list an array of MSI interrupts and uses single "msi" IRQ, the driver will limit the amount of supported MSI vectors accordingly (to 32). Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 33 ++++++++++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 6b0c7b75391f..258bafa306dc 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -291,7 +291,8 @@ static void dw_pcie_msi_init(struct pcie_port *pp) static int dw_pcie_msi_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct platform_device *pdev = to_platform_device(pci->dev); + struct device *dev = pci->dev; + struct platform_device *pdev = to_platform_device(dev); int ret; u32 ctrl, num_ctrls; @@ -299,6 +300,36 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp) for (ctrl = 0; ctrl < num_ctrls; ctrl++) pp->irq_mask[ctrl] = ~0; + if (pp->has_split_msi_irq) { + char irq_name[] = "msiXX"; + int irq; + + if (!pp->msi_irq[0]) { + irq = platform_get_irq_byname_optional(pdev, irq_name); + if (irq == -ENXIO) { + num_ctrls = 1; + pp->num_vectors = min((u32)MAX_MSI_IRQS_PER_CTRL, pp->num_vectors); + dev_warn(dev, "No additional MSI IRQs, limiting amount of MSI vectors to %d\n", + pp->num_vectors); + } else { + pp->msi_irq[0] = irq; + } + } + + /* If we fallback to the single MSI ctrl IRQ, this loop will be skipped as num_ctrls is 1 */ + for (ctrl = 1; ctrl < num_ctrls; ctrl++) { + if (pp->msi_irq[ctrl]) + continue; + + snprintf(irq_name, sizeof(irq_name), "msi%d", ctrl); + irq = platform_get_irq_byname(pdev, irq_name); + if (irq < 0) + return irq; + + pp->msi_irq[ctrl] = irq; + } + } + if (!pp->msi_irq[0]) { int irq = platform_get_irq_byname_optional(pdev, "msi"); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 9c1a38b0a6b3..3aa840a5b19c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -179,6 +179,7 @@ struct dw_pcie_host_ops { struct pcie_port { bool has_msi_ctrl:1; + bool has_split_msi_irq:1; u64 cfg0_base; void __iomem *va_cfg0_base; u32 cfg0_size; From patchwork Thu May 12 10:45:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12847536 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADA84C4332F for ; Thu, 12 May 2022 10:46:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352819AbiELKq1 (ORCPT ); Thu, 12 May 2022 06:46:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352824AbiELKqA (ORCPT ); Thu, 12 May 2022 06:46:00 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA30F10FEC for ; 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Thu, 12 May 2022 03:45:51 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q21-20020a2e9695000000b0024f3d1daeafsm831660lji.55.2022.05.12.03.45.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 03:45:51 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 07/10] PCI: qcom: Handle MSIs routed to multiple GIC interrupts Date: Thu, 12 May 2022 13:45:42 +0300 Message-Id: <20220512104545.2204523-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On some of Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Thus, to receive higher MSI vectors properly, declare that the host should use split MSI IRQ handling on these platforms. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2e5464edc36e..f79752d1d680 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -194,6 +194,7 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; + unsigned int has_split_msi_irq:1; unsigned int pipe_clk_need_muxing:1; unsigned int has_tbu_clk:1; unsigned int has_ddrss_sf_tbu_clk:1; @@ -1502,6 +1503,7 @@ static const struct qcom_pcie_cfg ipq8064_cfg = { static const struct qcom_pcie_cfg msm8996_cfg = { .ops = &ops_2_3_2, + .has_split_msi_irq = true, }; static const struct qcom_pcie_cfg ipq8074_cfg = { @@ -1514,6 +1516,7 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { static const struct qcom_pcie_cfg sdm845_cfg = { .ops = &ops_2_7_0, + .has_split_msi_irq = true, .has_tbu_clk = true, }; @@ -1526,12 +1529,14 @@ static const struct qcom_pcie_cfg sm8150_cfg = { static const struct qcom_pcie_cfg sm8250_cfg = { .ops = &ops_1_9_0, + .has_split_msi_irq = true, .has_tbu_clk = true, .has_ddrss_sf_tbu_clk = true, }; static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { .ops = &ops_1_9_0, + .has_split_msi_irq = true, .has_ddrss_sf_tbu_clk = true, .pipe_clk_need_muxing = true, .has_aggre0_clk = true, @@ -1540,6 +1545,7 @@ static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { .ops = &ops_1_9_0, + .has_split_msi_irq = true, .has_ddrss_sf_tbu_clk = true, .pipe_clk_need_muxing = true, .has_aggre1_clk = true, @@ -1547,6 +1553,7 @@ static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, + .has_split_msi_irq = true, .has_tbu_clk = true, .pipe_clk_need_muxing = true, }; @@ -1592,6 +1599,11 @@ static int qcom_pcie_probe(struct platform_device *pdev) pcie->cfg = pcie_cfg; + if (pcie->cfg->has_split_msi_irq) { + pp->num_vectors = MAX_MSI_IRQS; + pp->has_split_msi_irq = true; + } + pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); if (IS_ERR(pcie->reset)) { ret = PTR_ERR(pcie->reset); From patchwork Thu May 12 10:45:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12847532 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18A7BC43217 for ; Thu, 12 May 2022 10:46:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243226AbiELKqU (ORCPT ); Thu, 12 May 2022 06:46:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352817AbiELKqA (ORCPT ); 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Thu, 12 May 2022 03:45:52 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 08/10] PCI: dwc: Implement special ISR handler for split MSI IRQ setup Date: Thu, 12 May 2022 13:45:43 +0300 Message-Id: <20220512104545.2204523-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org If the PCIe DWC controller uses split MSI IRQs for reporting MSI vectors, it is possible to detect, which group triggered the interrupt. Provide an optimized version of MSI ISR handler that will handle just a single MSI group instead of handling all of them. Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 83 ++++++++++++++----- 1 file changed, 62 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 258bafa306dc..b1b8d924ea8c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -52,34 +52,42 @@ static struct msi_domain_info dw_pcie_msi_domain_info = { .chip = &dw_pcie_msi_irq_chip, }; +static inline irqreturn_t dw_handle_single_msi_group(struct pcie_port *pp, int i) +{ + int pos; + unsigned long val; + u32 status; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + + (i * MSI_REG_CTRL_BLOCK_SIZE)); + if (!status) + return IRQ_NONE; + + val = status; + pos = 0; + while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, + pos)) != MAX_MSI_IRQS_PER_CTRL) { + generic_handle_domain_irq(pp->irq_domain, + (i * MAX_MSI_IRQS_PER_CTRL) + + pos); + pos++; + } + + return IRQ_HANDLED; +} + /* MSI int handler */ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) { - int i, pos; - unsigned long val; - u32 status, num_ctrls; + int i; + u32 num_ctrls; irqreturn_t ret = IRQ_NONE; - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - for (i = 0; i < num_ctrls; i++) { - status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + - (i * MSI_REG_CTRL_BLOCK_SIZE)); - if (!status) - continue; - - ret = IRQ_HANDLED; - val = status; - pos = 0; - while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, - pos)) != MAX_MSI_IRQS_PER_CTRL) { - generic_handle_domain_irq(pp->irq_domain, - (i * MAX_MSI_IRQS_PER_CTRL) + - pos); - pos++; - } - } + for (i = 0; i < num_ctrls; i++) + ret |= dw_handle_single_msi_group(pp, i); return ret; } @@ -98,6 +106,38 @@ static void dw_chained_msi_isr(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static void dw_split_msi_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + int irq = irq_desc_get_irq(desc); + struct pcie_port *pp; + int i; + u32 num_ctrls; + struct dw_pcie *pci; + + chained_irq_enter(chip, desc); + + pp = irq_desc_get_handler_data(desc); + pci = to_dw_pcie_from_pp(pp); + + /* + * Unlike generic dw_handle_msi_irq(), we can determine which group of + * MSIs triggered the IRQ, so process just that group. + */ + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + for (i = 0; i < num_ctrls; i++) { + if (pp->msi_irq[i] == irq) { + dw_handle_single_msi_group(pp, i); + break; + } + } + + WARN_ON_ONCE(i == num_ctrls); + + chained_irq_exit(chip, desc); +} + static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct pcie_port *pp = irq_data_get_irq_chip_data(d); @@ -350,6 +390,7 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp) for (ctrl = 0; ctrl < num_ctrls; ctrl++) if (pp->msi_irq[ctrl] > 0) irq_set_chained_handler_and_data(pp->msi_irq[ctrl], + pp->has_split_msi_irq ? dw_split_msi_isr : dw_chained_msi_isr, pp); From patchwork Thu May 12 10:45:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12847534 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E30EC433EF for ; Thu, 12 May 2022 10:46:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352829AbiELKqY (ORCPT ); Thu, 12 May 2022 06:46:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352818AbiELKqA (ORCPT ); Thu, 12 May 2022 06:46:00 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBB2712ADC for ; Thu, 12 May 2022 03:45:55 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id m23so6007158ljc.0 for ; Thu, 12 May 2022 03:45:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HYUuQ4fR4SBZdSuM6IAnUnoggotKrAQZZIhO70s2q7Y=; b=AI85gBhV83QDzlTqzRBGdsoUBihIpwwhPVRMB4CW6beKtsgIVT6XXsICRIh5STiXUu uj2M5iqfyFYsTe0u/w4LgGb6dLr5pYaS3qXJNRc+H6gf4Y3jSoFfLkbZ7OJbyDSk4Pgo aXf4SJDfQyHdaX2jLjLSgwI8z1uyPGXSskEUObgrF67Kq6oiUQCo4DSYskpEJLSRKtWQ klBldhv0VV6svTU1t4bhN7MrBJHrF2OjBKFiES87FiX9wQD+aWf1dnUPXpOmt/4sXXws PWOdmushnyirUUTxllzccd6AeFxTJSZG1BcDj4WHymTj+thLkSP7HrALyAr/QN14AbGS io0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HYUuQ4fR4SBZdSuM6IAnUnoggotKrAQZZIhO70s2q7Y=; b=dUbzU9C9IFPOIKiRnfG5rnYB8C692lp167xuDztURIjhWJMM/zbLEBcTXFNzInu9t/ pwNoFBHWIc+eTbLOhlTQLYJtOtxIuvoRSASnjW7AdtgUs/yOa1/tuxymONiImUYBQHeG glAVld0GpcQB/o9tQ7aYx+/rOzARwQzb/efFihhMqJBFNKpw0RDkwDuGL91eUINwL34M XdtjhfDUNz6B9M5sXeZp+2+C33//85IYqoOp9d0sfqla+S6pDbqrtu36ifgyH3a+CtiA MuTM4E/dlLwFoEB6CwCkFY9Tc5cdTLJBZL1BQXrKOQ43CsgCgXqzFxi7tAbH1HljEEub r62Q== X-Gm-Message-State: AOAM531QJ0QZXwyl0cYVBq/5yMe7CjUY93KSbudKgNZ2Luh7x5cSbEd+ Md8MainAZip0WRqpI3up3lREkA== X-Google-Smtp-Source: ABdhPJzPor8TdDJcn8mGSUdKJQz7zY6//R7YZZKN7pVdivQ230Ba4iZ6E3PC8j9iImLdqUkr7dBVXQ== X-Received: by 2002:a2e:bd83:0:b0:24e:fe7b:7235 with SMTP id o3-20020a2ebd83000000b0024efe7b7235mr20276619ljq.409.1652352353242; Thu, 12 May 2022 03:45:53 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q21-20020a2e9695000000b0024f3d1daeafsm831660lji.55.2022.05.12.03.45.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 03:45:52 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v8 09/10] dt-bindings: PCI: qcom: Support additional MSI interrupts Date: Thu, 12 May 2022 13:45:44 +0300 Message-Id: <20220512104545.2204523-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Document mapping of additional interrupts. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie.yaml | 53 +++++++++++++++++-- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 0b69b12b849e..fe8f9a62a665 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -43,11 +43,12 @@ properties: maxItems: 5 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 interrupt-names: - items: - - const: msi + minItems: 1 + maxItems: 8 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. @@ -623,6 +624,52 @@ allOf: - resets - reset-names + # On newer chipsets support either 1 or 8 msi interrupts + # On older chipsets it's always 1 msi interrupt + - if: + properties: + compatibles: + contains: + enum: + - qcom,pcie-msm8996 + - qcom,pcie-sc7280 + - qcom,pcie-sc8180x + - qcom,pcie-sdm845 + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + then: + oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + items: + - const: msi + - properties: + interrupts: + minItems: 8 + interrupt-names: + minItems: 8 + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + unevaluatedProperties: false examples: From patchwork Thu May 12 10:45:45 2022 Content-Type: text/plain; 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Thu, 12 May 2022 03:45:54 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q21-20020a2e9695000000b0024f3d1daeafsm831660lji.55.2022.05.12.03.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 03:45:53 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 10/10] arm64: dts: qcom: sm8250: provide additional MSI interrupts Date: Thu, 12 May 2022 13:45:45 +0300 Message-Id: <20220512104545.2204523-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On SM8250 each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe0 host. Tested on Qualcomm RB5 platform with first group of MSI interrupts being used by the PME and attached ath11k WiFi chip using second group of MSI interrupts. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 410272a1e19b..ef683a2f7412 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1807,8 +1807,15 @@ pcie0: pci@1c00000 { ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */