From patchwork Fri May 13 12:34:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liang Yang X-Patchwork-Id: 12848766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1FFC8C433EF for ; Fri, 13 May 2022 12:35:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aJjsvfuWLj+FotMm6CjvGI8GNHsJc3OFnZ6NHZj5qNo=; b=P5SNFeI3Xghu80 pSNsRDXTyP/hPBuNsUnyJHE1T+HP6gqd1ME9RaoeN3IMSafdpX89pnA19ZTo+X81aC2sGme+nyLC6 uCG2s0AEUtXOXkxRz9JRZblSEPWNaTQvrpJQBzh1PllCHeeHODmbUCWKcBlbBamQo+2BILs99SURq 2KVEert9sv985jZsBLokclVH4wNaAFYJEASGtwbIC/12m4UT1TmopQPyv1SB5+miO5ztjVkRXzppN NZdxtbjpdlowF9abKgIpX64jAtla4zYzCKO2TmAiZpBAR1K6oOsm7lil1VwUc8h509uggFLFyY0xG 5layUDXN9fgYXkw+JDzQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1npUVV-00G2vw-UE; Fri, 13 May 2022 12:34:58 +0000 Received: from mail-sz.amlogic.com ([211.162.65.117]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1npUUq-00G2Sp-34; Fri, 13 May 2022 12:34:17 +0000 Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Fri, 13 May 2022 20:32:46 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , , Subject: [PATCH v5 1/4] dt-bindings: nand: meson: fix meson nfc clock Date: Fri, 13 May 2022 20:34:01 +0800 Message-ID: <20220513123404.48513-2-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220513123404.48513-1-liang.yang@amlogic.com> References: <20220513123404.48513-1-liang.yang@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.8.21] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220513_053416_151844_28C2BE4C X-CRM114-Status: GOOD ( 10.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org EMMC and NAND have the same clock control register named 'SD_EMMC_CLOCK' which is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider and bit6~7 is the mux for fix pll and xtal. At the beginning, a common MMC and NAND sub-clock was discussed and planed to be implemented as NFC clock provider, but now this series of patches of a common MMC and NAND sub-clock are never being accepted and the current binding was never valid. the reasons are: 1. EMMC and NAND, which are mutually exclusive anyway 2. coupling the EMMC and NAND. 3. it seems that a common MMC and NAND sub-clock is over engineered. and let us see the link for more information: https://lore.kernel.org/all/20220121074508.42168-5-liang.yang@amlogic.com so The meson nfc can't work now, let us rework the clock. Signed-off-by: Liang Yang Acked-by: Rob Herring --- .../bindings/mtd/amlogic,meson-nand.txt | 29 ++++++++----------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt index 5794ab1147c1..5d5cdfef417f 100644 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt @@ -7,18 +7,19 @@ Required properties: - compatible : contains one of: - "amlogic,meson-gxl-nfc" - "amlogic,meson-axg-nfc" + +- reg : Offset and length of the register set + +- reg-names : "nfc" is the register set for NFC controller and "emmc" + is the register set for MCI controller. + - clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names. - clock-names: Should contain the following: "core" - NFC module gate clock - "device" - device clock from eMMC sub clock controller - "rx" - rx clock phase - "tx" - tx clock phase - -- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC - controller port C + "device" - parent clock for internal NFC Optional children nodes: Children nodes represent the available nand chips. @@ -28,24 +29,18 @@ see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindi Example demonstrate on AXG SoC: - sd_emmc_c_clkc: mmc@7000 { - compatible = "amlogic,meson-axg-mmc-clkc", "syscon"; - reg = <0x0 0x7000 0x0 0x800>; - }; - nand-controller@7800 { compatible = "amlogic,meson-axg-nfc"; - reg = <0x0 0x7800 0x0 0x100>; + reg = <0x0 0x7800 0x0 0x100>, + <0x0 0x7000 0x0 0x800>; + reg-names = "nfc", "emmc"; #address-cells = <1>; #size-cells = <0>; interrupts = ; clocks = <&clkc CLKID_SD_EMMC_C>, - <&sd_emmc_c_clkc CLKID_MMC_DIV>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>; - clock-names = "core", "device", "rx", "tx"; - amlogic,mmc-syscon = <&sd_emmc_c_clkc>; + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "device"; pinctrl-names = "default"; pinctrl-0 = <&nand_pins>; From patchwork Fri May 13 12:34:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liang Yang X-Patchwork-Id: 12848767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13713C433EF for ; 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Fri, 13 May 2022 12:35:13 +0000 Received: from mail-sz.amlogic.com ([211.162.65.117]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1npUUs-00G2Sp-CY; Fri, 13 May 2022 12:34:20 +0000 Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Fri, 13 May 2022 20:32:48 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , Subject: [PATCH v5 2/4] mtd: rawnand: meson: fix the clock Date: Fri, 13 May 2022 20:34:02 +0800 Message-ID: <20220513123404.48513-3-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220513123404.48513-1-liang.yang@amlogic.com> References: <20220513123404.48513-1-liang.yang@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.8.21] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220513_053418_479033_FA51C60D X-CRM114-Status: GOOD ( 17.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org EMMC and NAND have the same clock control register named 'SD_EMMC_CLOCK' which is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider and bit6~7 is the mux for fix pll and xtal. At the beginning, a common MMC and NAND sub-clock was discussed and planed to be implemented as NFC clock provider, but now this series of patches of a common MMC and NAND sub-clock are never being accepted. the reasons for giving up are: 1. EMMC and NAND, which are mutually exclusive anyway 2. coupling the EMMC and NAND. 3. it seems that a common MMC and NAND sub-clock is over engineered. and let us see the link fot more information: https://lore.kernel.org/all/20220121074508.42168-5-liang.yang@amlogic.com so The meson nfc can't work now, let us rework the clock. Signed-off-by: Liang Yang Reported-by: kernel test robot Reviewed-by: Kevin Hilman --- drivers/mtd/nand/raw/meson_nand.c | 82 +++++++++++++++---------------- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c index ac3be92872d0..cc93667a1e7f 100644 --- a/drivers/mtd/nand/raw/meson_nand.c +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -56,6 +57,9 @@ #define NFC_RB_IRQ_EN BIT(21) +#define CLK_DIV_SHIFT 0 +#define CLK_DIV_WIDTH 6 + #define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \ ( \ (cmd_dir) | \ @@ -151,15 +155,15 @@ struct meson_nfc { struct nand_controller controller; struct clk *core_clk; struct clk *device_clk; - struct clk *phase_tx; - struct clk *phase_rx; + struct clk *nand_clk; + struct clk_divider nand_divider; unsigned long clk_rate; u32 bus_timing; struct device *dev; void __iomem *reg_base; - struct regmap *reg_clk; + void __iomem *reg_clk; struct completion completion; struct list_head chips; const struct meson_nfc_data *data; @@ -235,7 +239,7 @@ static void meson_nfc_select_chip(struct nand_chip *nand, int chip) nfc->timing.tbers_max = meson_chip->tbers_max; if (nfc->clk_rate != meson_chip->clk_rate) { - ret = clk_set_rate(nfc->device_clk, meson_chip->clk_rate); + ret = clk_set_rate(nfc->nand_clk, meson_chip->clk_rate); if (ret) { dev_err(nfc->dev, "failed to set clock rate\n"); return; @@ -987,6 +991,8 @@ static const struct mtd_ooblayout_ops meson_ooblayout_ops = { static int meson_nfc_clk_init(struct meson_nfc *nfc) { + struct clk_parent_data nfc_divider_parent_data[1]; + struct clk_init_data init = {0}; int ret; /* request core clock */ @@ -1002,21 +1008,28 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) return PTR_ERR(nfc->device_clk); } - nfc->phase_tx = devm_clk_get(nfc->dev, "tx"); - if (IS_ERR(nfc->phase_tx)) { - dev_err(nfc->dev, "failed to get TX clk\n"); - return PTR_ERR(nfc->phase_tx); - } - - nfc->phase_rx = devm_clk_get(nfc->dev, "rx"); - if (IS_ERR(nfc->phase_rx)) { - dev_err(nfc->dev, "failed to get RX clk\n"); - return PTR_ERR(nfc->phase_rx); - } + init.name = devm_kasprintf(nfc->dev, + GFP_KERNEL, "%s#div", + dev_name(nfc->dev)); + init.ops = &clk_divider_ops; + nfc_divider_parent_data[0].fw_name = "device"; + init.parent_data = nfc_divider_parent_data; + init.num_parents = 1; + nfc->nand_divider.reg = nfc->reg_clk; + nfc->nand_divider.shift = CLK_DIV_SHIFT; + nfc->nand_divider.width = CLK_DIV_WIDTH; + nfc->nand_divider.hw.init = &init; + nfc->nand_divider.flags = CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ROUND_CLOSEST | + CLK_DIVIDER_ALLOW_ZERO; + + nfc->nand_clk = devm_clk_register(nfc->dev, &nfc->nand_divider.hw); + if (IS_ERR(nfc->nand_clk)) + return PTR_ERR(nfc->nand_clk); /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ - regmap_update_bits(nfc->reg_clk, - 0, CLK_SELECT_NAND, CLK_SELECT_NAND); + writel(CLK_SELECT_NAND | readl(nfc->reg_clk), + nfc->reg_clk); ret = clk_prepare_enable(nfc->core_clk); if (ret) { @@ -1030,29 +1043,21 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) goto err_device_clk; } - ret = clk_prepare_enable(nfc->phase_tx); + ret = clk_prepare_enable(nfc->nand_clk); if (ret) { - dev_err(nfc->dev, "failed to enable TX clock\n"); - goto err_phase_tx; + dev_err(nfc->dev, "pre enable NFC divider fail\n"); + goto err_nand_clk; } - ret = clk_prepare_enable(nfc->phase_rx); - if (ret) { - dev_err(nfc->dev, "failed to enable RX clock\n"); - goto err_phase_rx; - } - - ret = clk_set_rate(nfc->device_clk, 24000000); + ret = clk_set_rate(nfc->nand_clk, 24000000); if (ret) - goto err_disable_rx; + goto err_disable_clk; return 0; -err_disable_rx: - clk_disable_unprepare(nfc->phase_rx); -err_phase_rx: - clk_disable_unprepare(nfc->phase_tx); -err_phase_tx: +err_disable_clk: + clk_disable_unprepare(nfc->nand_clk); +err_nand_clk: clk_disable_unprepare(nfc->device_clk); err_device_clk: clk_disable_unprepare(nfc->core_clk); @@ -1061,8 +1066,7 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) static void meson_nfc_disable_clk(struct meson_nfc *nfc) { - clk_disable_unprepare(nfc->phase_rx); - clk_disable_unprepare(nfc->phase_tx); + clk_disable_unprepare(nfc->nand_clk); clk_disable_unprepare(nfc->device_clk); clk_disable_unprepare(nfc->core_clk); } @@ -1396,13 +1400,9 @@ static int meson_nfc_probe(struct platform_device *pdev) if (IS_ERR(nfc->reg_base)) return PTR_ERR(nfc->reg_base); - nfc->reg_clk = - syscon_regmap_lookup_by_phandle(dev->of_node, - "amlogic,mmc-syscon"); - if (IS_ERR(nfc->reg_clk)) { - dev_err(dev, "Failed to lookup clock base\n"); + nfc->reg_clk = devm_platform_ioremap_resource_byname(pdev, "emmc"); + if (IS_ERR(nfc->reg_clk)) return PTR_ERR(nfc->reg_clk); - } irq = platform_get_irq(pdev, 0); if (irq < 0) From patchwork Fri May 13 12:34:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liang Yang X-Patchwork-Id: 12848768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99990C433EF for ; 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Fri, 13 May 2022 12:35:52 +0000 Received: from mail-sz.amlogic.com ([211.162.65.117]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1npUUv-00G2Sp-HL; Fri, 13 May 2022 12:34:22 +0000 Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Fri, 13 May 2022 20:32:50 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , Subject: [PATCH v5 3/4] mtd: rawnand: meson: refine resource getting in probe Date: Fri, 13 May 2022 20:34:03 +0800 Message-ID: <20220513123404.48513-4-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220513123404.48513-1-liang.yang@amlogic.com> References: <20220513123404.48513-1-liang.yang@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.8.21] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220513_053421_622274_42A3D252 X-CRM114-Status: UNSURE ( 9.05 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Signed-off-by: Liang Yang Reviewed-by: Neil Armstrong Reviewed-by: Kevin Hilman --- drivers/mtd/nand/raw/meson_nand.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c index cc93667a1e7f..6e50387475bb 100644 --- a/drivers/mtd/nand/raw/meson_nand.c +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -1378,7 +1378,6 @@ static int meson_nfc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct meson_nfc *nfc; - struct resource *res; int ret, irq; nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); @@ -1395,8 +1394,7 @@ static int meson_nfc_probe(struct platform_device *pdev) nfc->dev = dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - nfc->reg_base = devm_ioremap_resource(dev, res); + nfc->reg_base = devm_platform_ioremap_resource_byname(pdev, "nfc"); if (IS_ERR(nfc->reg_base)) return PTR_ERR(nfc->reg_base); From patchwork Fri May 13 12:34:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liang Yang X-Patchwork-Id: 12848769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C1CEC433F5 for ; Fri, 13 May 2022 12:37:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rEDYGoiBpFQcpM71soPH0eOSz30pfkoY7Ky+/V5+rLY=; b=VHgV59bZiAZFAM jSaz59/uOu0/7uso0tGy/JBslj0jc9WJdD57XqxBpnzxdE3asF480oPlJrE12gZ+7NGoH039u179x pRdiUCizy/lGMfo8ORlqgj4JZ22DRBU2jRxNdiKG7et7w6tM4Ulkp2kTAAe0F5IjFY6eE2us+XhGF KU0ycigym01CLLCqyMPAy49awObA7Iq2xDIDYi/CxN2iSPAYF1ZFFv4LFfx4Iy5zWSR8yYVUjVTwl VsbvVcwB4V7I4iFGD5eSHniqf2Fm91CnI7RHOI/TaS8FeLi/8tS7CPtr5baMnmSDYtFJZWnWJ+Lm0 i6JF1PH2xQ3t1gXbSSqA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1npUWZ-00G3j3-Ra; Fri, 13 May 2022 12:36:03 +0000 Received: from mail-sz.amlogic.com ([211.162.65.117]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1npUUx-00G2Sp-D3; Fri, 13 May 2022 12:34:26 +0000 Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Fri, 13 May 2022 20:32:53 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , Subject: [PATCH v5 4/4] dt-bindings: nand: meson: convert txt to yaml Date: Fri, 13 May 2022 20:34:04 +0800 Message-ID: <20220513123404.48513-5-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220513123404.48513-1-liang.yang@amlogic.com> References: <20220513123404.48513-1-liang.yang@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.8.21] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220513_053423_520906_F89FCA18 X-CRM114-Status: GOOD ( 14.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Signed-off-by: Liang Yang --- .../bindings/mtd/amlogic,meson-nand.txt | 55 ------------ .../bindings/mtd/amlogic,meson-nand.yaml | 88 +++++++++++++++++++ 2 files changed, 88 insertions(+), 55 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt deleted file mode 100644 index 5d5cdfef417f..000000000000 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt +++ /dev/null @@ -1,55 +0,0 @@ -Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs - -This file documents the properties in addition to those available in -the MTD NAND bindings. - -Required properties: -- compatible : contains one of: - - "amlogic,meson-gxl-nfc" - - "amlogic,meson-axg-nfc" - -- reg : Offset and length of the register set - -- reg-names : "nfc" is the register set for NFC controller and "emmc" - is the register set for MCI controller. - -- clocks : - A list of phandle + clock-specifier pairs for the clocks listed - in clock-names. - -- clock-names: Should contain the following: - "core" - NFC module gate clock - "device" - parent clock for internal NFC - -Optional children nodes: -Children nodes represent the available nand chips. - -Other properties: -see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings. - -Example demonstrate on AXG SoC: - - nand-controller@7800 { - compatible = "amlogic,meson-axg-nfc"; - reg = <0x0 0x7800 0x0 0x100>, - <0x0 0x7000 0x0 0x800>; - reg-names = "nfc", "emmc"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "device"; - - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins>; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - nand-on-flash-bbt; - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml new file mode 100644 index 000000000000..42634e9c0d3c --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs + +allOf: + - $ref: "nand-controller.yaml" + +maintainers: + - liang.yang@amlogic.com + +properties: + compatible: + enum: + - "amlogic,meson-gxl-nfc" + - "amlogic,meson-axg-nfc" + + reg: + maxItems: 2 + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + + clock-names: + items: + - const: core + - const: device + +patternProperties: + "^nand@[0-7]$": + type: object + properties: + reg: + minimum: 0 + maximum: 1 + + nand-ecc-mode: + const: hw + + nand-ecc-step-size: + const: 1024 + + nand-ecc-strength: + enum: [8, 16, 24, 30, 40, 50, 60] + description: | + The ECC configurations that can be supported are as follows. + meson-gxl-nfc 8, 16, 24, 30, 40, 50, 60 + meson-axg-nfc 8 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + nand-controller@ffe07800 { + compatible = "amlogic,meson-axg-nfc"; + reg = <0xffe07800 0x100>, <0xffe07000 0x800>; + reg-names = "nfc", "emmc"; + interrupts = ; + clocks = <&clkc CLKID_SD_EMMC_C>, <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "device"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + }; + }; + +...