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[89.14.181.123]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b006f3ef214e3esm953874ejc.164.2022.05.13.10.54.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 10:54:57 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Bernhard Beschow , =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Aurelien Jarno , "Michael S. Tsirkin" , Marcel Apfelbaum Subject: [PATCH 1/6] include/hw: Move TYPE_PIIX4_PCI_DEVICE to southbridge/piix.h Date: Fri, 13 May 2022 19:54:40 +0200 Message-Id: <20220513175445.89616-2-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220513175445.89616-1-shentey@gmail.com> References: <20220513175445.89616-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=shentey@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" TYPE_PIIX3_PCI_DEVICE resides there as well. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland --- include/hw/isa/isa.h | 2 -- include/hw/southbridge/piix.h | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h index 034d706ba1..e9fa2f5cea 100644 --- a/include/hw/isa/isa.h +++ b/include/hw/isa/isa.h @@ -144,6 +144,4 @@ static inline ISABus *isa_bus_from_device(ISADevice *d) return ISA_BUS(qdev_get_parent_bus(DEVICE(d))); } -#define TYPE_PIIX4_PCI_DEVICE "piix4-isa" - #endif diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index f63f83e5c6..a304fc6041 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -70,6 +70,8 @@ typedef struct PIIXState PIIX3State; DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, TYPE_PIIX3_PCI_DEVICE) +#define TYPE_PIIX4_PCI_DEVICE "piix4-isa" + PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus); DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus); From patchwork Fri May 13 17:54:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12849194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1FCBDC433F5 for ; Fri, 13 May 2022 17:59:24 +0000 (UTC) Received: from localhost ([::1]:45494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1npZZT-0006cQ-8m for qemu-devel@archiver.kernel.org; Fri, 13 May 2022 13:59:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53406) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1npZVG-0008Am-N5; Fri, 13 May 2022 13:55:02 -0400 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:36790) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1npZVE-0004jL-C9; Fri, 13 May 2022 13:55:02 -0400 Received: by mail-ej1-x62b.google.com with SMTP id z2so17691668ejj.3; Fri, 13 May 2022 10:54:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CrxtAcaTGjuEUtnIiGymO3XGo8jE/fdwJXlC8ObcJxA=; b=QHLPNPYDQ89UyjPg5Bw679LR8mm+8wQM4JC8MbIrmQ9uO3xzTfoNZ+vKnE7kPZCBrb 5d0oI63RH2NsakIH+9a4T48rBqINRdRIHcuQguBxRlJ6rdLBg3B8eJOO5pRNqEU5C+2u A3+0E3cpOB/CcCAmRDPSswweog0jGD/0s3vPAwaDy6dtz9GU04CAB85WmhfxdsIJwJG7 eGMZpr5nnan10yD3tF5LwVNBTuDgOn7uTJGhBYFVeJoF11ZMrolx9wgiBRbhfN9qUHc3 GZz7SxoutkweM1oJF1AQHzwe+CpCAowsKd/C1gWGWj07nlNTHVnoR+Yle6oM9fhAqOvp 3Mqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CrxtAcaTGjuEUtnIiGymO3XGo8jE/fdwJXlC8ObcJxA=; b=s2e+3Q8fmdVWG/yO/7mqBf9JfBYMJFE1TWJTg69lFZ7nuXjUSZ+KQO6Ol5mLMZa3nK iJU0pbamxpYsV/4tQv1oUyoW3+X6SiSL9kNc8IgEtW1BMSoY1yAD0k0nQGSIsmYsQt62 NtyXgmU/KAPEKdJT+lVxnbArzGwUU/Kei5Zn3XT2quPA4NxlF/IXmTrVGqytsvtoZInV e3tjM5JPwCgtJaf9B95dPmHY3fI23UA+qMwz738+9PUaJ6WyUra2EZ2hZ7Mve2uyKEYD gsl2gDuzWG7Thm94m6a/j9805kU/pBOgU4NK93gagHvOEARqmWkigesnu/f3HK6+OeGA YCdA== X-Gm-Message-State: AOAM530brQzEy1niKTQ5MPRxyn7DqBYpJWAWqo+B8s/dnjXgs+OSM2xm uN4yTI0uMNEwHQNRx7IR5ukHZUZbTw0= X-Google-Smtp-Source: ABdhPJx/nzHCRWL86SlTyX6pKQ59KMS9KKQqj7NV9wT/W65/Io1eW8NPvatZ7Si8wxcz1a7M9TZ0jw== X-Received: by 2002:a17:907:7745:b0:6f3:674a:339 with SMTP id kx5-20020a170907774500b006f3674a0339mr5219857ejc.207.1652464498541; Fri, 13 May 2022 10:54:58 -0700 (PDT) Received: from Provence.localdomain (dynamic-089-014-181-123.89.14.pool.telefonica.de. [89.14.181.123]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b006f3ef214e3esm953874ejc.164.2022.05.13.10.54.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 10:54:58 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Bernhard Beschow , "Michael S. Tsirkin" , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Aurelien Jarno , =?utf-8?q?Herv=C3=A9_Poussineau?= Subject: [PATCH 2/6] hw/isa/piix{3, 4}: Move pci_map_irq_fn's near pci_set_irq_fn's Date: Fri, 13 May 2022 19:54:41 +0200 Message-Id: <20220513175445.89616-3-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220513175445.89616-1-shentey@gmail.com> References: <20220513175445.89616-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=shentey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The pci_map_irq_fn's were implemented below type_init() which made them inaccessible to QOM functions. So move them up. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland --- hw/isa/piix3.c | 22 +++++++++++----------- hw/isa/piix4.c | 50 +++++++++++++++++++++++++------------------------- 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index dab901c9ad..7d69420967 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -81,6 +81,17 @@ static void piix3_set_irq(void *opaque, int pirq, int level) piix3_set_irq_level(piix3, pirq, level); } +/* + * Return the global irq number corresponding to a given device irq + * pin. We could also use the bus number to have a more precise mapping. + */ +static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) +{ + int slot_addend; + slot_addend = PCI_SLOT(pci_dev->devfn) - 1; + return (pci_intx + slot_addend) & 3; +} + static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIX3State *piix3 = opaque; @@ -353,17 +364,6 @@ static void piix3_register_types(void) type_init(piix3_register_types) -/* - * Return the global irq number corresponding to a given device irq - * pin. We could also use the bus number to have a more precise mapping. - */ -static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) -{ - int slot_addend; - slot_addend = PCI_SLOT(pci_dev->devfn) - 1; - return (pci_intx + slot_addend) & 3; -} - PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus) { PIIX3State *piix3; diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 8607e0ac36..a223b69e24 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -73,6 +73,31 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) } } +static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) +{ + int slot; + + slot = PCI_SLOT(pci_dev->devfn); + + switch (slot) { + /* PIIX4 USB */ + case 10: + return 3; + /* AMD 79C973 Ethernet */ + case 11: + return 1; + /* Crystal 4281 Sound */ + case 12: + return 2; + /* PCI slot 1 to 4 */ + case 18 ... 21: + return ((slot - 18) + irq_num) & 0x03; + /* Unknown device, don't do any translation */ + default: + return irq_num; + } +} + static void piix4_isa_reset(DeviceState *dev) { PIIX4State *d = PIIX4_PCI_DEVICE(dev); @@ -265,31 +290,6 @@ static void piix4_register_types(void) type_init(piix4_register_types) -static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) -{ - int slot; - - slot = PCI_SLOT(pci_dev->devfn); - - switch (slot) { - /* PIIX4 USB */ - case 10: - return 3; - /* AMD 79C973 Ethernet */ - case 11: - return 1; - /* Crystal 4281 Sound */ - case 12: - return 2; - /* PCI slot 1 to 4 */ - case 18 ... 21: - return ((slot - 18) + irq_num) & 0x03; - /* Unknown device, don't do any translation */ - default: - return irq_num; - } -} - DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) { PIIX4State *s; From patchwork Fri May 13 17:54:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12849192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0778C433EF for ; Fri, 13 May 2022 17:58:18 +0000 (UTC) Received: from localhost ([::1]:41400 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1npZYN-0003qc-GR for qemu-devel@archiver.kernel.org; Fri, 13 May 2022 13:58:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1npZVI-0008EC-Ln; Fri, 13 May 2022 13:55:04 -0400 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]:42773) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1npZVF-0004jU-Jo; Fri, 13 May 2022 13:55:03 -0400 Received: by mail-ej1-x632.google.com with SMTP id i27so17640443ejd.9; Fri, 13 May 2022 10:55:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9fyFY+E6JJjVdT5p/+Wp03gGdDkS94wyw4n8PQHDYiA=; b=qsWemKgHXO+hXoAyiTh5Lcy91eu0qBEOGnMF1dlqZNZqp1rQ9ptihyJwL7MZ84qvQ3 OaCGZNyGkMC0bENwhc+AMjd3sQOzL6RatBprHqpiaWjHqHOy0T6l7iRKK7nLBQTbli0Y gGTOTBZKIT7D+0+OWJ+2B/XwnXmuljMsO36LEgspATuUZ2/Yb5XB99LK4FX2f5i996Ff 2ehQBnbvb58EfiqZI8m6Hj3FqH8ATBXH1OJJ9qcm7jg/pTfkTrSlotjXgqLo7gSrrwO7 w6w0bLj6VOnHnPdj5mE1pnODdF/N7ylXhJ7/bS+u9sm0jNyjb6tBnjLm0myW7v4LYeen Vsqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9fyFY+E6JJjVdT5p/+Wp03gGdDkS94wyw4n8PQHDYiA=; b=dsF60M6R8zcpgp+P4rtuRgApYaVcq0yXs/3Ui5SVrmrWC7qDsuieTA1lJJ5ytCngRb tSeS4XPp/X5KIL8VzVSW4yiDuB+3XEn6a+E7CmpHVtP/CDpiQOGduc6NDSxftlu3IYoP tchvR9TbjYklb6/BnAevDwaCOuyqe3NuoCAubdO6zVQXtyvlhKOyFVyfoZMOBcTsszkq tXok9m3yE0ke7glSOwVBwr2bZxHAHE/XCwYmKRfC0hi1kKzLYdN2Tk/jTLl10gEyqxjA V9IS0aZcTWNYRHrWzkVefrn2RGtltgEchw52kiH2mVzo08tsrau2Z6+tL+EfLbzNF4Vl GWVA== X-Gm-Message-State: AOAM533UOEQPo+89Wa72PBSQPfZZDoyT9PpYNXOcYkKscpLhmG+zH3AZ Pgfmnyor/a6osYNNG6jpyuVXKO25GPU= X-Google-Smtp-Source: ABdhPJwkZ9ghJLzaakaY3NvWYMmn7TMqV1AKuxwiTNTXCx+8BsavE5NlC4dGZVb50yqOXL1zP2hytA== X-Received: by 2002:a17:907:6088:b0:6f4:bc5b:ab3c with SMTP id ht8-20020a170907608800b006f4bc5bab3cmr5332056ejc.236.1652464499471; Fri, 13 May 2022 10:54:59 -0700 (PDT) Received: from Provence.localdomain (dynamic-089-014-181-123.89.14.pool.telefonica.de. [89.14.181.123]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b006f3ef214e3esm953874ejc.164.2022.05.13.10.54.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 10:54:59 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Bernhard Beschow , "Michael S. Tsirkin" , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Aurelien Jarno , =?utf-8?q?Herv=C3=A9_Poussineau?= Subject: [PATCH 3/6] hw/isa/piix{3,4}: QOM'ify PCI device creation and wiring Date: Fri, 13 May 2022 19:54:42 +0200 Message-Id: <20220513175445.89616-4-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220513175445.89616-1-shentey@gmail.com> References: <20220513175445.89616-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=shentey@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PCI interrupt wiring and device creation (piix4 only) were performed in create() functions which are obsolete. Move these tasks into QOM functions to modernize the code. In order to avoid duplicate checking for xen_enabled() the piix3 realize methods are now split. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland --- hw/isa/piix3.c | 67 +++++++++++++++++++++++++++++++++----------------- hw/isa/piix4.c | 20 +++++++++------ 2 files changed, 57 insertions(+), 30 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 7d69420967..d15117a7c7 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "qemu/range.h" +#include "qapi/error.h" #include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/isa/isa.h" @@ -280,7 +281,7 @@ static const MemoryRegionOps rcr_ops = { .endianness = DEVICE_LITTLE_ENDIAN }; -static void piix3_realize(PCIDevice *dev, Error **errp) +static void pci_piix3_realize(PCIDevice *dev, Error **errp) { PIIX3State *d = PIIX3_PCI_DEVICE(dev); @@ -305,7 +306,6 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) dc->desc = "ISA bridge"; dc->vmsd = &vmstate_piix3; dc->hotpluggable = false; - k->realize = piix3_realize; k->vendor_id = PCI_VENDOR_ID_INTEL; /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; @@ -329,11 +329,28 @@ static const TypeInfo piix3_pci_type_info = { }, }; +static void piix3_realize(PCIDevice *dev, Error **errp) +{ + ERRP_GUARD(); + PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PCIBus *pci_bus = pci_get_bus(dev); + + pci_piix3_realize(dev, errp); + if (*errp) { + return; + } + + pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, + piix3, PIIX_NUM_PIRQS); + pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); +}; + static void piix3_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->config_write = piix3_write_config; + k->realize = piix3_realize; } static const TypeInfo piix3_info = { @@ -342,11 +359,33 @@ static const TypeInfo piix3_info = { .class_init = piix3_class_init, }; +static void piix3_xen_realize(PCIDevice *dev, Error **errp) +{ + ERRP_GUARD(); + PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PCIBus *pci_bus = pci_get_bus(dev); + + pci_piix3_realize(dev, errp); + if (*errp) { + return; + } + + /* + * Xen supports additional interrupt routes from the PCI devices to + * the IOAPIC: the four pins of each PCI device on the bus are also + * connected to the IOAPIC directly. + * These additional routes can be discovered through ACPI. + */ + pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, + piix3, XEN_PIIX_NUM_PIRQS); +}; + static void piix3_xen_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->config_write = piix3_write_config_xen; + k->realize = piix3_xen_realize; }; static const TypeInfo piix3_xen_info = { @@ -368,27 +407,11 @@ PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus) { PIIX3State *piix3; PCIDevice *pci_dev; + const char *type = xen_enabled() ? TYPE_PIIX3_XEN_DEVICE + : TYPE_PIIX3_DEVICE; - /* - * Xen supports additional interrupt routes from the PCI devices to - * the IOAPIC: the four pins of each PCI device on the bus are also - * connected to the IOAPIC directly. - * These additional routes can be discovered through ACPI. - */ - if (xen_enabled()) { - pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, - TYPE_PIIX3_XEN_DEVICE); - piix3 = PIIX3_PCI_DEVICE(pci_dev); - pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, - piix3, XEN_PIIX_NUM_PIRQS); - } else { - pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, - TYPE_PIIX3_DEVICE); - piix3 = PIIX3_PCI_DEVICE(pci_dev); - pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, - piix3, PIIX_NUM_PIRQS); - pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); - } + pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type); + piix3 = PIIX3_PCI_DEVICE(pci_dev); *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); return piix3; diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index a223b69e24..134d23aea7 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -204,6 +204,8 @@ static const MemoryRegionOps piix4_rcr_ops = { static void piix4_realize(PCIDevice *dev, Error **errp) { PIIX4State *s = PIIX4_PCI_DEVICE(dev); + PCIDevice *pci; + PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; qemu_irq *i8259_out_irq; @@ -242,6 +244,15 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq); + + /* IDE */ + pci = pci_create_simple(pci_bus, dev->devfn + 1, "piix4-ide"); + pci_ide_create_devs(pci); + + /* USB */ + pci_create_simple(pci_bus, dev->devfn + 2, "piix4-usb-uhci"); + + pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); } static void piix4_init(Object *obj) @@ -292,7 +303,6 @@ type_init(piix4_register_types) DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) { - PIIX4State *s; PCIDevice *pci; DeviceState *dev; int devfn = PCI_DEVFN(10, 0); @@ -300,22 +310,16 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) pci = pci_create_simple_multifunction(pci_bus, devfn, true, TYPE_PIIX4_PCI_DEVICE); dev = DEVICE(pci); - s = PIIX4_PCI_DEVICE(pci); + if (isa_bus) { *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); } - pci = pci_create_simple(pci_bus, devfn + 1, "piix4-ide"); - pci_ide_create_devs(pci); - - pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); if (smbus) { *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100, qdev_get_gpio_in_named(dev, "isa", 9), NULL, 0, NULL); } - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); - return dev; } From patchwork Fri May 13 17:54:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12849195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1600EC433F5 for ; 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[89.14.181.123]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b006f3ef214e3esm953874ejc.164.2022.05.13.10.54.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 10:55:00 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Bernhard Beschow , Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Aurelien Jarno , =?utf-8?q?Herv=C3=A9_Poussineau?= Subject: [PATCH 4/6] hw/isa/piix{3, 4}: Factor out ISABus retrieval from create() functions Date: Fri, 13 May 2022 19:54:43 +0200 Message-Id: <20220513175445.89616-5-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220513175445.89616-1-shentey@gmail.com> References: <20220513175445.89616-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Modernizes the code and even saves a few lines. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland --- hw/i386/pc_piix.c | 3 ++- hw/isa/piix3.c | 3 +-- hw/isa/piix4.c | 6 +----- hw/mips/malta.c | 3 ++- include/hw/southbridge/piix.h | 4 ++-- 5 files changed, 8 insertions(+), 11 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f843dd906f..47932448fd 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -206,9 +206,10 @@ static void pc_init1(MachineState *machine, pci_memory, ram_memory); pcms->bus = pci_bus; - piix3 = piix3_create(pci_bus, &isa_bus); + piix3 = piix3_create(pci_bus); piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn; + isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); } else { pci_bus = NULL; i440fx_state = NULL; diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index d15117a7c7..6eacb22dd0 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -403,7 +403,7 @@ static void piix3_register_types(void) type_init(piix3_register_types) -PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus) +PIIX3State *piix3_create(PCIBus *pci_bus) { PIIX3State *piix3; PCIDevice *pci_dev; @@ -412,7 +412,6 @@ PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus) pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type); piix3 = PIIX3_PCI_DEVICE(pci_dev); - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); return piix3; } diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 134d23aea7..4968c69da9 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -301,7 +301,7 @@ static void piix4_register_types(void) type_init(piix4_register_types) -DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) +DeviceState *piix4_create(PCIBus *pci_bus, I2CBus **smbus) { PCIDevice *pci; DeviceState *dev; @@ -311,10 +311,6 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) TYPE_PIIX4_PCI_DEVICE); dev = DEVICE(pci); - if (isa_bus) { - *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); - } - if (smbus) { *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100, qdev_get_gpio_in_named(dev, "isa", 9), diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 9ffdc5b8f1..e446b25ad0 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1399,7 +1399,8 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - dev = piix4_create(pci_bus, &isa_bus, &smbus); + dev = piix4_create(pci_bus, &smbus); + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); /* Interrupt controller */ qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index a304fc6041..b768109f30 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -72,8 +72,8 @@ DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, #define TYPE_PIIX4_PCI_DEVICE "piix4-isa" -PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus); +PIIX3State *piix3_create(PCIBus *pci_bus); -DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus); +DeviceState *piix4_create(PCIBus *pci_bus, I2CBus **smbus); #endif From patchwork Fri May 13 17:54:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12849198 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CCF8DC433EF for ; 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[89.14.181.123]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b006f3ef214e3esm953874ejc.164.2022.05.13.10.55.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 10:55:01 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Bernhard Beschow , =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Aurelien Jarno , "Michael S. Tsirkin" , Marcel Apfelbaum Subject: [PATCH 5/6] hw/isa/piix4: Factor out SM bus initialization from create() function Date: Fri, 13 May 2022 19:54:44 +0200 Message-Id: <20220513175445.89616-6-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220513175445.89616-1-shentey@gmail.com> References: <20220513175445.89616-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Initialize the SM bus just like is done for piix3 which modernizes the code. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 15 +++------------ hw/mips/malta.c | 7 ++++++- include/hw/southbridge/piix.h | 2 +- 3 files changed, 10 insertions(+), 14 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 4968c69da9..852e5c4db1 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -301,21 +301,12 @@ static void piix4_register_types(void) type_init(piix4_register_types) -DeviceState *piix4_create(PCIBus *pci_bus, I2CBus **smbus) +PCIDevice *piix4_create(PCIBus *pci_bus) { PCIDevice *pci; - DeviceState *dev; - int devfn = PCI_DEVFN(10, 0); - pci = pci_create_simple_multifunction(pci_bus, devfn, true, + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, TYPE_PIIX4_PCI_DEVICE); - dev = DEVICE(pci); - if (smbus) { - *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100, - qdev_get_gpio_in_named(dev, "isa", 9), - NULL, 0, NULL); - } - - return dev; + return pci; } diff --git a/hw/mips/malta.c b/hw/mips/malta.c index e446b25ad0..d4bd3549d0 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1238,6 +1238,7 @@ void mips_malta_init(MachineState *machine) int be; MaltaState *s; DeviceState *dev; + PCIDevice *piix4; s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA)); sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); @@ -1399,8 +1400,12 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - dev = piix4_create(pci_bus, &smbus); + piix4 = piix4_create(pci_bus); + dev = DEVICE(piix4); isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); + smbus = piix4_pm_init(pci_bus, piix4->devfn + 3, 0x1100, + qdev_get_gpio_in_named(dev, "isa", 9), + NULL, 0, NULL); /* Interrupt controller */ qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index b768109f30..bea3b44551 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -74,6 +74,6 @@ DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, PIIX3State *piix3_create(PCIBus *pci_bus); -DeviceState *piix4_create(PCIBus *pci_bus, I2CBus **smbus); +PCIDevice *piix4_create(PCIBus *pci_bus); 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[89.14.181.123]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b006f3ef214e3esm953874ejc.164.2022.05.13.10.55.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 10:55:02 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Bernhard Beschow , Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Aurelien Jarno , =?utf-8?q?Herv=C3=A9_Poussineau?= Subject: [PATCH 6/6] hw/isa/piix{3,4}: Inline and remove create() functions Date: Fri, 13 May 2022 19:54:45 +0200 Message-Id: <20220513175445.89616-7-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220513175445.89616-1-shentey@gmail.com> References: <20220513175445.89616-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=shentey@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" During the previous changesets the create() functions became trivial wrappers around more generic functions. Modernize the code. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland --- hw/i386/pc_piix.c | 6 +++++- hw/isa/piix3.c | 16 ---------------- hw/isa/piix4.c | 10 ---------- hw/mips/malta.c | 3 ++- include/hw/southbridge/piix.h | 6 ++---- 5 files changed, 9 insertions(+), 32 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 47932448fd..82c7941958 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -196,6 +196,9 @@ static void pc_init1(MachineState *machine, if (pcmc->pci_enabled) { PIIX3State *piix3; + PCIDevice *pci_dev; + const char *type = xen_enabled() ? TYPE_PIIX3_XEN_DEVICE + : TYPE_PIIX3_DEVICE; pci_bus = i440fx_init(host_type, pci_type, @@ -206,7 +209,8 @@ static void pc_init1(MachineState *machine, pci_memory, ram_memory); pcms->bus = pci_bus; - piix3 = piix3_create(pci_bus); + pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type); + piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn; isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 6eacb22dd0..01c376b39a 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -36,9 +36,6 @@ #define XEN_PIIX_NUM_PIRQS 128ULL -#define TYPE_PIIX3_DEVICE "PIIX3" -#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" - static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) { qemu_set_irq(piix3->pic[pic_irq], @@ -402,16 +399,3 @@ static void piix3_register_types(void) } type_init(piix3_register_types) - -PIIX3State *piix3_create(PCIBus *pci_bus) -{ - PIIX3State *piix3; - PCIDevice *pci_dev; - const char *type = xen_enabled() ? TYPE_PIIX3_XEN_DEVICE - : TYPE_PIIX3_DEVICE; - - pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type); - piix3 = PIIX3_PCI_DEVICE(pci_dev); - - return piix3; -} diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 852e5c4db1..a70063bc77 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -300,13 +300,3 @@ static void piix4_register_types(void) } type_init(piix4_register_types) - -PCIDevice *piix4_create(PCIBus *pci_bus) -{ - PCIDevice *pci; - - pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, - TYPE_PIIX4_PCI_DEVICE); - - return pci; -} diff --git a/hw/mips/malta.c b/hw/mips/malta.c index d4bd3549d0..57b5eddc74 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1400,7 +1400,8 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - piix4 = piix4_create(pci_bus); + piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, + TYPE_PIIX4_PCI_DEVICE); dev = DEVICE(piix4); isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); smbus = piix4_pm_init(pci_bus, piix4->devfn + 3, 0x1100, diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index bea3b44551..2d55dbdef7 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -70,10 +70,8 @@ typedef struct PIIXState PIIX3State; DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, TYPE_PIIX3_PCI_DEVICE) +#define TYPE_PIIX3_DEVICE "PIIX3" +#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" #define TYPE_PIIX4_PCI_DEVICE "piix4-isa" -PIIX3State *piix3_create(PCIBus *pci_bus); - -PCIDevice *piix4_create(PCIBus *pci_bus); - #endif