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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b006f3ef214e49sm1736739ejc.175.2022.05.14.06.36.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 06:36:46 -0700 (PDT) From: Nicolas Frattaroli To: Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Nicolas Frattaroli Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/3] media: dt-binding: media: Add rockchip-vepu binding Date: Sat, 14 May 2022 15:36:02 +0200 Message-Id: <20220514133604.174905-2-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220514133604.174905-1-frattaroli.nicolas@gmail.com> References: <20220514133604.174905-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The RK3568 and RK3566 have a Hantro VPU node solely dedicated to encoding. This patch adds a new binding to describe it, as it does not really fit the rockchip-vpu binding, since there is no decoder. Signed-off-by: Nicolas Frattaroli --- .../bindings/media/rockchip-vepu.yaml | 64 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/rockchip-vepu.yaml diff --git a/Documentation/devicetree/bindings/media/rockchip-vepu.yaml b/Documentation/devicetree/bindings/media/rockchip-vepu.yaml new file mode 100644 index 000000000000..b7ba5bf3517a --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip-vepu.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/rockchip-vepu.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Hantro G1 VPU encoders implemented on Rockchip SoCs + +maintainers: + - Nicolas Frattaroli + +description: + Hantro G1 video encode-only accelerators present on Rockchip SoCs. + +properties: + compatible: + enum: + - rockchip,rk3568-vepu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: aclk + - const: hclk + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + vepu: video-codec@fdee0000 { + compatible = "rockchip,rk3568-vepu"; + reg = <0x0 0xfdee0000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; + clock-names = "aclk", "hclk"; + iommus = <&vepu_mmu>; + power-domains = <&power RK3568_PD_RGA>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 9ce78f2275dc..f901a42e5d0f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8637,6 +8637,7 @@ L: linux-media@vger.kernel.org L: linux-rockchip@lists.infradead.org S: Maintained F: Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +F: Documentation/devicetree/bindings/media/rockchip-vepu.yaml F: Documentation/devicetree/bindings/media/rockchip-vpu.yaml F: drivers/staging/media/hantro/ From patchwork Sat May 14 13:36:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Frattaroli X-Patchwork-Id: 12849783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38202C433EF for ; Sat, 14 May 2022 13:37:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232664AbiENNg7 (ORCPT ); Sat, 14 May 2022 09:36:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232667AbiENNg5 (ORCPT ); Sat, 14 May 2022 09:36:57 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A953422B01; Sat, 14 May 2022 06:36:55 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id c12so12992499edv.10; Sat, 14 May 2022 06:36:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fWumciIhP+oFBoIFbUXRMlzycA/gM0riZhiqo5gNScU=; b=V3ukrmo1UeLvhuLRQplrZ9DIj98TdIzk1/sq4otyZfc0INqVtkaSqdln+UYidsqJyy dPCMjq1+6XjKslck4xtsaIs2N2W2nnx/hXs/z0YGTPmPiNkB3lz9D+q0vlWSWxNU8LRL MHxVzkMIc00XFQm78Z97YHgA2c5EVUFWvLRgB9p4oMR+YJ4fb9tZRde7SSsjlb26li2g 7w9UO67aufDizFWDU6WZjdvybkhtpTYDx6w+cWVPcY3zKfOaHU4eEBLWwJBenhvFu7C9 kCIgc4Hl5dbQasSFP9GABY8O5sroUn1bdXtjAuNdupA0w3GUm8w9HLOoOBVKp25uEvy1 3epQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fWumciIhP+oFBoIFbUXRMlzycA/gM0riZhiqo5gNScU=; b=4GbfhivGiWEs+KQhh/+P5TDDRfmHPUqYwPVI3LJ64UNGuy4pVYPiO2jvUdlm+Hlm/Y kn9LNnGR5UbeR0uWxmlvd5tlYV43Ios39VsnYQ5LCMPq+k3Nv3luCtNJjT8EILYcFnnr Wsl2Phv8Rmhh/QQWzPipToRPVaW8TrZctmp4aomkWeYgv3hhcMjjPTD182goyyYFEqXt VwOlEnRCMjksWckdasin1KpvikT4BRkc9F0bRGYgcYLbW2Z9ssVOc7iety2YyvupgscA 6ehBXtF4zBf2JjgW2W93mmLlXyPOj52GXjEX9YdSZiiXym71akKbi2/Q1CJBSoHFzZI4 9Erw== X-Gm-Message-State: AOAM531QcOQPIkLvNEMco9dVJdrQ6501DD9KUmq59OS7wORJPOLMLiME My6pmtrLeVenKBJgLYOG3iA= X-Google-Smtp-Source: ABdhPJyD0WYz9/D9X12wXHaejif0/1Ip2LueFcJDATsZp1cXy8onWFmfrxR+gjZLn4/sKxCh+pc4Zw== X-Received: by 2002:a05:6402:3214:b0:428:9d92:e5c5 with SMTP id g20-20020a056402321400b004289d92e5c5mr3819742eda.108.1652535414308; Sat, 14 May 2022 06:36:54 -0700 (PDT) Received: from localhost.localdomain (84-72-105-84.dclient.hispeed.ch. [84.72.105.84]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b006f3ef214e49sm1736739ejc.175.2022.05.14.06.36.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 06:36:53 -0700 (PDT) From: Nicolas Frattaroli To: Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Greg Kroah-Hartman , Heiko Stuebner Cc: Nicolas Frattaroli , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/3] media: hantro: Add support for RK356x encoder Date: Sat, 14 May 2022 15:36:03 +0200 Message-Id: <20220514133604.174905-3-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220514133604.174905-1-frattaroli.nicolas@gmail.com> References: <20220514133604.174905-1-frattaroli.nicolas@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The RK3566 and RK3568 SoCs come with a small Hantro instance which is solely dedicated to encoding. This patch adds the necessary structs to the Hantro driver to allow the JPEG encoder of it to function. Through some sleuthing through the vendor's MPP source code and after closer inspection of the TRM, it was determined that the hardware likely supports VP8 and H.264 as well. Tested with the following GStreamer command: gst-launch-1.0 videotestsrc ! v4l2jpegenc ! matroskamux ! \ filesink location=foo.mkv Signed-off-by: Nicolas Frattaroli --- drivers/staging/media/hantro/hantro_drv.c | 1 + drivers/staging/media/hantro/hantro_hw.h | 1 + .../staging/media/hantro/rockchip_vpu_hw.c | 25 +++++++++++++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index ac232b5f7825..1112e8d0c821 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -638,6 +638,7 @@ static const struct of_device_id of_hantro_match[] = { { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, { .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, }, { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, + { .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, }, { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, }, #endif #ifdef CONFIG_VIDEO_HANTRO_IMX8M diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index c5dc77125fb7..38988be04d39 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -300,6 +300,7 @@ extern const struct hantro_variant rk3066_vpu_variant; extern const struct hantro_variant rk3288_vpu_variant; extern const struct hantro_variant rk3328_vpu_variant; extern const struct hantro_variant rk3399_vpu_variant; +extern const struct hantro_variant rk3568_vepu_variant; extern const struct hantro_variant rk3568_vpu_variant; extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_variant sunxi_vpu_variant; diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c index fc96501f3bc8..b39813d53e57 100644 --- a/drivers/staging/media/hantro/rockchip_vpu_hw.c +++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c @@ -417,6 +417,14 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = { }, }; +static const struct hantro_codec_ops rk3568_vepu_codec_ops[] = { + [HANTRO_MODE_JPEG_ENC] = { + .run = rockchip_vpu2_jpeg_enc_run, + .reset = rockchip_vpu2_enc_reset, + .done = rockchip_vpu2_jpeg_enc_done, + }, +}; + /* * VPU variant. */ @@ -439,6 +447,10 @@ static const struct hantro_irq rockchip_vpu2_irqs[] = { { "vdpu", rockchip_vpu2_vdpu_irq }, }; +static const struct hantro_irq rk3568_vepu_irqs[] = { + { "vepu", rockchip_vpu2_vepu_irq }, +}; + static const char * const rk3066_vpu_clk_names[] = { "aclk_vdpu", "hclk_vdpu", "aclk_vepu", "hclk_vepu" @@ -545,6 +557,19 @@ const struct hantro_variant rk3399_vpu_variant = { .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) }; +const struct hantro_variant rk3568_vepu_variant = { + .enc_offset = 0x0, + .enc_fmts = rockchip_vpu_enc_fmts, + .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts), + .codec = HANTRO_JPEG_ENCODER, + .codec_ops = rk3568_vepu_codec_ops, + .irqs = rk3568_vepu_irqs, + .num_irqs = ARRAY_SIZE(rk3568_vepu_irqs), + .init = rockchip_vpu_hw_init, + .clk_names = rockchip_vpu_clk_names, + .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) +}; + const struct hantro_variant rk3568_vpu_variant = { .dec_offset = 0x400, .dec_fmts = rk3399_vpu_dec_fmts,