From patchwork Sun May 15 02:56:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 12849969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05E24C433EF for ; Sun, 15 May 2022 02:58:35 +0000 (UTC) Received: from localhost ([::1]:53760 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nq4So-0005pN-V8 for qemu-devel@archiver.kernel.org; Sat, 14 May 2022 22:58:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq4Qp-0003eW-Ft; Sat, 14 May 2022 22:56:31 -0400 Received: from mail-sender-0.a4lg.com ([2401:2500:203:30b:4000:6bfe:4757:0]:48434) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq4Qn-0005IN-TS; Sat, 14 May 2022 22:56:31 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 855DB30008A; Sun, 15 May 2022 02:56:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1652583384; bh=9TRKppZCuWM+og3uS9Kog/rj7fGEgc51lArhHCk6kJo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=To6DKzl9W8BTeEMr1QeuhocP8oOtQ+rBGJp4AvS/1Ax783BmdTgHnzQZplTlrZiUy gaAyEd5qBMgN9WKsIeYilrPVqQZe1H7fCyW/j7mC+HLQNbCK546WZzRoZiZs/m/1rI T6CFgHOdrHLn+K5AdKDYU3QIiezjz35SL+ne83pw= From: Tsukasa OI To: Tsukasa OI , Alistair Francis , Frank Chang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion Date: Sun, 15 May 2022 11:56:07 +0900 Message-Id: <91633f8349253656dd08bc8dc36498a9c7538b10.1652583332.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Received-SPF: pass client-ip=2401:2500:203:30b:4000:6bfe:4757:0; envelope-from=research_trasio@irq.a4lg.com; helo=mail-sender-0.a4lg.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Because ext_? members are boolean variables, operator `&&' should be used instead of `&'. Signed-off-by: Tsukasa OI Reviewed-by: Víctor Colombo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..00bf26ec8b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -596,8 +596,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & - cpu->cfg.ext_a & cpu->cfg.ext_f & + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && + cpu->cfg.ext_a && cpu->cfg.ext_f && cpu->cfg.ext_d)) { warn_report("Setting G will also set IMAFD"); cpu->cfg.ext_i = true; From patchwork Sun May 15 02:56:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 12849972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34C60C433EF for ; Sun, 15 May 2022 02:59:45 +0000 (UTC) Received: from localhost ([::1]:58928 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nq4Tw-0000q1-5g for qemu-devel@archiver.kernel.org; Sat, 14 May 2022 22:59:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58134) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq4Qr-0003fq-OL; Sat, 14 May 2022 22:56:33 -0400 Received: from mail-sender.a4lg.com ([153.120.152.154]:53433 helo=mail-sender-0.a4lg.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq4Qq-0005It-8I; Sat, 14 May 2022 22:56:33 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 0F355300089; Sun, 15 May 2022 02:56:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1652583390; bh=iBuz9s2lVnC1Qr79+mx564AyUY+YXnNGXVW4c6ve6F8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=HD5dv8367S4x4ScTO4akMsL0tm4Sf/O2Bo15zN5F1fYMScSs7RY+Xw4StYyCnEGLB I1PJqUvRJCrO0mMdJujvO9jveRbIe/fJhWu5dVbVjf2U6XzHb0d4qH01Vlp55AxFxs FCkwa09siK5Ho3mona0L7QQkcc8PtUl0LhE9JK4Q= From: Tsukasa OI To: Tsukasa OI , Alistair Francis , Frank Chang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 2/5] target/riscv: Disable "G" by default Date: Sun, 15 May 2022 11:56:08 +0900 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Received-SPF: pass client-ip=153.120.152.154; envelope-from=research_trasio@irq.a4lg.com; helo=mail-sender-0.a4lg.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Because "G" virtual extension expands to "IMAFD", we cannot separately disable extensions like "F" or "D" without disabling "G". Because all "IMAFD" are enabled by default, it's harmless to disable "G" by default. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 00bf26ec8b..3ea68d5cd7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -812,7 +812,7 @@ static Property riscv_cpu_properties[] = { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), - DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), + DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), From patchwork Sun May 15 02:56:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 12849973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A71BC433EF for ; Sun, 15 May 2022 03:01:50 +0000 (UTC) Received: from localhost ([::1]:33162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nq4Vx-0002bu-GR for qemu-devel@archiver.kernel.org; Sat, 14 May 2022 23:01:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58172) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq4Qy-0003u4-DN; Sat, 14 May 2022 22:56:40 -0400 Received: from mail-sender.a4lg.com ([153.120.152.154]:53434 helo=mail-sender-0.a4lg.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq4Qw-0005JM-PE; Sat, 14 May 2022 22:56:40 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 8E26C300089; Sun, 15 May 2022 02:56:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1652583395; bh=6+nGTMnGzT+4YiTY9T3eWkIA/IB43U9AdVSwTusne2A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=o/jozdtqDoovuSM/WZHt8AV0jeNMpDriKZ2KN9TFz331dM6YrWiNF3n9VajFGTsjZ DEyVUdiIIUw3LXxiO41/ZdvroVoGZ4V7Mic33cwGbO7zXvLPR9zHiAzk3TkhxF0yVj cREuHNHDYVBMgGjKp3EuKO3N5oSM6MQsRzn66i+E= From: Tsukasa OI To: Tsukasa OI , Alistair Francis , Frank Chang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 3/5] target/riscv: Change "G" expansion Date: Sun, 15 May 2022 11:56:09 +0900 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Received-SPF: pass client-ip=153.120.152.154; envelope-from=research_trasio@irq.a4lg.com; helo=mail-sender-0.a4lg.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei". Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to be (virtually) enabled as well, it should be safe to change its expansion. Signed-off-by: Tsukasa OI Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3ea68d5cd7..0854ca9103 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -598,13 +598,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d)) { - warn_report("Setting G will also set IMAFD"); + cpu->cfg.ext_d && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i = true; cpu->cfg.ext_m = true; cpu->cfg.ext_a = true; cpu->cfg.ext_f = true; cpu->cfg.ext_d = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.ext_ifencei = true; } if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || From patchwork Sun May 15 02:56:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 12849974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29B06C433EF for ; Sun, 15 May 2022 03:03:24 +0000 (UTC) Received: from localhost ([::1]:35552 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nq4XT-0004FV-BU for qemu-devel@archiver.kernel.org; Sat, 14 May 2022 23:03:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq4R2-0003ze-W2; Sat, 14 May 2022 22:56:45 -0400 Received: from mail-sender-0.a4lg.com ([2401:2500:203:30b:4000:6bfe:4757:0]:48462) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq4R1-0005KD-AV; Sat, 14 May 2022 22:56:44 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 21754300089; Sun, 15 May 2022 02:56:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1652583401; bh=Jfqqtmoi2WLwrqHF9zHmJg4Q/zSEG+Ag6cz00WwP6Ug=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=G+0xJZkBVqrFrHK6GT9kD0wYLqQ90LyPfPSh/eKlCHyGdow53iJwQ3xuxfpdhOPxU GklQ+2riCe0sSNCXLEe71Bv/zM4dfGTS7W7YhEGCL3EwEl8nQsByP3sfLbOJANKc6m In3tQZ5NV7sNRirAYvPM8IZhEZHU86tHmCLfR2AY= From: Tsukasa OI To: Tsukasa OI , Alistair Francis , Frank Chang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 4/5] target/riscv: FP extension requirements Date: Sun, 15 May 2022 11:56:10 +0900 Message-Id: <00e7b1c6060dab32ac7d49813b1ca84d3eb63298.1652583332.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Received-SPF: pass client-ip=2401:2500:203:30b:4000:6bfe:4757:0; envelope-from=research_trasio@irq.a4lg.com; helo=mail-sender-0.a4lg.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" QEMU allowed inconsistent configurations that made floating point arithmetic effectively unusable. This commit adds certain checks for consistent FP arithmetic: - F requires Zicsr - Zfinx requires Zicsr - Zfh/Zfhmin require F - D requires F - V requires D Because F/D/Zicsr are enabled by default (and an error will not occur unless we manually disable one or more of prerequisites), this commit just enforces the user to give consistent combinations. Signed-off-by: Tsukasa OI Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0854ca9103..f910a41407 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -610,11 +610,36 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) cpu->cfg.ext_ifencei = true; } + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + error_setg(errp, "F extension requires Zicsr"); + return; + } + + if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); + return; + } + + if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + error_setg(errp, "D extension requires F extension"); + return; + } + + if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { + error_setg(errp, "V extension requires D extension"); + return; + } + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || cpu->cfg.ext_zhinxmin) { cpu->cfg.ext_zfinx = true; } + if (cpu->cfg.ext_zfinx && !cpu->cfg.ext_icsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); + return; + } + if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; cpu->cfg.ext_zkr = true; From patchwork Sun May 15 02:56:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 12849971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 618ADC433F5 for ; Sun, 15 May 2022 02:58:45 +0000 (UTC) Received: from localhost ([::1]:54502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nq4Sy-0006KJ-6b for qemu-devel@archiver.kernel.org; Sat, 14 May 2022 22:58:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58200) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq4R8-00047Q-Hs; Sat, 14 May 2022 22:56:50 -0400 Received: from mail-sender.a4lg.com ([153.120.152.154]:53432 helo=mail-sender-0.a4lg.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nq4R6-0005KW-RT; Sat, 14 May 2022 22:56:50 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id A4A03300089; Sun, 15 May 2022 02:56:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1652583406; bh=U1E5YcO6hbXuVriPUxUBmX2CdR0DFWEC40Vlm7seRbU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=NGknJdWsgnfzKaJaDv4wNRprgm9qgix6CwM0HG9Ipb+EVmEnFeiwDbcRQjPzrjrDg tZJ+SbbwVBwRYt74JvR7QS/jhWTpE/4hh/K7BwYpycyl46Z2XHQaHAlKJcCQQYB+8s QRZj5+2JG4z3/0JgmEi5n+Hh9YJmRhYF4tKLYrOo= From: Tsukasa OI To: Tsukasa OI , Alistair Francis , Frank Chang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks Date: Sun, 15 May 2022 11:56:11 +0900 Message-Id: In-Reply-To: References: Mime-Version: 1.0 Received-SPF: pass client-ip=153.120.152.154; envelope-from=research_trasio@irq.a4lg.com; helo=mail-sender-0.a4lg.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We should separate "check" and "configure" steps as possible. This commit separates both steps except vector/Zfinx-related checks. Signed-off-by: Tsukasa OI Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f910a41407..5ab246bf63 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -630,14 +630,27 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); + return; + } + + /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || cpu->cfg.ext_zhinxmin) { cpu->cfg.ext_zfinx = true; } - if (cpu->cfg.ext_zfinx && !cpu->cfg.ext_icsr) { - error_setg(errp, "Zfinx extension requires Zicsr"); - return; + if (cpu->cfg.ext_zfinx) { + if (!cpu->cfg.ext_icsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); + return; + } + if (cpu->cfg.ext_f) { + error_setg(errp, + "Zfinx cannot be supported together with F extension"); + return; + } } if (cpu->cfg.ext_zk) { @@ -663,7 +676,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) cpu->cfg.ext_zksh = true; } - /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_i) { ext |= RVI; } @@ -734,20 +746,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } set_vext_version(env, vext_version); } - if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { - error_setg(errp, "Zve32f/Zve64f extension depends upon RVF."); - return; - } if (cpu->cfg.ext_j) { ext |= RVJ; } - if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh || - cpu->cfg.ext_zfhmin)) { - error_setg(errp, - "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh'," - " 'Zfhmin'"); - return; - } set_misa(env, env->misa_mxl, ext); }