From patchwork Sun May 15 21:00:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12850117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FF2DC43217 for ; Sun, 15 May 2022 21:01:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233638AbiEOVA5 (ORCPT ); Sun, 15 May 2022 17:00:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232020AbiEOVAz (ORCPT ); Sun, 15 May 2022 17:00:55 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E440C643A; Sun, 15 May 2022 14:00:52 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id y21so16033827edo.2; Sun, 15 May 2022 14:00:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=GurDE2uniGnUSdql0qTVquEExm5Vat6TsOsO+B9Kmfo=; b=UHYmV2zZ9MhZnHicX0Ek7+4zk9NZ4dthxv+ZBGxUpSLXO24RJK+EvytDQ7M1594aiS ADpdP2GsYr2wWgk+qCVyusNcPKkxY26fazEbCh55wdYmFhIYjltTgJnu2yVywQjDNyIb oA8XjryGt0OB8LtsOT5Ne8Jt0AImytWZGvLDIiwhfE3mIdDDNQKD1aOSRCmFmRoI1qL5 CMb1ZSC6Dh8h/L/Msp3pnhr9wr5oeSh+os4cvsy+GyO08IbS7vF/gzuzINA2z3Qz8VNz dhCZFPWUFhlWdSvlzo9WxTOLUCsO+SUw0B8kUVQZi5ZMyI/iUKcmNblKlSHVWw71YrnF WF/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=GurDE2uniGnUSdql0qTVquEExm5Vat6TsOsO+B9Kmfo=; b=gGeFt5+wT+GWVrlkQB2IkNYhaFgQcoPOWECTvb9750/Gy12J+luI4CIOIeUaREXmlX VPhjsPomI5jVgOmlAtI/pqrVjktZ4y19hkcQxHSmI4FU0AMxF6R1v1X2yOkbV2fUQuXR VLxQtGrqIqXd1/IDbEhpzEY/FXW8KgE1zIC3tbKZ8P2tOrMS5MP4cyqke/tDQCG4LXzV V4bhMe75WP39/DydAuxr9F/bcHip9fYFipxLe8waiRBh4iZHaIew726zF2nyGwBkDaO8 ddorDBfYL7l2YaygGKnSVlpGJOckm4xu1de+nKWQzV6DNCg9jaJPfJsYe9ROxJMBnjVb SdKw== X-Gm-Message-State: AOAM530ojc3j1qZ5gyIut1qfbUrRU5P3xaWqAKI3QmYOtnX8SIupi9Xa iIW2qV6ocHNq6FiqbW55K6KQOEoZ+TPeqA== X-Google-Smtp-Source: ABdhPJw2wNSbVeFUg3eFtVpTx51cCUNt8J2XyYDbbMfhgKup0CNK1rOzJsjuRcYDyDKWwlMNziz61A== X-Received: by 2002:a05:6402:440d:b0:412:9e8a:5e51 with SMTP id y13-20020a056402440d00b004129e8a5e51mr9764099eda.362.1652648451103; Sun, 15 May 2022 14:00:51 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id w12-20020aa7da4c000000b0042ab649183asm28917eds.35.2022.05.15.14.00.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 14:00:50 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v4 01/11] clk: qcom: ipq8074: fix NSS core PLL-s Date: Sun, 15 May 2022 23:00:38 +0200 Message-Id: <20220515210048.483898-1-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration to work. So, obtain the regmap that is required for the Alpha PLL configuration and thus utilize the qcom_cc_really_probe() as we already have the regmap. Then utilize the Alpha PLL configs from the downstream QCA 5.4 based kernel to configure them. This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the kernel. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 39 +++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 541016db3c4b..1a5141da7e23 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4371,6 +4371,33 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { }, }; +static const struct alpha_pll_config ubi32_pll_config = { + .l = 0x4e, + .config_ctl_val = 0x200d4aa8, + .config_ctl_hi_val = 0x3c2, + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .pre_div_val = 0x0, + .pre_div_mask = BIT(12), + .post_div_val = 0x0, + .post_div_mask = GENMASK(9, 8), +}; + +static const struct alpha_pll_config nss_crypto_pll_config = { + .l = 0x3e, + .alpha = 0x0, + .alpha_hi = 0x80, + .config_ctl_val = 0x4001055b, + .main_output_mask = BIT(0), + .pre_div_val = 0x0, + .pre_div_mask = GENMASK(14, 12), + .post_div_val = 0x1 << 8, + .post_div_mask = GENMASK(11, 8), + .vco_mask = GENMASK(21, 20), + .vco_val = 0x0, + .alpha_en_mask = BIT(24), +}; + static struct clk_hw *gcc_ipq8074_hws[] = { &gpll0_out_main_div2.hw, &gpll6_out_main_div2.hw, @@ -4772,7 +4799,17 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = { static int gcc_ipq8074_probe(struct platform_device *pdev) { - return qcom_cc_probe(pdev, &gcc_ipq8074_desc); + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, + &nss_crypto_pll_config); + + return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap); } static struct platform_driver gcc_ipq8074_driver = { From patchwork Sun May 15 21:00:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12850116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 226E5C433F5 for ; Sun, 15 May 2022 21:00:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232519AbiEOVA4 (ORCPT ); Sun, 15 May 2022 17:00:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232091AbiEOVAz (ORCPT ); Sun, 15 May 2022 17:00:55 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 376EE6438; Sun, 15 May 2022 14:00:54 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id j28so1969999eda.13; Sun, 15 May 2022 14:00:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+Ns1RqO2cFYUrMqcJQr7rdBO780Yqa0pL6pb5yGq7SQ=; b=GOe+p2cbTc+TOwseoHreFOyY+q4zCnPdK/bUwvCcSz84wRZdHv8LyfzzLXaWUYtwhm s0oQMmDwNupVM+ckYOf9Mx7tWoFgH3IUdHeZ4po//fQ95tapmlS6sc86divBgeO83KxW ZvIkshvXrfgXpIRhQuBPN2mnWUpfOvsiI119UESBblSMrrF6ZtruBlzFCoJ2GVkiMFme CN3TiPUnGC0+bYI8vHAU8knEVWQXgsvamN6TVrb35ZhohUxNtIjxISMV2sxEDIUDA17a s8EYFU0lZhbieD0TOgXOX3QXMEuFA0/rczToYE+KBfR5GuvbnxQYRr3rbLfMjzbWopwg z8Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+Ns1RqO2cFYUrMqcJQr7rdBO780Yqa0pL6pb5yGq7SQ=; b=YeRYHY4Bx/Uu71DzNTK5QKrf5FmyDsA2t8iohoh/usxYjR/om9stM507Yw2aOeZQtE /ApJexSf3xSPk0vnRlb/P2TOg6haWYF1fkwr7LJAGRD8UR2m5vmo0a9JP6QBAahQBcZO ZW95/2+mhcUjJYPxpnkUl7iBhVuZKL4Z+BNN3Vka1EhaF82UZcr1CNQ8WVuDplltIUDs yIvv15ZRj5lm9mUWMjYcj73fXzwwu7aQ3QZO9l2BeAUPoeotZv8kwIqE6siw4XoCE3hK UhVGQXrvIAL8wfLNVtPLvp3mYNxigfHFNbhsniAjHz4AncXB3I+DzCEFaYs39heBjJGb rMNg== X-Gm-Message-State: AOAM533+UCaweX7xDRXPDU3v/7ARBJj4EqjgpdvMETc3U2LDKIGqBOid SSlaTCYqy3Zz6eV/LTrA784= X-Google-Smtp-Source: ABdhPJwNFNGE4ksp89T+QwmXEYmbhSSMCKNwYylnQuJXr+lZ0Stz/XyILm2BVKLgPg2AApcMkaChYg== X-Received: by 2002:a05:6402:3586:b0:427:b16e:a191 with SMTP id y6-20020a056402358600b00427b16ea191mr9745523edc.137.1652648452800; Sun, 15 May 2022 14:00:52 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id w12-20020aa7da4c000000b0042ab649183asm28917eds.35.2022.05.15.14.00.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 14:00:52 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v4 02/11] clk: qcom: ipq8074: SW workaround for UBI32 PLL lock Date: Sun, 15 May 2022 23:00:39 +0200 Message-Id: <20220515210048.483898-2-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515210048.483898-1-robimarko@gmail.com> References: <20220515210048.483898-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org UBI32 Huayra PLL fails to lock in 5 us in some SoC silicon and thus it will cause the wait_for_pll() to timeout and thus return the error indicating that the PLL failed to lock. This is bug in Huayra PLL HW for which SW workaround is to set bit 26 of TEST_CTL register. This is ported from the QCA 5.4 based downstream kernel. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 1a5141da7e23..b4291ba53c78 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4805,6 +4805,9 @@ static int gcc_ipq8074_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + /* SW Workaround for UBI32 Huayra PLL */ + regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, &nss_crypto_pll_config); From patchwork Sun May 15 21:00:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12850118 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFD23C4332F for ; Sun, 15 May 2022 21:01:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235704AbiEOVA7 (ORCPT ); Sun, 15 May 2022 17:00:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231190AbiEOVA4 (ORCPT ); Sun, 15 May 2022 17:00:56 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E884A452; Sun, 15 May 2022 14:00:55 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id ks9so25273694ejb.2; Sun, 15 May 2022 14:00:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l/I4h6a0+55bSw+/uZ84Z4GGZ1gfpli20lnEWHPl1Hg=; b=EQ7RQv5d8XXcBQt7PTNEWL+apenjeues+htUviZ9KkG/nbsKGG/fiMgFqxbYLuh8p2 LU6DcmEvw2iNKNKtsk/BXckaINBZNemszbQqXBSgcB8Xka1W/rsXKCg04TjgcHzzD0EN +cHbPs4n+19yh9B+MGB/Mu3f6DY6z4WvBOH04alSoLJeKdHwSeyNCkby75dT+iNgYrZU ed1Nd4DUg+VFwCYY2YIGVHUOn8UvXzPWJPS080lUW+AI55orZ64aPK/4vnVk3f/DVSfq nfpXV5o3R/SSRTCOymiuRtCruoTXntpqgC2927+1AMGtyV1pZE1YxTvmuKkJaSRo6EfK colQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l/I4h6a0+55bSw+/uZ84Z4GGZ1gfpli20lnEWHPl1Hg=; b=aWK5jOsqW3n4sFxDBMw3IkYiiXeXW29aiseFUUnkATr+1DByKILljOwDZZWIlVdLoU MWx8H6efDqpEzXo0Ahw3A38AimVLsjrircd1XsqiuJdlwPIZF0J5VbYsNNRzjni+xzWM 44dCtXOxwurwo7+5lr3hspbUSe6GrBcrqbvcK9JHcSdADWoi4LOWx9YfHhUSZsY2At8P VTmdjDvI/4LhlIAEYpBHg90F3tk6OZxc9al5qVxPdUl2FA3BPX7AiBIvJJQqK91BeEzz DsaK0r1ZYEK8QovG3fT/3CiVIAHtS7qXbT7AYnyEZnArDqfxo8uN3ohNqeSMF3I6+N8D IAhQ== X-Gm-Message-State: AOAM533qaICi2h7T7UlB/GO6UGIPTt4nci7fCx8kVqMDEejgubF8mWwM IxCzCyVoc23BbizjNKv5vCQ= X-Google-Smtp-Source: ABdhPJyOIejBuRFTlDRjZ0spAVelYNvKdT2KdGxTxSdO8irynX9ggM8RylkFU+1M5gM2YcnjVadkmQ== X-Received: by 2002:a17:907:3f26:b0:6f4:dc59:3cfe with SMTP id hq38-20020a1709073f2600b006f4dc593cfemr12605064ejc.528.1652648453883; Sun, 15 May 2022 14:00:53 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id w12-20020aa7da4c000000b0042ab649183asm28917eds.35.2022.05.15.14.00.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 14:00:53 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v4 03/11] clk: qcom: ipq8074: fix NSS port frequency tables Date: Sun, 15 May 2022 23:00:40 +0200 Message-Id: <20220515210048.483898-3-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515210048.483898-1-robimarko@gmail.com> References: <20220515210048.483898-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org NSS port 5 and 6 frequency tables are currently broken and are causing a wide ranges of issue like 1G not working at all on port 6 or port 5 being clocked with 312 instead of 125 MHz as UNIPHY1 gets selected. So, update the frequency tables with the ones from the downstream QCA 5.4 based kernel which has already fixed this. Fixes: 7117a51ed303 ("clk: qcom: ipq8074: add NSS ethernet port clocks") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index b4291ba53c78..f1017f2e61bd 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -1788,8 +1788,10 @@ static struct clk_regmap_div nss_port4_tx_div_clk_src = { static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(25000000, P_UNIPHY1_RX, 12.5, 0, 0), + F(25000000, P_UNIPHY0_RX, 5, 0, 0), F(78125000, P_UNIPHY1_RX, 4, 0, 0), F(125000000, P_UNIPHY1_RX, 2.5, 0, 0), + F(125000000, P_UNIPHY0_RX, 1, 0, 0), F(156250000, P_UNIPHY1_RX, 2, 0, 0), F(312500000, P_UNIPHY1_RX, 1, 0, 0), { } @@ -1828,8 +1830,10 @@ static struct clk_regmap_div nss_port5_rx_div_clk_src = { static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(25000000, P_UNIPHY1_TX, 12.5, 0, 0), + F(25000000, P_UNIPHY0_TX, 5, 0, 0), F(78125000, P_UNIPHY1_TX, 4, 0, 0), F(125000000, P_UNIPHY1_TX, 2.5, 0, 0), + F(125000000, P_UNIPHY0_TX, 1, 0, 0), F(156250000, P_UNIPHY1_TX, 2, 0, 0), F(312500000, P_UNIPHY1_TX, 1, 0, 0), { } @@ -1867,8 +1871,10 @@ static struct clk_regmap_div nss_port5_tx_div_clk_src = { static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY2_RX, 5, 0, 0), F(25000000, P_UNIPHY2_RX, 12.5, 0, 0), F(78125000, P_UNIPHY2_RX, 4, 0, 0), + F(125000000, P_UNIPHY2_RX, 1, 0, 0), F(125000000, P_UNIPHY2_RX, 2.5, 0, 0), F(156250000, P_UNIPHY2_RX, 2, 0, 0), F(312500000, P_UNIPHY2_RX, 1, 0, 0), @@ -1907,8 +1913,10 @@ static struct clk_regmap_div nss_port6_rx_div_clk_src = { static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY2_TX, 5, 0, 0), F(25000000, P_UNIPHY2_TX, 12.5, 0, 0), F(78125000, P_UNIPHY2_TX, 4, 0, 0), + F(125000000, P_UNIPHY2_TX, 1, 0, 0), F(125000000, P_UNIPHY2_TX, 2.5, 0, 0), F(156250000, P_UNIPHY2_TX, 2, 0, 0), F(312500000, P_UNIPHY2_TX, 1, 0, 0), From patchwork Sun May 15 21:00:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12850119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5025C4332F for ; Sun, 15 May 2022 21:01:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238618AbiEOVBD (ORCPT ); Sun, 15 May 2022 17:01:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234843AbiEOVA6 (ORCPT ); Sun, 15 May 2022 17:00:58 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 771A0B48B; Sun, 15 May 2022 14:00:56 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id j28so1970081eda.13; Sun, 15 May 2022 14:00:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I3v3xUbGkou9V1pzQELGCGcR+zcC6SorV8LTEkdqEGA=; b=lOAbB2alfyM+wvCTjQG52WxzfXC/jnLz0/0o1zdUu64Ra43vvSqapN71xYslIkTag7 Zr29MshPA0guPExDTOlyJbm0210YjsGmVYzqArlMTST3PTUnjQlYFHkh+LwiJYLanb2d HoFLjuLhBkdDXF912+bIISYcrlljZI9CpINDps1dkqv85GZVW0ryVjtAChYqCCVFp7m/ LUYMfgfebQMJzoDnT2S5neu7GduQBJRC6fkw+ne/R0IAcM+oTvOnlS3mFuqMRXe4StHp pwf5Q7qkFyvqtKt/m2SAWk66/nW2WMBUQhpCL5v1lMKq8+BQk3UxpKM39AtLJu1ZPTlJ OiTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I3v3xUbGkou9V1pzQELGCGcR+zcC6SorV8LTEkdqEGA=; b=tWbAaVzkAf6PXfm9H8V6Xv/SiZyCRdp1xFPjHmZJfWutxc3/cCuX+ARycCd8pqhzL6 vbFLyHD2VprIrmAPtcYpqJgDV26xP+U4+2TAGQzF2sOHgHi1lUwjBZwasc4uYykZZrte VETihPwtQorZW055/5MnGdhcX+WZT2Ia4S2j7xOy4MOr9KlpCJvF7Ag0+l+D+KvzfjMn qcbsp5eOMJPr1W8yyFodvprysWKkiFXWGe44Ctlg9Hlr1W7cDBeJGWw613J5+BxAhTvm 90ZUPjNMtK9EdAUxnAw+rku2ln73KEsMcAvvjp73pDzG8PaPCRhBVjul92X5966iPuLJ 6s6g== X-Gm-Message-State: AOAM532gsOAsoR0f5k6lp+MGw70J44xDNEZleOJsgsXqX71SZain19rh N5DgrQq/pB/EWHMb0CZ86bM= X-Google-Smtp-Source: ABdhPJwdJKyrBI26zmBAdTtnYN6xQtiSInCiBOQ5k/Jx1Z+xpH8b7YvL0zXjmnq9atkgBpw2HKmHwA== X-Received: by 2002:a05:6402:2789:b0:427:bc78:85c9 with SMTP id b9-20020a056402278900b00427bc7885c9mr10110228ede.50.1652648455107; Sun, 15 May 2022 14:00:55 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id w12-20020aa7da4c000000b0042ab649183asm28917eds.35.2022.05.15.14.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 14:00:54 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko , Krzysztof Kozlowski Subject: [PATCH v4 04/11] dt-bindings: clock: qcom: ipq8074: add PPE crypto clock Date: Sun, 15 May 2022 23:00:41 +0200 Message-Id: <20220515210048.483898-4-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515210048.483898-1-robimarko@gmail.com> References: <20220515210048.483898-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add binding for the PPE crypto clock in IPQ8074. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 8e2bec1c91bf..5f0928785d7a 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -233,6 +233,7 @@ #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 #define GCC_PCIE0_RCHNG_CLK_SRC 225 #define GCC_PCIE0_RCHNG_CLK 226 +#define GCC_CRYPTO_PPE_CLK 227 #define GCC_BLSP1_BCR 0 #define GCC_BLSP1_QUP1_BCR 1 From patchwork Sun May 15 21:00:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12850120 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25F71C4321E for ; Sun, 15 May 2022 21:01:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235241AbiEOVBD (ORCPT ); Sun, 15 May 2022 17:01:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236791AbiEOVA7 (ORCPT ); Sun, 15 May 2022 17:00:59 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E51D7B7EC; Sun, 15 May 2022 14:00:57 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id en5so1909474edb.1; Sun, 15 May 2022 14:00:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tS71jE0WRdd742PGPX4S4NYBMalYLsRNuQATyXyB9rQ=; b=MHIz8aAXaKnFCMDAo6pZ92tifX30ncDe6+JJ5nxhXQMRDk/fFbhzy5tukIYRCq+zhy sUH28ulMlPcE8FD3lgnd1gl/omrrnbOteMf/t99NCzd9bykkcl9WeZUFAsX94B/ka46i Q/BVFvA6PdmG0z/c8+CktQ853xx4GCaF4vcg3JhslFkanDdhScIgSse5J872WtNyRBJu CRORsZfBv8gU2iBLUCBGO9ui2tbgWDHqVHs8JNwFItllRpl7qDY+mm10Bh8gTBUAixiX TqGnb01Z8ubeP+H9MtoBrLSNYVE2et5UNoivSfoR+28Ux4PPFdqxi7r/x4CNZaurR9XD AwdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tS71jE0WRdd742PGPX4S4NYBMalYLsRNuQATyXyB9rQ=; b=aMe3p3wa0FX3RsUJALVOAxPSP3IfLl9H6XjF64KlPjL1iMn2e7nTLm/pDo7FN/0FTC hvyehf2lzR4H+1kJVXpSboxzfZprl7JMebygmiVp+UywCZPPH7ZX6OfJWnsy3pyA4cQ0 dh1OKl/5FF9D3d/WZGqAE8nV91lPuQH5EBmoJUaQ0yJqD5t3V0bcw1ulIk30io3FhSvZ zNsPs5/iPQUhM+E8BWEeXkCWarbqnR2gbRMps61DOvHwXbsSj9yd1OsCK5WsUWFtNbzD yO3qd93MxFoj+qCwMT4F18hPX+m+XAjOP8FWrPtuQqVT7uVbbI7gBuAnE+RyaWs4ckSI 2fmA== X-Gm-Message-State: AOAM533fSLSZul8jlrKcGoCs05vXB5BsFoZy9JoRqobNmf1HZslzlXkL VVQTDomqL/7ZxOC6LtmhuXc= X-Google-Smtp-Source: ABdhPJxFez/HsR9DDAfOesc1EVfyxsuhw1jTY0AN2DAooKGwjY8PEwVOLrdJjMndhBKxfBuv9CL1Xw== X-Received: by 2002:a05:6402:1148:b0:413:11e0:1f58 with SMTP id g8-20020a056402114800b0041311e01f58mr9798398edw.113.1652648456228; Sun, 15 May 2022 14:00:56 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id w12-20020aa7da4c000000b0042ab649183asm28917eds.35.2022.05.15.14.00.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 14:00:55 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v4 05/11] clk: qcom: ipq8074: add PPE crypto clock Date: Sun, 15 May 2022 23:00:42 +0200 Message-Id: <20220515210048.483898-5-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515210048.483898-1-robimarko@gmail.com> References: <20220515210048.483898-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The built-in PPE engine has a dedicated clock for the EIP-197 crypto engine. So, since the required clock currently missing add support for it. Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index f1017f2e61bd..c964e43ba68a 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -3182,6 +3182,24 @@ static struct clk_branch gcc_nss_ptp_ref_clk = { }, }; +static struct clk_branch gcc_crypto_ppe_clk = { + .halt_reg = 0x68310, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x68310, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_ppe_clk", + .parent_names = (const char *[]){ + "nss_ppe_clk_src" + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nssnoc_ce_apb_clk = { .halt_reg = 0x6830c, .clkr = { @@ -4644,6 +4662,7 @@ static struct clk_regmap *gcc_ipq8074_clks[] = { [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, + [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr, }; static const struct qcom_reset_map gcc_ipq8074_resets[] = { From patchwork Sun May 15 21:00:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12850125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9772C433EF for ; Sun, 15 May 2022 21:01:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238745AbiEOVBJ (ORCPT ); Sun, 15 May 2022 17:01:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234471AbiEOVBB (ORCPT ); Sun, 15 May 2022 17:01:01 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B52CEBC3A; Sun, 15 May 2022 14:00:58 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id i40so995850eda.7; Sun, 15 May 2022 14:00:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dzaCsc5NE5smSEagSfvo1JD5ChGYk1foMXMH/Nh5gcI=; b=eTpbzX5AEb89EE1/KYxfriGv7uZdAeDMhxb/5pbmaetRjjV6zWlCQ8WaxcTt4JzZ5Z nYpsZyAPp64m7mQ2ifmCrSIt9kiNj2EYy+NMr8W63x1XvNzDI4CNVPvrMQ1f/dFn+g70 xfnvnmsXjIKRH6BUr4ol1bUcHRy4dRSQhtA4biWsu9JKQptbHx4btlA3odMMORpUOZij uWGfA5fLtiN/Q73KLmGHmUYiu6C/jW2QdEJx71agjFJmht6zYhEVc/ORZoZ+cXandlrd FHSwwJD70XgwQl95RbQCAyeyBvJQu7H5Py8719uCK2IhphDux66kuS0+K/wQ3B9zQ/Xd ckpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dzaCsc5NE5smSEagSfvo1JD5ChGYk1foMXMH/Nh5gcI=; b=KccOdG5x8vK1egaQGqNUUzT/SZCOtexO+iyW9S6gxB6v5ACZQQ/byZ2/HVOkP+hxDp yThf5cxnaMoxpOMJXQhpwO5zsaMzcA3l1KokP3GfSsmxSKzEU65+RsP7UzA2PYaDIcLk MdWZieVT/BeL46kJYHCEL28SwmpDhUGlAIDStwSEoFCaxwAKffJgnhVO+e2k9Gcjo9PL 45CMJl2vyZc0zylYZzuQsBxmyogpcm1fwqVaET2EY0//eIS9HYZGDszQAXwX/xST8BSZ LkvUab5ZFpn2HskSyQQI65Vv+KOp5TeWk1WX7RX1ZEr3+A2rNXVVRXfW2Ln7RmMIVpll lxSA== X-Gm-Message-State: AOAM533HgvuIgdeszf0WGk9p2xMbYjII55CmTRwA0GQJKsrjkJQoU0fL vdpyYTo0Wycyku1jEa+FV6M= X-Google-Smtp-Source: ABdhPJzSIWv2Zor2t1kLv6CBRusMdFa/nCk+yvljtF20Luv1POke9hM92t1imgRn0BqfQtQKZLqe4Q== X-Received: by 2002:a50:a6c8:0:b0:428:5b3a:6c99 with SMTP id f8-20020a50a6c8000000b004285b3a6c99mr10029635edc.222.1652648457368; Sun, 15 May 2022 14:00:57 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id w12-20020aa7da4c000000b0042ab649183asm28917eds.35.2022.05.15.14.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 14:00:56 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v4 06/11] clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks Date: Sun, 15 May 2022 23:00:43 +0200 Message-Id: <20220515210048.483898-6-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515210048.483898-1-robimarko@gmail.com> References: <20220515210048.483898-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently, attempting to enable the UBI clocks will cause the stuck at off warning to be printed and clk_enable will fail. [ 14.936694] gcc_ubi1_ahb_clk status stuck at 'off' Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY flag on UBI clocks, so lets do the same. Fixes: 5736294aef83 ("clk: qcom: ipq8074: add NSS clocks") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index c964e43ba68a..85076c1383c7 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -3372,6 +3372,7 @@ static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = { static struct clk_branch gcc_ubi0_ahb_clk = { .halt_reg = 0x6820c, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6820c, .enable_mask = BIT(0), @@ -3389,6 +3390,7 @@ static struct clk_branch gcc_ubi0_ahb_clk = { static struct clk_branch gcc_ubi0_axi_clk = { .halt_reg = 0x68200, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68200, .enable_mask = BIT(0), @@ -3406,6 +3408,7 @@ static struct clk_branch gcc_ubi0_axi_clk = { static struct clk_branch gcc_ubi0_nc_axi_clk = { .halt_reg = 0x68204, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68204, .enable_mask = BIT(0), @@ -3423,6 +3426,7 @@ static struct clk_branch gcc_ubi0_nc_axi_clk = { static struct clk_branch gcc_ubi0_core_clk = { .halt_reg = 0x68210, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68210, .enable_mask = BIT(0), @@ -3440,6 +3444,7 @@ static struct clk_branch gcc_ubi0_core_clk = { static struct clk_branch gcc_ubi0_mpt_clk = { .halt_reg = 0x68208, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68208, .enable_mask = BIT(0), @@ -3457,6 +3462,7 @@ static struct clk_branch gcc_ubi0_mpt_clk = { static struct clk_branch gcc_ubi1_ahb_clk = { .halt_reg = 0x6822c, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6822c, .enable_mask = BIT(0), @@ -3474,6 +3480,7 @@ static struct clk_branch gcc_ubi1_ahb_clk = { static struct clk_branch gcc_ubi1_axi_clk = { .halt_reg = 0x68220, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68220, .enable_mask = BIT(0), @@ -3491,6 +3498,7 @@ static struct clk_branch gcc_ubi1_axi_clk = { static struct clk_branch gcc_ubi1_nc_axi_clk = { .halt_reg = 0x68224, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68224, .enable_mask = BIT(0), @@ -3508,6 +3516,7 @@ static struct clk_branch gcc_ubi1_nc_axi_clk = { static struct clk_branch gcc_ubi1_core_clk = { .halt_reg = 0x68230, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68230, .enable_mask = BIT(0), @@ -3525,6 +3534,7 @@ static struct clk_branch gcc_ubi1_core_clk = { static struct clk_branch gcc_ubi1_mpt_clk = { .halt_reg = 0x68228, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68228, .enable_mask = BIT(0), From patchwork Sun May 15 21:00:44 2022 Content-Type: text/plain; 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[88.207.98.105]) by smtp.googlemail.com with ESMTPSA id w12-20020aa7da4c000000b0042ab649183asm28917eds.35.2022.05.15.14.00.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 14:00:58 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v4 07/11] dt-bindings: clocks: qcom,gcc-ipq8074: support power domains Date: Sun, 15 May 2022 23:00:44 +0200 Message-Id: <20220515210048.483898-7-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515210048.483898-1-robimarko@gmail.com> References: <20220515210048.483898-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GCC inside of IPQ8074 also provides power management via built-in GDSCs. In order to do so, '#power-domain-cells' must be set to 1. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski --- Changes in v4: * Alphabetically sort the cells properties --- .../devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml index 98572b4a9b60..21470f52ce36 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml @@ -24,6 +24,9 @@ properties: '#clock-cells': const: 1 + '#power-domain-cells': + const: 1 + '#reset-cells': const: 1 @@ -38,6 +41,7 @@ required: - compatible - reg - '#clock-cells' + - '#power-domain-cells' - '#reset-cells' additionalProperties: false @@ -48,6 +52,7 @@ examples: compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; }; ... 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[88.207.98.105]) by smtp.googlemail.com with ESMTPSA id w12-20020aa7da4c000000b0042ab649183asm28917eds.35.2022.05.15.14.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 14:00:59 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v4 08/11] dt-bindings: clock: qcom: ipq8074: add USB GDSCs Date: Sun, 15 May 2022 23:00:45 +0200 Message-Id: <20220515210048.483898-8-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515210048.483898-1-robimarko@gmail.com> References: <20220515210048.483898-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings for the USB GDSCs found in IPQ8074 GCC. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 5f0928785d7a..e4991d303708 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -368,4 +368,7 @@ #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 +#define USB0_GDSC 0 +#define USB1_GDSC 1 + #endif From patchwork Sun May 15 21:00:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12850121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C9E4C433F5 for ; Sun, 15 May 2022 21:01:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238678AbiEOVBE (ORCPT ); Sun, 15 May 2022 17:01:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238557AbiEOVBC (ORCPT ); Sun, 15 May 2022 17:01:02 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37CDBDF68; Sun, 15 May 2022 14:01:02 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id kq17so25276418ejb.4; Sun, 15 May 2022 14:01:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y5Mlp4MlPX47xiT5PAs3WlBL8yry+8fZ0v7z+93yv/A=; b=V6NJiJdQMSKmXj5nIF1KxDALUTPue0qi/+9Ay5DrugFOZUGZziNjp+1eRwRLZPd3Tw FT+hHc3qBRc4xd0ETQ2A5th0aHyzxj65hJXDaVZ4RYREFR70jMy9Rx7p3gfYsgn/cuHe BJ2Kt+UagTPD0R3ah4C1yRFcD6Jetv0PahmXiZSyxJs0gUSdwaTi8sLnyUel3KiSLL1F 2vnVBqlkJh9hMk80g3EHERrGtdATqgSndlAtLtDidayklRc7xWWnzdt2czoKJDhz0kZe bVYtbgXhGykfrRPwkcM2IpNfa8IzV1+eOe+OEKF7CvXNs4BNWsqrGV65KLjsKXZFkpn+ w9RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y5Mlp4MlPX47xiT5PAs3WlBL8yry+8fZ0v7z+93yv/A=; b=iw62XeMVqkFIfI5aPw/XVW0g4JTLR9u4e6BpedBl3qhp5yEqMi3nGpI5MHUsXo9m0J V8M9v8iy/pJOFr1LBUaFR9B+zlq9WFrofxJK41RncF5Qy/5IstLqb8TYM1KBTtaSvyVc HAzelsMlkiS006f1A/eNgS7lOQP9FLtUzR+m469Y5DjdyRixBrTK91oT1GuLuSwnAF4R e1tqfUmkV4vJRMxEf2cXvp57jMVh2zwaVpp0LcHguXIdW6wqX4G/yzjIu6e1FDn6VAEo /f4LMPr7NUiK1k9HPeUVc1oX6WWYrD8MldDHmCyll7pRaAGuOPAUkp1xAMIOxrBYtmM/ SspA== X-Gm-Message-State: AOAM5304I/uqATbTvioqTw/N6ETGGfL1wi530QAjhn78JqJ0NdasLvZQ UQNjE9era/1Lrx5Il69GDoU= X-Google-Smtp-Source: ABdhPJyfbDHmxnETtisFSULc3VaOS7HbMiPdGO5yeOCaNDbXSKbT+wYIi84CIqptaR6cw1eI4/BoCg== X-Received: by 2002:a17:906:ed1:b0:6f4:ebc2:da8a with SMTP id u17-20020a1709060ed100b006f4ebc2da8amr12612170eji.126.1652648460789; Sun, 15 May 2022 14:01:00 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id w12-20020aa7da4c000000b0042ab649183asm28917eds.35.2022.05.15.14.00.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 14:01:00 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v4 09/11] clk: qcom: ipq8074: add USB GDSCs Date: Sun, 15 May 2022 23:00:46 +0200 Message-Id: <20220515210048.483898-9-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515210048.483898-1-robimarko@gmail.com> References: <20220515210048.483898-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add GDSC-s for each of the two USB controllers built-in the IPQ8074. Signed-off-by: Robert Marko --- Changes in v2: * Use proper GSDCs instead of raw regmap writes. --- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-ipq8074.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d01436be6d7a..00fe5f066de5 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -166,6 +166,7 @@ config IPQ_LCC_806X config IPQ_GCC_8074 tristate "IPQ8074 Global Clock Controller" + select QCOM_GDSC help Support for global clock controller on ipq8074 devices. Say Y if you want to use peripheral devices such as UART, SPI, diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 85076c1383c7..3204d550ff76 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -22,6 +22,7 @@ #include "clk-alpha-pll.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "gdsc.h" #include "reset.h" enum { @@ -4407,6 +4408,22 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { }, }; +static struct gdsc usb0_gdsc = { + .gdscr = 0x3e078, + .pd = { + .name = "usb0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb1_gdsc = { + .gdscr = 0x3f078, + .pd = { + .name = "usb1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static const struct alpha_pll_config ubi32_pll_config = { .l = 0x4e, .config_ctl_val = 0x200d4aa8, @@ -4810,6 +4827,11 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = { [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, }; +static struct gdsc *gcc_ipq8074_gdscs[] = { + [USB0_GDSC] = &usb0_gdsc, + [USB1_GDSC] = &usb1_gdsc, +}; + static const struct of_device_id gcc_ipq8074_match_table[] = { { .compatible = "qcom,gcc-ipq8074" }, { } @@ -4832,6 +4854,8 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = { .num_resets = ARRAY_SIZE(gcc_ipq8074_resets), .clk_hws = gcc_ipq8074_hws, .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws), + .gdscs = gcc_ipq8074_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs), }; static int gcc_ipq8074_probe(struct platform_device *pdev) From patchwork Sun May 15 21:00:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12850123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F19BAC4167E for ; Sun, 15 May 2022 21:01:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237516AbiEOVBH (ORCPT ); Sun, 15 May 2022 17:01:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237542AbiEOVBD (ORCPT ); Sun, 15 May 2022 17:01:03 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FBDDB86A; Sun, 15 May 2022 14:01:02 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id dk23so25243590ejb.8; Sun, 15 May 2022 14:01:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=npYBdm+Z3JK/AAr8Gk9MHyCf99zBDnSXIOh7phMrfJA=; b=arQwpoazmz7KmsnEl3pcO9LHJ0Bfpaygrjd7lLfmYESy9dpYb90nS920fw+kXVE6Fs vE4Y3+4mdj6MuCD9Rj/7vgYJLCakQAtd3Evos72Ii7fZXHn5oRtVLi5sOU4hQLhwdRho GBTE6ERUpFwY1diX3WjYnk3sG2ArDJMqFNZin/ZjCNxTnPqqj4zJkWwAzWWWdOuI4q77 QwS6OIKg8WM9KxVYOoRrFYO3UWtAwmsxZGgH9ukDRm4mCOroOV4cgUpQumMHR5e2G6t2 CKuLoBJlZqlvI6TnXNIQ9P3dtycG0bmYXOVo0U0Wt0u05pQk+rS9A3tthI0tPgWU8qWZ iJWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=npYBdm+Z3JK/AAr8Gk9MHyCf99zBDnSXIOh7phMrfJA=; b=7BKDKwY8XT/bfoDjZBMGxImesqgUEIai5ngAs5IFk2UFUtHrfBRxcOIZFstOh2WzlN LtO20d4W0/WASQ33w8z5XGLLWdiplgXV8bs9NM+ZSuIleNqLdq3ARwiyATJejzwCdJz+ uzU4PeaPm6D8/WJwLXyL5ispekZSXejCDjJe8PNt5OnNvwdzyvh9mzqiZGtOlNB/DpQi lir6v+wp+QuxXTzZq/sEdpa8QEn166+FF91ot8qcFbBv/Dl4kQSnZSJYQVZG5+8UJ6kJ zeZtEcg9PdHkxfwl3XySoC7iVF2nM1g3aJ77GiD+W/otI+JvlGXBUTMXlwp6LP8xZ+IU oQZA== X-Gm-Message-State: AOAM533EArcsLC05sNCxrj7JuIQI048nxuDGav1T34TRODmE5PZ+rbOl 2Ktya1ifdNe68eLkd6M06N4= X-Google-Smtp-Source: ABdhPJwMamDJlumEP9BSNN49y5AS3ZIgyvSZDNir9lKs5LPCrlE+SWzSAeUCeesO4f2kz1kihUL4qg== X-Received: by 2002:a17:907:7d89:b0:6f3:ef24:ddd2 with SMTP id oz9-20020a1709077d8900b006f3ef24ddd2mr13166520ejc.550.1652648462001; Sun, 15 May 2022 14:01:02 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id w12-20020aa7da4c000000b0042ab649183asm28917eds.35.2022.05.15.14.01.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 14:01:01 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v4 10/11] clk: qcom: ipq8074: dont disable gcc_sleep_clk_src Date: Sun, 15 May 2022 23:00:47 +0200 Message-Id: <20220515210048.483898-10-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515210048.483898-1-robimarko@gmail.com> References: <20220515210048.483898-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Once the usb sleep clocks are disabled, clock framework is trying to disable the sleep clock source also. However, it seems that it cannot be disabled and trying to do so produces: [ 245.436390] ------------[ cut here ]------------ [ 245.441233] gcc_sleep_clk_src status stuck at 'on' [ 245.441254] WARNING: CPU: 2 PID: 223 at clk_branch_wait+0x130/0x140 [ 245.450435] Modules linked in: xhci_plat_hcd xhci_hcd dwc3 dwc3_qcom leds_gpio [ 245.456601] CPU: 2 PID: 223 Comm: sh Not tainted 5.18.0-rc4 #215 [ 245.463889] Hardware name: Xiaomi AX9000 (DT) [ 245.470050] pstate: 204000c5 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 245.474307] pc : clk_branch_wait+0x130/0x140 [ 245.481073] lr : clk_branch_wait+0x130/0x140 [ 245.485588] sp : ffffffc009f2bad0 [ 245.489838] x29: ffffffc009f2bad0 x28: ffffff8003e6c800 x27: 0000000000000000 [ 245.493057] x26: 0000000000000000 x25: 0000000000000000 x24: ffffff800226ef20 [ 245.500175] x23: ffffffc0089ff550 x22: 0000000000000000 x21: ffffffc008476ad0 [ 245.507294] x20: 0000000000000000 x19: ffffffc00965ac70 x18: fffffffffffc51a7 [ 245.514413] x17: 68702e3030303837 x16: 3a6d726f6674616c x15: ffffffc089f2b777 [ 245.521531] x14: ffffffc0095c9d18 x13: 0000000000000129 x12: 0000000000000129 [ 245.528649] x11: 00000000ffffffea x10: ffffffc009621d18 x9 : 0000000000000001 [ 245.535767] x8 : 0000000000000001 x7 : 0000000000017fe8 x6 : 0000000000000001 [ 245.542885] x5 : ffffff803fdca6d8 x4 : 0000000000000000 x3 : 0000000000000027 [ 245.550002] x2 : 0000000000000027 x1 : 0000000000000023 x0 : 0000000000000026 [ 245.557122] Call trace: [ 245.564229] clk_branch_wait+0x130/0x140 [ 245.566490] clk_branch2_disable+0x2c/0x40 [ 245.570656] clk_core_disable+0x60/0xb0 [ 245.574561] clk_core_disable+0x68/0xb0 [ 245.578293] clk_disable+0x30/0x50 [ 245.582113] dwc3_qcom_remove+0x60/0xc0 [dwc3_qcom] [ 245.585588] platform_remove+0x28/0x60 [ 245.590361] device_remove+0x4c/0x80 [ 245.594179] device_release_driver_internal+0x1dc/0x230 [ 245.597914] device_driver_detach+0x18/0x30 [ 245.602861] unbind_store+0xec/0x110 [ 245.607027] drv_attr_store+0x24/0x40 [ 245.610847] sysfs_kf_write+0x44/0x60 [ 245.614405] kernfs_fop_write_iter+0x128/0x1c0 [ 245.618052] new_sync_write+0xc0/0x130 [ 245.622391] vfs_write+0x1d4/0x2a0 [ 245.626123] ksys_write+0x58/0xe0 [ 245.629508] __arm64_sys_write+0x1c/0x30 [ 245.632895] invoke_syscall.constprop.0+0x5c/0x110 [ 245.636890] do_el0_svc+0xa0/0x150 [ 245.641488] el0_svc+0x18/0x60 [ 245.644872] el0t_64_sync_handler+0xa4/0x130 [ 245.647914] el0t_64_sync+0x174/0x178 [ 245.652340] ---[ end trace 0000000000000000 ]--- So, add CLK_IS_CRITICAL flag to the clock so that the kernel won't try to disable the sleep clock. Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 3204d550ff76..42d185fe19c8 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -663,6 +663,7 @@ static struct clk_branch gcc_sleep_clk_src = { }, .num_parents = 1, .ops = &clk_branch2_ops, + .flags = CLK_IS_CRITICAL, }, }, }; From patchwork Sun May 15 21:00:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12850126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4366C433F5 for ; Sun, 15 May 2022 21:01:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238806AbiEOVBM (ORCPT ); Sun, 15 May 2022 17:01:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238735AbiEOVBG (ORCPT ); Sun, 15 May 2022 17:01:06 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2369DFC0; Sun, 15 May 2022 14:01:04 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id m20so25211083ejj.10; Sun, 15 May 2022 14:01:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kiaVpz1eUfDqE52UW9rfQ/0tpqjiTOXtuh3HRB0EhLk=; b=UlQ0Wf4tAlxYudfXwS23LRgu7dEtmTUo6YZPEmJB3AF6ca0mvh5MF0ywA2vOD7bHQh CekfjhGkXVJpcqQ2GevOtNV5QHVIEneEtijwSbig0xXpEucR+qO7NdPN3QeiIyJszPzc 2T5KV0sl36xM8NMfPJ7AdRCr4H7KzynVtd8zIYUaH51YVyFNedh27Y/kp5dEE17AopTe tqLUjB2QfcilRCICW+O90HzNz56eS+fi25DTL1og+HzzfvahvnoZXLk/7uY9hr/j8VYa auaiP4+wOb1XY16iKWyCNIDHd01Fe9GxwpkAaiowHaP1OloPbKZ1PjTCyiqATiVQfR6V lOSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kiaVpz1eUfDqE52UW9rfQ/0tpqjiTOXtuh3HRB0EhLk=; b=PzCiuAHVcNdn94A+Qnq6vZOf6C42UBi0PCGYgotn1Oe2qoB2lFsA5VF/OluFxvfxgj /ZlBsb7gqCCLIB5Z1y4r+y6dlxjZT5MOtDoWbSH4pC3aYr+CTdXC5V6W9KK+T+dzvUYY IMd6OPgCQh6T6YQIsEC84uaBXBDtFzXzyUncfS+HxPdJAqQdEPggJcaguYOHv2rX0cpF uEPUjywleMqxI9RPVnFlpc2+PdOlkYqv23V4nFpve8swhflrerF/qMkGgDoBGbYCF60I x5Jx2gH0yt6MlS6p5+GeRwVLQB3dHhDMHh7KJw15VchABz3v+El6fH7hienjQfcv58Xq TyZQ== X-Gm-Message-State: AOAM533QC9VO5akF/zROeGHBNYczc/XTdtKkCvZySQzOOKSh7ECpjPKV Sg0Rrq26ev8B6rHj0qtchyU= X-Google-Smtp-Source: ABdhPJy32tmp8NybQjxKq745ldaozsmbaAs7o3W5RY1yw4zX9siucDBSA5IoMjvGbdeQ6Pvy3b4L7A== X-Received: by 2002:a17:906:58d2:b0:6fd:daa7:3a6e with SMTP id e18-20020a17090658d200b006fddaa73a6emr12977265ejs.0.1652648463193; Sun, 15 May 2022 14:01:03 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id w12-20020aa7da4c000000b0042ab649183asm28917eds.35.2022.05.15.14.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 14:01:02 -0700 (PDT) From: Robert Marko To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tdas@codeaurora.org, absahu@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v4 11/11] arm64: dts: ipq8074: add USB power domains Date: Sun, 15 May 2022 23:00:48 +0200 Message-Id: <20220515210048.483898-11-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515210048.483898-1-robimarko@gmail.com> References: <20220515210048.483898-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add USB power domains provided by GCC GDSCs. Add the required #power-domain-cells to the GCC as well. Signed-off-by: Robert Marko --- Changes in v4: * Alphabetically sort the GCC cells properties --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index ba81c510dd39..4d278151cfcf 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -382,6 +382,7 @@ gcc: gcc@1800000 { compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; #clock-cells = <0x1>; + #power-domain-cells = <1>; #reset-cells = <0x1>; }; @@ -610,6 +611,8 @@ usb_0: usb@8af8800 { <133330000>, <19200000>; + power-domains = <&gcc USB0_GDSC>; + resets = <&gcc GCC_USB0_BCR>; status = "disabled"; @@ -650,6 +653,8 @@ usb_1: usb@8cf8800 { <133330000>, <19200000>; + power-domains = <&gcc USB1_GDSC>; + resets = <&gcc GCC_USB1_BCR>; status = "disabled";