From patchwork Mon May 16 16:06:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851030 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ECB8C433F5 for ; Mon, 16 May 2022 16:07:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245631AbiEPQHy (ORCPT ); Mon, 16 May 2022 12:07:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245725AbiEPQHp (ORCPT ); Mon, 16 May 2022 12:07:45 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98D9737A90; Mon, 16 May 2022 09:07:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 33DD760FF0; Mon, 16 May 2022 16:07:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C11BBC385AA; Mon, 16 May 2022 16:07:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717262; bh=jjinRlKFxifScyEw3OjetYoQ52Kq5EtAMT5xBGYx7aA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EpwkWTUByEhFiRMI9BJxFC8C1LSTZEt75kW4RdxXupXCUZQXPHs1VspfG6Xp+FR+n TrjRKGpPPxt3YzZuGaYvgdgB5ldyt3q4bxkzE3krvqQDEudVof11C2r3PytplSOqlo PJYb2L3W4oAG81w4BJzxT9ngbRZq6pjRn2iPcXcN/ZoVQhvknMf7PC/yTS77hr+0t9 PukHu6Fwa/e+QAADrDMP/UPnqAKCeZtLzqN4U11m7D1oSoT1+LpbVeJrfouKaCKYQH ocKAeCR9k/e7v6VDXA/3dxQrsAmC2cpImLezD/vQHZ5REdlyUpdAJyl3CMqEEqDr6J jf6r9YmrP+dBA== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 01/15] arm64: dts: mediatek: mt7986: introduce ethernet nodes Date: Mon, 16 May 2022 18:06:28 +0200 Message-Id: <2d74a009757a558a26f74d7c9c8070af57926be5.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Introduce ethernet nodes in mt7986 bindings in order to enable mt7986a/mt7986b ethernet support. Co-developed-by: Sam Shih Signed-off-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 74 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 39 +++++++++++ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 70 ++++++++++++++++++ 3 files changed, 183 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 21e420829572..882277a52b69 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -25,6 +25,80 @@ memory@40000000 { }; }; +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 0>; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 694acf8f5b70..d2636a0ed152 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -222,6 +222,45 @@ ethsys: syscon@15000000 { #reset-cells = <1>; }; + eth: ethernet@15100000 { + compatible = "mediatek,mt7986-eth"; + reg = <0 0x15100000 0 0x80000>; + interrupts = , + , + , + ; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&sgmiisys0 CLK_SGMII0_TX250M_EN>, + <&sgmiisys0 CLK_SGMII0_RX250M_EN>, + <&sgmiisys0 CLK_SGMII0_CDR_REF>, + <&sgmiisys0 CLK_SGMII0_CDR_FB>, + <&sgmiisys1 CLK_SGMII1_TX250M_EN>, + <&sgmiisys1 CLK_SGMII1_RX250M_EN>, + <&sgmiisys1 CLK_SGMII1_CDR_REF>, + <&sgmiisys1 CLK_SGMII1_CDR_FB>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "netsys0", "netsys1"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index d73467ea3641..0f49d5764ff3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -28,3 +28,73 @@ memory@40000000 { &uart0 { status = "okay"; }; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; From patchwork Mon May 16 16:06:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851031 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BFB4C43217 for ; Mon, 16 May 2022 16:07:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245641AbiEPQH4 (ORCPT ); Mon, 16 May 2022 12:07:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245738AbiEPQHu (ORCPT ); Mon, 16 May 2022 12:07:50 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C36B37A90; Mon, 16 May 2022 09:07:48 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 705A2CE16C9; Mon, 16 May 2022 16:07:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1524FC3411A; Mon, 16 May 2022 16:07:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717265; bh=aSYMxoghmBGi6PfPfKaZsOsTEC8kXQeaqa+ZGO11hk8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ahRiq8qzeZmvXj2gpcyNfY6uxf8QpCXe5OUzQac4DziIFYOwhGI5U8rvF0Qm0JKaH ZnbgP+VtopvVLZ3z7tlItBnq5hI2NpgDBpH+QdT6LW1SH7Tkz3CHENfkKWUFAnUtpV JSaE2Z5YIRDm4UJVqhJZtAddLvBWssWoTDjlF3KGbSpD31QyVar2repVofv/TzA9If M+0hLSdCypvI4wg0K/mQtsSsN/jTclJuYdKIhz6VYyFw45eEqZCu0DFgCLYdVB6zac ah7x8kepn7jhM+bn00CP+/74Kzf4cB0Pq2zvt2pPbtcsXa2uMMPkHvKQbKC3dpHpg9 WwEK5X0qJI1Xg== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 02/15] dt-bindings: net: mediatek,net: add mt7986-eth binding Date: Mon, 16 May 2022 18:06:29 +0200 Message-Id: X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Introduce dts bindings for mt7986 soc in mediatek,net.yaml. Signed-off-by: Lorenzo Bianconi Reviewed-by: Rob Herring --- .../devicetree/bindings/net/mediatek,net.yaml | 141 +++++++++++++++++- 1 file changed, 139 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml index 43cc4024ef98..699164dd1295 100644 --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt7623-eth - mediatek,mt7622-eth - mediatek,mt7629-eth + - mediatek,mt7986-eth - ralink,rt5350-eth reg: @@ -28,7 +29,7 @@ properties: interrupts: minItems: 3 - maxItems: 3 + maxItems: 4 power-domains: maxItems: 1 @@ -88,6 +89,9 @@ allOf: - mediatek,mt7623-eth then: properties: + interrupts: + maxItems: 3 + clocks: minItems: 4 maxItems: 4 @@ -112,6 +116,9 @@ allOf: const: mediatek,mt7622-eth then: properties: + interrupts: + maxItems: 3 + clocks: minItems: 11 maxItems: 11 @@ -155,6 +162,9 @@ allOf: const: mediatek,mt7629-eth then: properties: + interrupts: + maxItems: 3 + clocks: minItems: 17 maxItems: 17 @@ -189,6 +199,42 @@ allOf: minItems: 2 maxItems: 2 + - if: + properties: + compatible: + contains: + const: mediatek,mt7986-eth + then: + properties: + interrupts: + minItems: 4 + + clocks: + minItems: 15 + maxItems: 15 + + clock-names: + items: + - const: fe + - const: gp2 + - const: gp1 + - const: wocpu1 + - const: wocpu0 + - const: sgmii_tx250m + - const: sgmii_rx250m + - const: sgmii_cdr_ref + - const: sgmii_cdr_fb + - const: sgmii2_tx250m + - const: sgmii2_rx250m + - const: sgmii2_cdr_ref + - const: sgmii2_cdr_fb + - const: netsys0 + - const: netsys1 + + mediatek,sgmiisys: + minItems: 2 + maxItems: 2 + patternProperties: "^mac@[0-1]$": type: object @@ -219,7 +265,6 @@ required: - interrupts - clocks - clock-names - - power-domains - mediatek,ethsys unevaluatedProperties: false @@ -295,3 +340,95 @@ examples: }; }; }; + + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + eth: ethernet@15100000 { + #define CLK_ETH_FE_EN 0 + #define CLK_ETH_WOCPU1_EN 3 + #define CLK_ETH_WOCPU0_EN 4 + #define CLK_TOP_NETSYS_SEL 43 + #define CLK_TOP_NETSYS_500M_SEL 44 + #define CLK_TOP_NETSYS_2X_SEL 46 + #define CLK_TOP_SGM_325M_SEL 47 + #define CLK_APMIXED_NET2PLL 1 + #define CLK_APMIXED_SGMPLL 3 + + compatible = "mediatek,mt7986-eth"; + reg = <0 0x15100000 0 0x80000>; + interrupts = , + , + , + ; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&sgmiisys0 CLK_SGMII_TX250M_EN>, + <&sgmiisys0 CLK_SGMII_RX250M_EN>, + <&sgmiisys0 CLK_SGMII_CDR_REF>, + <&sgmiisys0 CLK_SGMII_CDR_FB>, + <&sgmiisys1 CLK_SGMII_TX250M_EN>, + <&sgmiisys1 CLK_SGMII_RX250M_EN>, + <&sgmiisys1 CLK_SGMII_CDR_REF>, + <&sgmiisys1 CLK_SGMII_CDR_FB>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "netsys0", "netsys1"; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + + #address-cells = <1>; + #size-cells = <0>; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy5: ethernet-phy@0 { + compatible = "ethernet-phy-id67c9.de0a"; + phy-mode = "2500base-x"; + reset-gpios = <&pio 6 1>; + reset-deassert-us = <20000>; + reg = <5>; + }; + + phy6: ethernet-phy@1 { + compatible = "ethernet-phy-id67c9.de0a"; + phy-mode = "2500base-x"; + reg = <6>; + }; + }; + + mac0: mac@0 { + compatible = "mediatek,eth-mac"; + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + reg = <0>; + }; + + mac1: mac@1 { + compatible = "mediatek,eth-mac"; + phy-mode = "2500base-x"; + phy-handle = <&phy6>; + reg = <1>; + }; + }; + }; From patchwork Mon May 16 16:06:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851032 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DE49C433EF for ; Mon, 16 May 2022 16:08:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245652AbiEPQIA (ORCPT ); Mon, 16 May 2022 12:08:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245260AbiEPQHx (ORCPT ); Mon, 16 May 2022 12:07:53 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CC1037A90; Mon, 16 May 2022 09:07:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id BF6BECE16E4; Mon, 16 May 2022 16:07:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5873EC34113; Mon, 16 May 2022 16:07:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717269; bh=zo+PQVFuA+GxPo/d6/CtXgd7jFrLzi0gI150KZBcaLA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FUjrw4Hx8KjxReUXnNdcEyzFAfRLwM59ktxCL724Q6Pm3d6WPZ3pf/ceINM+NVUym NkAXEX+CuiKec6gxClNPld9HxIl+hVX7yXCMQtIdWNBOF10JILmFlgiRkSEp1TYakl 6iF+t3ZsmUKV7gHY9n+EZ86FlzAJHRxtbyBcyvrKoP3eUGoNWLSmJ6QE81HU9D4nj/ tJ9FvyTZqmToUwswqYKPVDA55AiAIYxLs+VQ7S1/VLJpofPjNz5U7EuFmp9jku3Gsv QH4bOKRRpIet5686a8sREg9FN6S1dAobGXDL26vDVZ6/Q1itCu2cAL37Nq024YqlSs BxgvNDcuALvJg== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 03/15] net: ethernet: mtk_eth_soc: move tx dma desc configuration in mtk_tx_set_dma_desc Date: Mon, 16 May 2022 18:06:30 +0200 Message-Id: <56f87927844502969dd6929e9137c47e54c99c00.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Move tx dma descriptor configuration in mtk_tx_set_dma_desc routine. This is a preliminary patch to introduce mt7986 ethernet support since it relies on a different tx dma descriptor layout. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 105 +++++++++++--------- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++ 2 files changed, 67 insertions(+), 49 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 31c5da5d6b72..085c740779de 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -918,18 +918,51 @@ static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, } } +static void mtk_tx_set_dma_desc(struct net_device *dev, struct mtk_tx_dma *desc, + struct mtk_tx_dma_desc_info *info) +{ + struct mtk_mac *mac = netdev_priv(dev); + u32 data; + + WRITE_ONCE(desc->txd1, info->addr); + + data = TX_DMA_SWC | TX_DMA_PLEN0(info->size); + if (info->last) + data |= TX_DMA_LS0; + WRITE_ONCE(desc->txd3, data); + + data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ + if (info->first) { + if (info->gso) + data |= TX_DMA_TSO; + /* tx checksum offload */ + if (info->csum) + data |= TX_DMA_CHKSUM; + /* vlan header offload */ + if (info->vlan) + data |= TX_DMA_INS_VLAN | info->vlan_tci; + } + WRITE_ONCE(desc->txd4, data); +} + static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, int tx_num, struct mtk_tx_ring *ring, bool gso) { + struct mtk_tx_dma_desc_info txd_info = { + .size = skb_headlen(skb), + .gso = gso, + .csum = skb->ip_summed == CHECKSUM_PARTIAL, + .vlan = skb_vlan_tag_present(skb), + .vlan_tci = skb_vlan_tag_get(skb), + .first = true, + .last = !skb_is_nonlinear(skb), + }; struct mtk_mac *mac = netdev_priv(dev); struct mtk_eth *eth = mac->hw; struct mtk_tx_dma *itxd, *txd; struct mtk_tx_dma *itxd_pdma, *txd_pdma; struct mtk_tx_buf *itx_buf, *tx_buf; - dma_addr_t mapped_addr; - unsigned int nr_frags; int i, n_desc = 1; - u32 txd4 = 0, fport; int k = 0; itxd = ring->next_free; @@ -937,49 +970,32 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, if (itxd == ring->last_free) return -ENOMEM; - /* set the forward port */ - fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; - txd4 |= fport; - itx_buf = mtk_desc_to_tx_buf(ring, itxd); memset(itx_buf, 0, sizeof(*itx_buf)); - if (gso) - txd4 |= TX_DMA_TSO; - - /* TX Checksum offload */ - if (skb->ip_summed == CHECKSUM_PARTIAL) - txd4 |= TX_DMA_CHKSUM; - - /* VLAN header offload */ - if (skb_vlan_tag_present(skb)) - txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); - - mapped_addr = dma_map_single(eth->dma_dev, skb->data, - skb_headlen(skb), DMA_TO_DEVICE); - if (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr))) + txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, + DMA_TO_DEVICE); + if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) return -ENOMEM; - WRITE_ONCE(itxd->txd1, mapped_addr); + mtk_tx_set_dma_desc(dev, itxd, &txd_info); + itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; - setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb), + setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, k++); /* TX SG offload */ txd = itxd; txd_pdma = qdma_to_pdma(ring, txd); - nr_frags = skb_shinfo(skb)->nr_frags; - for (i = 0; i < nr_frags; i++) { + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; unsigned int offset = 0; int frag_size = skb_frag_size(frag); while (frag_size) { - bool last_frag = false; - unsigned int frag_map_size; bool new_desc = true; if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) || @@ -994,23 +1010,17 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, new_desc = false; } - - frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); - mapped_addr = skb_frag_dma_map(eth->dma_dev, frag, offset, - frag_map_size, - DMA_TO_DEVICE); - if (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr))) + memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); + txd_info.size = min(frag_size, MTK_TX_DMA_BUF_LEN); + txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && + !(frag_size - txd_info.size); + txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, + offset, txd_info.size, + DMA_TO_DEVICE); + if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) goto err_dma; - if (i == nr_frags - 1 && - (frag_size - frag_map_size) == 0) - last_frag = true; - - WRITE_ONCE(txd->txd1, mapped_addr); - WRITE_ONCE(txd->txd3, (TX_DMA_SWC | - TX_DMA_PLEN0(frag_map_size) | - last_frag * TX_DMA_LS0)); - WRITE_ONCE(txd->txd4, fport); + mtk_tx_set_dma_desc(dev, txd, &txd_info); tx_buf = mtk_desc_to_tx_buf(ring, txd); if (new_desc) @@ -1020,20 +1030,17 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; - setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr, - frag_map_size, k++); + setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, + txd_info.size, k++); - frag_size -= frag_map_size; - offset += frag_map_size; + frag_size -= txd_info.size; + offset += txd_info.size; } } /* store skb to cleanup */ itx_buf->skb = skb; - WRITE_ONCE(itxd->txd4, txd4); - WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | - (!nr_frags * TX_DMA_LS0))); if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { if (k & 0x1) txd_pdma->txd2 |= TX_DMA_LS0; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index b04977fa84f6..5d940315c7ba 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -844,6 +844,17 @@ enum mkt_eth_capabilities { MTK_MUX_U3_GMAC2_TO_QPHY | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) +struct mtk_tx_dma_desc_info { + dma_addr_t addr; + u32 size; + u16 vlan_tci; + u8 gso:1; + u8 csum:1; + u8 vlan:1; + u8 first:1; + u8 last:1; +}; + /* struct mtk_eth_data - This is the structure holding all differences * among various plaforms * @ana_rgc3: The offset for register ANA_RGC3 related to From patchwork Mon May 16 16:06:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851033 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E3FEC433EF for ; Mon, 16 May 2022 16:08:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237279AbiEPQIB (ORCPT ); Mon, 16 May 2022 12:08:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245614AbiEPQHy (ORCPT ); Mon, 16 May 2022 12:07:54 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6842537AAF; Mon, 16 May 2022 09:07:53 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0F17960FFC; Mon, 16 May 2022 16:07:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9CA28C385AA; Mon, 16 May 2022 16:07:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717272; bh=a3XU0e49ixn1FJ0IrvFS5xrudvBm8/hSAT0hJzRlaqs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tVMW0n2ZJuDDcaqWRaEFU7oRXI20dQn3aj4KCwUH0MCKizNkVddTxMiJCc1654EXR xpieU9dmDdiP5BzOq6ObqJL34gcDsSaB1zkdY6omvjKE65hjI7vaIk8JxRl0yNw0Is PGnI6Ayz9R1ifIwFbS1PJykhgaJWpM+AexAl+sEXbZemq6WTbrz15z/tQwseSy1j45 A3Q7kdIOA9sZfx0r1G7niA3SGCcdbGoBt+x44Q6jSrCIqCov4NZcyM8KTepWNtoNQk sGeWaUKV6xLLGRPGTfYTwdzUQ7ceksU8DdNEyj28jukYTctVsgUvu9AA94q5PTMDnT UoWX19heEZbWA== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 04/15] net: ethernet: mtk_eth_soc: add txd_size to mtk_soc_data Date: Mon, 16 May 2022 18:06:31 +0200 Message-Id: <22bd1bd88c09205b9bf83ea4c3ab030d5dc6e670.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org In order to remove mtk_tx_dma size dependency, introduce txd_size in mtk_soc_data data structure. Rely on txd_size in mtk_init_fq_dma() and mtk_dma_free() routines. This is a preliminary patch to add mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 47 +++++++++++++++------ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++ 2 files changed, 38 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 085c740779de..cde66463bf98 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -784,20 +784,20 @@ static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd, /* the qdma core needs scratch memory to be setup */ static int mtk_init_fq_dma(struct mtk_eth *eth) { + const struct mtk_soc_data *soc = eth->soc; dma_addr_t phy_ring_tail; int cnt = MTK_DMA_SIZE; dma_addr_t dma_addr; int i; eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, - cnt * sizeof(struct mtk_tx_dma), + cnt * soc->txrx.txd_size, ð->phy_scratch_ring, GFP_ATOMIC); if (unlikely(!eth->scratch_ring)) return -ENOMEM; - eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, - GFP_KERNEL); + eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); if (unlikely(!eth->scratch_head)) return -ENOMEM; @@ -807,16 +807,19 @@ static int mtk_init_fq_dma(struct mtk_eth *eth) if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) return -ENOMEM; - phy_ring_tail = eth->phy_scratch_ring + - (sizeof(struct mtk_tx_dma) * (cnt - 1)); + phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); for (i = 0; i < cnt; i++) { - eth->scratch_ring[i].txd1 = - (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); + struct mtk_tx_dma *txd; + + txd = (void *)eth->scratch_ring + i * soc->txrx.txd_size; + txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; if (i < cnt - 1) - eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + - ((i + 1) * sizeof(struct mtk_tx_dma))); - eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); + txd->txd2 = eth->phy_scratch_ring + + (i + 1) * soc->txrx.txd_size; + + txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); + txd->txd4 = 0; } mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); @@ -2108,6 +2111,7 @@ static int mtk_dma_init(struct mtk_eth *eth) static void mtk_dma_free(struct mtk_eth *eth) { + const struct mtk_soc_data *soc = eth->soc; int i; for (i = 0; i < MTK_MAC_COUNT; i++) @@ -2115,9 +2119,8 @@ static void mtk_dma_free(struct mtk_eth *eth) netdev_reset_queue(eth->netdev[i]); if (eth->scratch_ring) { dma_free_coherent(eth->dma_dev, - MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), - eth->scratch_ring, - eth->phy_scratch_ring); + MTK_DMA_SIZE * soc->txrx.txd_size, + eth->scratch_ring, eth->phy_scratch_ring); eth->scratch_ring = NULL; eth->phy_scratch_ring = 0; } @@ -3353,6 +3356,9 @@ static const struct mtk_soc_data mt2701_data = { .hw_features = MTK_HW_FEATURES, .required_clks = MT7623_CLKS_BITMAP, .required_pctl = true, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + }, }; static const struct mtk_soc_data mt7621_data = { @@ -3361,6 +3367,9 @@ static const struct mtk_soc_data mt7621_data = { .required_clks = MT7621_CLKS_BITMAP, .required_pctl = false, .offload_version = 2, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + }, }; static const struct mtk_soc_data mt7622_data = { @@ -3370,6 +3379,9 @@ static const struct mtk_soc_data mt7622_data = { .required_clks = MT7622_CLKS_BITMAP, .required_pctl = false, .offload_version = 2, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + }, }; static const struct mtk_soc_data mt7623_data = { @@ -3378,6 +3390,9 @@ static const struct mtk_soc_data mt7623_data = { .required_clks = MT7623_CLKS_BITMAP, .required_pctl = true, .offload_version = 2, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + }, }; static const struct mtk_soc_data mt7629_data = { @@ -3386,6 +3401,9 @@ static const struct mtk_soc_data mt7629_data = { .hw_features = MTK_HW_FEATURES, .required_clks = MT7629_CLKS_BITMAP, .required_pctl = false, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + }, }; static const struct mtk_soc_data rt5350_data = { @@ -3393,6 +3411,9 @@ static const struct mtk_soc_data rt5350_data = { .hw_features = MTK_HW_FEATURES_MT7628, .required_clks = MT7628_CLKS_BITMAP, .required_pctl = false, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + }, }; const struct of_device_id of_mtk_match[] = { diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 5d940315c7ba..495f623b62ef 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -865,6 +865,7 @@ struct mtk_tx_dma_desc_info { * the target SoC * @required_pctl A bool value to show whether the SoC requires * the extra setup for those pins used by GMAC. + * @txd_size TX DMA descriptor size. */ struct mtk_soc_data { u32 ana_rgc3; @@ -873,6 +874,9 @@ struct mtk_soc_data { bool required_pctl; u8 offload_version; netdev_features_t hw_features; + struct { + u32 txd_size; + } txrx; }; /* currently no SoC has more than 2 macs */ From patchwork Mon May 16 16:06:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851034 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 895E1C433FE for ; Mon, 16 May 2022 16:08:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245634AbiEPQIM (ORCPT ); Mon, 16 May 2022 12:08:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245658AbiEPQIA (ORCPT ); Mon, 16 May 2022 12:08:00 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5D9C37BE3; Mon, 16 May 2022 09:07:58 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0433DB8125F; Mon, 16 May 2022 16:07:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E0FF0C34115; Mon, 16 May 2022 16:07:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717275; bh=La4DfYogy1OZ7h+SajH4VcUJwX9hHdoQB3uCgc5dP00=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l3ZL7vmOBzmBvQok17XKRQckajdm7HayZ0KgyJslXuOC+vSVu0jBoRzaHaMooI6yv rEILzktFKPcwCnBINIFSy843I+aovwMcGAmlCjMIB3hdHiRccgznayaPo1albC2GOr R5G1sa6WfUlHEIuCvY3XFXqIpwHB4jDM9oVB0uWN8iqJA8rxV4cvgMR9AnkKaWUW86 TSDKTru+AkcvAIy5ZkuNbrVoAzzDB+YaVjJn+WASqQR9VaUEgXOZfm+urA4Xtr8goV zeSApdVACOqJr35j3xsnICxVlK8KY9ypT5Qh5lyJSnuRWa6/QMXspzkMnCMD5p/Web AbyFgSY1rn+Zw== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 05/15] net: ethernet: mtk_eth_soc: rely on txd_size in mtk_tx_alloc/mtk_tx_clean Date: Mon, 16 May 2022 18:06:32 +0200 Message-Id: X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org This is a preliminary patch to add mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 39 ++++++++++++--------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index cde66463bf98..a48e93792db1 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -1568,25 +1568,30 @@ static int mtk_napi_rx(struct napi_struct *napi, int budget) static int mtk_tx_alloc(struct mtk_eth *eth) { + const struct mtk_soc_data *soc = eth->soc; struct mtk_tx_ring *ring = ð->tx_ring; - int i, sz = sizeof(*ring->dma); + struct mtk_tx_dma *txd; + int i; ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), GFP_KERNEL); if (!ring->buf) goto no_tx_mem; - ring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, + ring->dma = dma_alloc_coherent(eth->dma_dev, + MTK_DMA_SIZE * soc->txrx.txd_size, &ring->phys, GFP_ATOMIC); if (!ring->dma) goto no_tx_mem; for (i = 0; i < MTK_DMA_SIZE; i++) { int next = (i + 1) % MTK_DMA_SIZE; - u32 next_ptr = ring->phys + next * sz; + u32 next_ptr = ring->phys + next * soc->txrx.txd_size; - ring->dma[i].txd2 = next_ptr; - ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; + txd = (void *)ring->dma + i * soc->txrx.txd_size; + txd->txd2 = next_ptr; + txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; + txd->txd4 = 0; } /* On MT7688 (PDMA only) this driver uses the ring->dma structs @@ -1594,9 +1599,9 @@ static int mtk_tx_alloc(struct mtk_eth *eth) * descriptors in ring->dma_pdma. */ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { - ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, - &ring->phys_pdma, - GFP_ATOMIC); + ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, + MTK_DMA_SIZE * soc->txrx.txd_size, + &ring->phys_pdma, GFP_ATOMIC); if (!ring->dma_pdma) goto no_tx_mem; @@ -1609,8 +1614,9 @@ static int mtk_tx_alloc(struct mtk_eth *eth) ring->dma_size = MTK_DMA_SIZE; atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); ring->next_free = &ring->dma[0]; - ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; - ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz)); + ring->last_free = (void *)txd; + ring->last_free_ptr = (u32)(ring->phys + + (MTK_DMA_SIZE - 1) * soc->txrx.txd_size); ring->thresh = MAX_SKB_FRAGS; /* make sure that all changes to the dma ring are flushed before we @@ -1622,7 +1628,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); mtk_w32(eth, - ring->phys + ((MTK_DMA_SIZE - 1) * sz), + ring->phys + (MTK_DMA_SIZE - 1) * soc->txrx.txd_size, MTK_QTX_CRX_PTR); mtk_w32(eth, ring->last_free_ptr, MTK_QTX_DRX_PTR); mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, @@ -1642,6 +1648,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) static void mtk_tx_clean(struct mtk_eth *eth) { + const struct mtk_soc_data *soc = eth->soc; struct mtk_tx_ring *ring = ð->tx_ring; int i; @@ -1654,17 +1661,15 @@ static void mtk_tx_clean(struct mtk_eth *eth) if (ring->dma) { dma_free_coherent(eth->dma_dev, - MTK_DMA_SIZE * sizeof(*ring->dma), - ring->dma, - ring->phys); + MTK_DMA_SIZE * soc->txrx.txd_size, + ring->dma, ring->phys); ring->dma = NULL; } if (ring->dma_pdma) { dma_free_coherent(eth->dma_dev, - MTK_DMA_SIZE * sizeof(*ring->dma_pdma), - ring->dma_pdma, - ring->phys_pdma); + MTK_DMA_SIZE * soc->txrx.txd_size, + ring->dma_pdma, ring->phys_pdma); ring->dma_pdma = NULL; } } From patchwork Mon May 16 16:06:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851035 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1DC9C433EF for ; Mon, 16 May 2022 16:08:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245635AbiEPQIU (ORCPT ); Mon, 16 May 2022 12:08:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245647AbiEPQIJ (ORCPT ); Mon, 16 May 2022 12:08:09 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2789937BFA; Mon, 16 May 2022 09:08:01 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 4946BB81261; Mon, 16 May 2022 16:08:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30546C385AA; Mon, 16 May 2022 16:07:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717279; bh=Fj9JFlaKbmnQVBZzLkZZrJLpdmId1DncPM5qdcLaj44=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t0uT+7yr1+QxZ57GgvwPGRcy5xV+IkFmBQpDevHy3yN/WIr12/u3x+yFmFpkJpw+U wX2a6YYLkx088VZpMEb8sECOqsQCA8pfVQDXLlHXCRcs1xufpwjq9ExOtRBJiE5Fcx hYl/flNzOBhgVuBaLdI87JOTigCvk9QSItrgrlUEdKli/4EhbUkegLcYVC7uaVwVmD gmdNGRkDpZJ6KgZHJS8oVN/E5JXOqXDSsKM6h1dVbT+AvewEgy0uuxToO1VMsT7WZg sg1kAXLeBh9KBOxGK33UbiZbFXNR6fPBngNTvruPFf5xPVKmkt0eCBOXQQJsJ/JaaD Dv6hZ/r6JPmzg== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 06/15] net: ethernet: mtk_eth_soc: rely on txd_size in mtk_desc_to_tx_buf Date: Mon, 16 May 2022 18:06:33 +0200 Message-Id: <185cc16faadc2b4b1fa47d550ef59d2bfd4b0d23.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org This is a preliminary patch to add mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 26 ++++++++++++--------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index a48e93792db1..5f0082f92cc7 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -837,10 +837,11 @@ static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) return ret + (desc - ring->phys); } -static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, - struct mtk_tx_dma *txd) +static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, + struct mtk_tx_dma *txd, + u32 txd_size) { - int idx = txd - ring->dma; + int idx = ((void *)txd - (void *)ring->dma) / txd_size; return &ring->buf[idx]; } @@ -962,6 +963,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, }; struct mtk_mac *mac = netdev_priv(dev); struct mtk_eth *eth = mac->hw; + const struct mtk_soc_data *soc = eth->soc; struct mtk_tx_dma *itxd, *txd; struct mtk_tx_dma *itxd_pdma, *txd_pdma; struct mtk_tx_buf *itx_buf, *tx_buf; @@ -973,7 +975,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, if (itxd == ring->last_free) return -ENOMEM; - itx_buf = mtk_desc_to_tx_buf(ring, itxd); + itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); memset(itx_buf, 0, sizeof(*itx_buf)); txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, @@ -1001,7 +1003,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, while (frag_size) { bool new_desc = true; - if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) || + if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (i & 0x1)) { txd = mtk_qdma_phys_to_virt(ring, txd->txd2); txd_pdma = qdma_to_pdma(ring, txd); @@ -1025,7 +1027,8 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, mtk_tx_set_dma_desc(dev, txd, &txd_info); - tx_buf = mtk_desc_to_tx_buf(ring, txd); + tx_buf = mtk_desc_to_tx_buf(ring, txd, + soc->txrx.txd_size); if (new_desc) memset(tx_buf, 0, sizeof(*tx_buf)); tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; @@ -1044,7 +1047,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, /* store skb to cleanup */ itx_buf->skb = skb; - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { + if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { if (k & 0x1) txd_pdma->txd2 |= TX_DMA_LS0; else @@ -1062,7 +1065,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, */ wmb(); - if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { + if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !netdev_xmit_more()) mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); @@ -1076,13 +1079,13 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, err_dma: do { - tx_buf = mtk_desc_to_tx_buf(ring, itxd); + tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); /* unmap dma */ mtk_tx_unmap(eth, tx_buf, false); itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) + if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) itxd_pdma->txd2 = TX_DMA_DESP2_DEF; itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); @@ -1393,7 +1396,8 @@ static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) break; - tx_buf = mtk_desc_to_tx_buf(ring, desc); + tx_buf = mtk_desc_to_tx_buf(ring, desc, + eth->soc->txrx.txd_size); if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) mac = 1; From patchwork Mon May 16 16:06:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851036 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84869C433FE for ; Mon, 16 May 2022 16:08:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245590AbiEPQIb (ORCPT ); Mon, 16 May 2022 12:08:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242263AbiEPQIQ (ORCPT ); Mon, 16 May 2022 12:08:16 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29005381A8; Mon, 16 May 2022 09:08:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id D524ACE16D3; Mon, 16 May 2022 16:08:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 73D72C34116; Mon, 16 May 2022 16:07:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717282; bh=/7JibGmqxINAAC2OLNWW7h4NBtLSDt9RP8nVknEhicc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kfXRNgO2WskOdTn3GnqwOmDwAZhkdOQoiCrQZqwaN2h9LiIGhhMZ6BqKT0ii2/URU tk+NvpBbRlOFdOzQPLYnYxfiWpHa95JIHohZxJCSIW6j368UO5K+fN7G39PZhB386A es2tUU3jSnVmX5INwWrS9lGle8J/FH/RTLRB2qq8rZgD9QC2qxbghjoERXxRK2UqOt Z4QQsRDMoW6qaRv5jdMx65i4GUBMvk4yejBDztaqSAwMVF3WW/WkeleQRRC/56TwvK Q1/JtwGAHl9HwHGwHTCmjmYnEghnvoP+/WArW2wIqRrrd15J6MuAoqUUe4WIqz8Xnv pzaK0cD66eglw== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 07/15] net: ethernet: mtk_eth_soc: rely on txd_size in txd_to_idx Date: Mon, 16 May 2022 18:06:34 +0200 Message-Id: <4e672c71564e1071ff1c94691984173ae9b0b54d.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org This is a preliminary patch to add mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 5f0082f92cc7..a67b22dbaac7 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -852,9 +852,10 @@ static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, return ring->dma_pdma - ring->dma + dma; } -static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma) +static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma, + u32 txd_size) { - return ((void *)dma - (void *)ring->dma) / sizeof(*dma); + return ((void *)dma - (void *)ring->dma) / txd_size; } static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, @@ -1070,8 +1071,10 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, !netdev_xmit_more()) mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); } else { - int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd), - ring->dma_size); + int next_idx; + + next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), + ring->dma_size); mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); } From patchwork Mon May 16 16:06:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851037 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6B46C433FE for ; Mon, 16 May 2022 16:08:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245735AbiEPQIj (ORCPT ); Mon, 16 May 2022 12:08:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245689AbiEPQIR (ORCPT ); Mon, 16 May 2022 12:08:17 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70D863818E; Mon, 16 May 2022 09:08:08 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E7788B81257; Mon, 16 May 2022 16:08:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B8EECC36AE2; Mon, 16 May 2022 16:08:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717285; bh=dyJ5XoChkvP74PxhAd12f/ogtOqmcld4InFdd//3jsA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p4tG3nNgIkOG0h9u/zk1rrinvtvrwF2NBDtC33MLOYbfTudtQG7jDqMFqywiMivhh PzpOqSfjKRAsdHh7kqFJWeV7xXIJx5om6MB6qrIJ4O/M0WpJWvCkmNGYxEGxfyIGzv LTMDw4bp70jV7mr6225cuA8IfbzqBPdd1zjxtPk3Wxhek7bvhYKxgS4WKmIUs0ZpAF ETXRHe7FiVpEqCVgEK3G+sc94CRWFpdZInehEsBqCkDynCBjJrfNp7HvnYYMeFaOJH R/xNU6jMMvLBCuBgL2t5wErpzaFZ0wt5UpYiq75AqaQli6lenHuwYPS8k5Kfc/92Dv B8/ZVdnm4HSog== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 08/15] net: ethernet: mtk_eth_soc: add rxd_size to mtk_soc_data Date: Mon, 16 May 2022 18:06:35 +0200 Message-Id: <5a5ddce4bf8fb08dcbc730864c05a1aa58ec360f.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Similar to tx counterpart, introduce rxd_size in mtk_soc_data data structure. This is a preliminary patch to add mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 13 +++++++++---- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 ++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index a67b22dbaac7..bb628b65a9e5 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -1719,7 +1719,7 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) } ring->dma = dma_alloc_coherent(eth->dma_dev, - rx_dma_size * sizeof(*ring->dma), + rx_dma_size * eth->soc->txrx.rxd_size, &ring->phys, GFP_ATOMIC); if (!ring->dma) return -ENOMEM; @@ -1777,9 +1777,8 @@ static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) if (ring->dma) { dma_free_coherent(eth->dma_dev, - ring->dma_size * sizeof(*ring->dma), - ring->dma, - ring->phys); + ring->dma_size * eth->soc->txrx.rxd_size, + ring->dma, ring->phys); ring->dma = NULL; } } @@ -3370,6 +3369,7 @@ static const struct mtk_soc_data mt2701_data = { .required_pctl = true, .txrx = { .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), }, }; @@ -3381,6 +3381,7 @@ static const struct mtk_soc_data mt7621_data = { .offload_version = 2, .txrx = { .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), }, }; @@ -3393,6 +3394,7 @@ static const struct mtk_soc_data mt7622_data = { .offload_version = 2, .txrx = { .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), }, }; @@ -3404,6 +3406,7 @@ static const struct mtk_soc_data mt7623_data = { .offload_version = 2, .txrx = { .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), }, }; @@ -3415,6 +3418,7 @@ static const struct mtk_soc_data mt7629_data = { .required_pctl = false, .txrx = { .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), }, }; @@ -3425,6 +3429,7 @@ static const struct mtk_soc_data rt5350_data = { .required_pctl = false, .txrx = { .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), }, }; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 495f623b62ef..150d692633fa 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -866,6 +866,7 @@ struct mtk_tx_dma_desc_info { * @required_pctl A bool value to show whether the SoC requires * the extra setup for those pins used by GMAC. * @txd_size TX DMA descriptor size. + * @rxd_size RX DMA descriptor size. */ struct mtk_soc_data { u32 ana_rgc3; @@ -876,6 +877,7 @@ struct mtk_soc_data { netdev_features_t hw_features; struct { u32 txd_size; + u32 rxd_size; } txrx; }; From patchwork Mon May 16 16:06:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851038 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96296C433F5 for ; Mon, 16 May 2022 16:08:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245703AbiEPQIl (ORCPT ); Mon, 16 May 2022 12:08:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245695AbiEPQIR (ORCPT ); Mon, 16 May 2022 12:08:17 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D571637BE3; Mon, 16 May 2022 09:08:09 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 71BBF60FF0; Mon, 16 May 2022 16:08:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 08663C36AE3; Mon, 16 May 2022 16:08:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717288; bh=t9Pe6TXTNALE+q/ldJlquf7ThnvPV79cToZ2NboGpxs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X0D/+6G8mP/AWzIsQLvSuw0LSpd18Bv0OLjcNWim29BH7jtv1nZGuB3jv5F8SHuFX crOzUQyqTCOVNLcPDsUePdv2wV4QCFoVrnMV4Qtg1Mdj0/JxQU0paIHbmFDUWJ/1c/ cqUy/pvwTP/q1vLydTH4y+dqiWVogccDDblqvdr4O+k4swkQA0O+2R5KojnVg94fHA HXYJw1Y3cV24YPFkpVk+2Co8XDW1Zt9OMEwsMFDPLqmTYGG+NOYE3BNARTyoY2LC+Z fNIN3UkmKkDGGLzFGGCPYH0TOsuP2W38+Zi8Db6Eu4mlkPZNSroEbxTrepfvCwsxuU 76IiZ90ujIIQQ== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 09/15] net: ethernet: mtk_eth_soc: rely on txd_size field in mtk_poll_tx/mtk_poll_rx Date: Mon, 16 May 2022 18:06:36 +0200 Message-Id: X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org This is a preliminary to ad mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index bb628b65a9e5..d431311578e8 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -1211,9 +1211,12 @@ static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) return ð->rx_ring[0]; for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { + struct mtk_rx_dma *rxd; + ring = ð->rx_ring[i]; idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); - if (ring->dma[idx].rxd2 & RX_DMA_DONE) { + rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size; + if (rxd->rxd2 & RX_DMA_DONE) { ring->calc_idx_update = true; return ring; } @@ -1264,7 +1267,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, goto rx_done; idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); - rxd = &ring->dma[idx]; + rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size; data = ring->data[idx]; if (!mtk_rx_get_desc(&trxd, rxd)) @@ -1453,7 +1456,7 @@ static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, mtk_tx_unmap(eth, tx_buf, true); - desc = &ring->dma[cpu]; + desc = (void *)ring->dma + cpu * eth->soc->txrx.txd_size; ring->last_free = desc; atomic_inc(&ring->free_count); From patchwork Mon May 16 16:06:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851039 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12DD8C433FE for ; Mon, 16 May 2022 16:08:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245648AbiEPQIm (ORCPT ); Mon, 16 May 2022 12:08:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245708AbiEPQIX (ORCPT ); Mon, 16 May 2022 12:08:23 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BDAF3878F; Mon, 16 May 2022 09:08:14 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5C9E1B8125B; Mon, 16 May 2022 16:08:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4F3D8C36AE5; Mon, 16 May 2022 16:08:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717292; bh=1BP0hNAhVdSiaByBwuA4bapH8q0B/c5pl0i6BWJcHFU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qIS/fgeOVOq4M/JM/e6N7JJbGjwpKZ5YYTI9q/vQDq4f81wBLps+6hOIlYF/JtBVs GoqrZ24GOGAL6RWWN45OxXUSaSSLWE2WUsTWe2mhJNn16lztx4uxzT6BWIa/sent7x ytaVvf1OCdBYIfU8vM0una1WQaRJZd5iE/HK+Zrz4BmON+/TN6Qy1dslV4mI+YWQsz +W6od/m2RpTuBPU09D6MINKCWtDGKSb189guLmyBuPeo0ykJ8i3yvfNzuQ96sIEw3/ FvEhdzbvDALcKKtCIWfyIfO+3syI+fQGnYKAyoNvJ9ju41pV0p6FQZXjbgb8C7ZODf HdoLaWeGVLRpA== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 10/15] net: ethernet: mtk_eth_soc: rely on rxd_size field in mtk_rx_alloc/mtk_rx_clean Date: Mon, 16 May 2022 18:06:37 +0200 Message-Id: X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org This is a preliminary patch to add mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 26 ++++++++++++++------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index d431311578e8..1e2fddc2bdcb 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -1728,18 +1728,25 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) return -ENOMEM; for (i = 0; i < rx_dma_size; i++) { + struct mtk_rx_dma *rxd; + dma_addr_t dma_addr = dma_map_single(eth->dma_dev, ring->data[i] + NET_SKB_PAD + eth->ip_align, ring->buf_size, DMA_FROM_DEVICE); if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) return -ENOMEM; - ring->dma[i].rxd1 = (unsigned int)dma_addr; + + rxd = (void *)ring->dma + i * eth->soc->txrx.rxd_size; + rxd->rxd1 = (unsigned int)dma_addr; if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) - ring->dma[i].rxd2 = RX_DMA_LSO; + rxd->rxd2 = RX_DMA_LSO; else - ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); + rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); + + rxd->rxd3 = 0; + rxd->rxd4 = 0; } ring->dma_size = rx_dma_size; ring->calc_idx_update = false; @@ -1764,14 +1771,17 @@ static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) if (ring->data && ring->dma) { for (i = 0; i < ring->dma_size; i++) { + struct mtk_rx_dma *rxd; + if (!ring->data[i]) continue; - if (!ring->dma[i].rxd1) + + rxd = (void *)ring->dma + i * eth->soc->txrx.rxd_size; + if (!rxd->rxd1) continue; - dma_unmap_single(eth->dma_dev, - ring->dma[i].rxd1, - ring->buf_size, - DMA_FROM_DEVICE); + + dma_unmap_single(eth->dma_dev, rxd->rxd1, + ring->buf_size, DMA_FROM_DEVICE); skb_free_frag(ring->data[i]); } kfree(ring->data); From patchwork Mon May 16 16:06:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851040 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A16E4C43217 for ; Mon, 16 May 2022 16:08:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245706AbiEPQIn (ORCPT ); Mon, 16 May 2022 12:08:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245713AbiEPQIY (ORCPT ); Mon, 16 May 2022 12:08:24 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28DEB37BED; Mon, 16 May 2022 09:08:18 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 9EBE3B8125A; Mon, 16 May 2022 16:08:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94B7AC34115; Mon, 16 May 2022 16:08:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717295; bh=iMrlZwNouCsE2/lev2Gal4DO5Wl2oRqF5YpiHwwXe6A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RFSyEEAPCprMk7bpOFnhRl8HuZ466OOyjQ/mkFkNVGxg9dHN46si0Lx9GK36Qlct2 1+Zu18+xg9VjHGyRLnfdEEdWN58I4HKxkTith3r1DnEG/G3ki3+/Xyhsv8ycF6LBZh U96W65JRKAdgkvSRgFb5VgYa9KMspIjwtgbuuriUtmPGrF8Iyp9yW/ihUEexugNEA+ zuOZDt9DdE0GRaoeMTrB37ehVlJWyQgnX38Cm+JBIc6qYWd+jfXa1/q+Enn7BFgEne qhDIFWuGmBjMm6zBBodFU7jrObhKdWNhxvFzjxYRpChHiIoDSqV0nwfbMeG5YSkMrq ZrTflFc7FcXAw== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 11/15] net: ethernet: mtk_eth_soc: introduce device register map Date: Mon, 16 May 2022 18:06:38 +0200 Message-Id: <78e8c6ed230130b75aae77e6d05a9b35e298860a.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Introduce reg_map structure to add the capability to support different register definitions. This is a preliminary patch to introduce mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 17 +++ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 160 +++++++++++++------- 2 files changed, 121 insertions(+), 56 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 1e2fddc2bdcb..4dfd43023d80 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -34,6 +34,17 @@ MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); #define MTK_ETHTOOL_STAT(x) { #x, \ offsetof(struct mtk_hw_stats, x) / sizeof(u64) } +static const u32 mtk_reg_map[] = { + [MTK_PDMA_BASE] = 0x0800, + [MTK_PDMA_LRO_CTRL] = 0x0980, + [MTK_PDMA_ALT_SCORE_DELTA_BASE] = 0x0a4c, + [MTK_PDMA_LRO_RX_RING_DIP_BASE] = 0x0b04, + [MTK_PDMA_LRO_RX_RING_CTRL_BASE] = 0x0b28, + [MTK_QDMA_BASE] = 0x1800, + [MTK_GDM1_TX_STAT_BASE] = 0x2400, + [MTK_PDMA_RSS_GLO_BASE] = 0x3000, +}; + /* strings used by ethtool */ static const struct mtk_ethtool_stats { char str[ETH_GSTRING_LEN]; @@ -3376,6 +3387,7 @@ static int mtk_remove(struct platform_device *pdev) } static const struct mtk_soc_data mt2701_data = { + .reg_map = mtk_reg_map, .caps = MT7623_CAPS | MTK_HWLRO, .hw_features = MTK_HW_FEATURES, .required_clks = MT7623_CLKS_BITMAP, @@ -3387,6 +3399,7 @@ static const struct mtk_soc_data mt2701_data = { }; static const struct mtk_soc_data mt7621_data = { + .reg_map = mtk_reg_map, .caps = MT7621_CAPS, .hw_features = MTK_HW_FEATURES, .required_clks = MT7621_CLKS_BITMAP, @@ -3399,6 +3412,7 @@ static const struct mtk_soc_data mt7621_data = { }; static const struct mtk_soc_data mt7622_data = { + .reg_map = mtk_reg_map, .ana_rgc3 = 0x2028, .caps = MT7622_CAPS | MTK_HWLRO, .hw_features = MTK_HW_FEATURES, @@ -3412,6 +3426,7 @@ static const struct mtk_soc_data mt7622_data = { }; static const struct mtk_soc_data mt7623_data = { + .reg_map = mtk_reg_map, .caps = MT7623_CAPS | MTK_HWLRO, .hw_features = MTK_HW_FEATURES, .required_clks = MT7623_CLKS_BITMAP, @@ -3424,6 +3439,7 @@ static const struct mtk_soc_data mt7623_data = { }; static const struct mtk_soc_data mt7629_data = { + .reg_map = mtk_reg_map, .ana_rgc3 = 0x128, .caps = MT7629_CAPS | MTK_HWLRO, .hw_features = MTK_HW_FEATURES, @@ -3436,6 +3452,7 @@ static const struct mtk_soc_data mt7629_data = { }; static const struct mtk_soc_data rt5350_data = { + .reg_map = mtk_reg_map, .caps = MT7628_CAPS, .hw_features = MTK_HW_FEATURES_MT7628, .required_clks = MT7628_CLKS_BITMAP, diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 150d692633fa..2b98f0812655 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -19,6 +19,18 @@ #include #include "mtk_ppe.h" +enum mtk_reg_base { + MTK_PDMA_BASE, + MTK_PDMA_LRO_CTRL, + MTK_PDMA_ALT_SCORE_DELTA_BASE, + MTK_PDMA_LRO_RX_RING_DIP_BASE, + MTK_PDMA_LRO_RX_RING_CTRL_BASE, + MTK_PDMA_RSS_GLO_BASE, + MTK_GDM1_TX_STAT_BASE, + MTK_QDMA_BASE, + __MT_BASE_MAX, +}; + #define MTK_QDMA_PAGE_SIZE 2048 #define MTK_MAX_RX_LENGTH 1536 #define MTK_MAX_RX_LENGTH_2K 2048 @@ -100,43 +112,67 @@ #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) /* PDMA RX Base Pointer Register */ -#define MTK_PRX_BASE_PTR0 0x900 +#define MTK_PRX_BASE_PTR0 (eth->soc->reg_map[MTK_PDMA_BASE] + 0x100) #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) /* PDMA RX Maximum Count Register */ -#define MTK_PRX_MAX_CNT0 0x904 +#define MTK_PRX_MAX_CNT0 (MTK_PRX_BASE_PTR0 + 0x04) #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) /* PDMA RX CPU Pointer Register */ -#define MTK_PRX_CRX_IDX0 0x908 +#define MTK_PRX_CRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x08) #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) +/* PDMA RX DMA Pointer Register */ +#define MTK_PRX_DRX_IDX0 (MTK_PRX_BASE_PTR0 + 0x0c) +#define MTK_PRX_DRX_IDX_CFG(x) (MTK_PRX_DRX_IDX0 + (x * 0x10)) + /* PDMA HW LRO Control Registers */ -#define MTK_PDMA_LRO_CTRL_DW0 0x980 +#define MTK_PDMA_LRO_CTRL_DW0 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL]) #define MTK_LRO_EN BIT(0) #define MTK_L3_CKS_UPD_EN BIT(7) #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) -#define MTK_PDMA_LRO_CTRL_DW1 0x984 -#define MTK_PDMA_LRO_CTRL_DW2 0x988 -#define MTK_PDMA_LRO_CTRL_DW3 0x98c +#define MTK_PDMA_LRO_CTRL_DW1 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x04) +#define MTK_PDMA_LRO_CTRL_DW2 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x08) +#define MTK_PDMA_LRO_CTRL_DW3 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x0c) #define MTK_ADMA_MODE BIT(15) #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) +/* PDMA RSS Control Registers */ +#define MTK_RSS_EN BIT(0) +#define MTK_RSS_CFG_REQ BIT(2) +#define MTK_RSS_IPV6_STATIC_HASH (0x7 << 8) +#define MTK_RSS_IPV4_STATIC_HASH (0x7 << 12) +#define MTK_RSS_INDR_TABLE_DW0 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x50) +#define MTK_RSS_INDR_TABLE_DW1 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x54) +#define MTK_RSS_INDR_TABLE_DW2 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x58) +#define MTK_RSS_INDR_TABLE_DW3 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x5c) +#define MTK_RSS_INDR_TABLE_DW4 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x60) +#define MTK_RSS_INDR_TABLE_DW5 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x64) +#define MTK_RSS_INDR_TABLE_DW6 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x68) +#define MTK_RSS_INDR_TABLE_DW7 (eth->soc->reg_map[MTK_PDMA_RSS_GLO_BASE] + 0x6c) +#define MTK_RSS_INDR_TABLE_SIZE4 0x44444444 + /* PDMA Global Configuration Register */ -#define MTK_PDMA_GLO_CFG 0xa04 +#define MTK_PDMA_GLO_CFG (eth->soc->reg_map[MTK_PDMA_BASE] + 0x204) #define MTK_MULTI_EN BIT(10) #define MTK_PDMA_SIZE_8DWORDS (1 << 4) +/* PDMA Global Configuration Register */ +#define MTK_PDMA_RX_CFG (eth->soc->reg_map[MTK_PDMA_BASE] + 0x210) +#define MTK_PDMA_LRO_SDL 0x3000 +#define MTK_RX_CFG_SDL_OFFSET 16 + /* PDMA Reset Index Register */ -#define MTK_PDMA_RST_IDX 0xa08 +#define MTK_PDMA_RST_IDX (eth->soc->reg_map[MTK_PDMA_BASE] + 0x208) #define MTK_PST_DRX_IDX0 BIT(16) #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) /* PDMA Delay Interrupt Register */ -#define MTK_PDMA_DELAY_INT 0xa0c +#define MTK_PDMA_DELAY_INT (eth->soc->reg_map[MTK_PDMA_BASE] + 0x20c) #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) #define MTK_PDMA_DELAY_RX_EN BIT(15) #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 @@ -151,27 +187,34 @@ #define MTK_PDMA_DELAY_PTIME_MASK 0xff /* PDMA Interrupt Status Register */ -#define MTK_PDMA_INT_STATUS 0xa20 +#define MTK_PDMA_INT_STATUS (eth->soc->reg_map[MTK_PDMA_BASE] + 0x220) /* PDMA Interrupt Mask Register */ -#define MTK_PDMA_INT_MASK 0xa28 +#define MTK_PDMA_INT_MASK (eth->soc->reg_map[MTK_PDMA_BASE] + 0x228) /* PDMA HW LRO Alter Flow Delta Register */ -#define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c +#define MTK_PDMA_LRO_ALT_SCORE_DELTA (eth->soc->reg_map[MTK_PDMA_ALT_SCORE_DELTA_BASE]) /* PDMA Interrupt grouping registers */ -#define MTK_PDMA_INT_GRP1 0xa50 -#define MTK_PDMA_INT_GRP2 0xa54 +#define MTK_PDMA_INT_GRP1 (eth->soc->reg_map[MTK_PDMA_BASE] + 0x250) +#define MTK_PDMA_INT_GRP2 (eth->soc->reg_map[MTK_PDMA_BASE] + 0x254) /* PDMA HW LRO IP Setting Registers */ -#define MTK_LRO_RX_RING0_DIP_DW0 0xb04 +#define MTK_LRO_RX_RING0_DIP_DW0 (eth->soc->reg_map[MTK_PDMA_LRO_RX_RING_DIP_BASE]) #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) #define MTK_RING_MYIP_VLD BIT(9) +/* PDMA HW LRO ALT Debug Registers */ +#define MTK_LRO_ALT_DBG (eth->soc->reg_map[MTK_PDMA_BASE] + 0x440) +#define MTK_LRO_ALT_INDEX_OFFSET (8) + +/* PDMA HW LRO ALT Data Registers */ +#define MTK_LRO_ALT_DBG_DATA (eth->soc->reg_map[MTK_PDMA_BASE] + 0x444) + /* PDMA HW LRO Ring Control Registers */ -#define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 -#define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c -#define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 +#define MTK_LRO_RX_RING0_CTRL_DW1 (eth->soc->reg_map[MTK_PDMA_LRO_RX_RING_CTRL_BASE]) +#define MTK_LRO_RX_RING0_CTRL_DW2 (eth->soc->reg_map[MTK_PDMA_LRO_RX_RING_CTRL_BASE] + 0x4) +#define MTK_LRO_RX_RING0_CTRL_DW3 (eth->soc->reg_map[MTK_PDMA_LRO_RX_RING_CTRL_BASE] + 0x8) #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) @@ -184,26 +227,29 @@ #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) /* QDMA TX Queue Configuration Registers */ -#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) +#define MTK_QTX_CFG(x) (eth->soc->reg_map[MTK_QDMA_BASE] + ((x) * 0x10)) #define QDMA_RES_THRES 4 /* QDMA TX Queue Scheduler Registers */ -#define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) +#define MTK_QTX_SCH(x) (eth->soc->reg_map[MTK_QDMA_BASE] + 4 + ((x) * 0x10)) /* QDMA RX Base Pointer Register */ -#define MTK_QRX_BASE_PTR0 0x1900 +#define MTK_QRX_BASE_PTR0 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x100) +#define MTK_QRX_BASE_PTR_CFG(x) (MTK_QRX_BASE_PTR0 + ((x) * 0x10)) /* QDMA RX Maximum Count Register */ -#define MTK_QRX_MAX_CNT0 0x1904 +#define MTK_QRX_MAX_CNT0 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x104) +#define MTK_QRX_MAX_CNT_CFG(x) (MTK_QRX_MAX_CNT0 + ((x) * 0x10)) /* QDMA RX CPU Pointer Register */ -#define MTK_QRX_CRX_IDX0 0x1908 +#define MTK_QRX_CRX_IDX0 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x108) +#define MTK_QRX_CRX_IDX_CFG(x) (MTK_QRX_CRX_IDX0 + ((x) * 0x10)) /* QDMA RX DMA Pointer Register */ -#define MTK_QRX_DRX_IDX0 0x190C +#define MTK_QRX_DRX_IDX0 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x10c) /* QDMA Global Configuration Register */ -#define MTK_QDMA_GLO_CFG 0x1A04 +#define MTK_QDMA_GLO_CFG (eth->soc->reg_map[MTK_QDMA_BASE] + 0x204) #define MTK_RX_2B_OFFSET BIT(31) #define MTK_RX_BT_32DWORDS (3 << 11) #define MTK_NDP_CO_PRO BIT(10) @@ -216,19 +262,19 @@ #define MTK_DMA_BUSY_TIMEOUT_US 1000000 /* QDMA Reset Index Register */ -#define MTK_QDMA_RST_IDX 0x1A08 +#define MTK_QDMA_RST_IDX (eth->soc->reg_map[MTK_QDMA_BASE] + 0x208) /* QDMA Delay Interrupt Register */ -#define MTK_QDMA_DELAY_INT 0x1A0C +#define MTK_QDMA_DELAY_INT (eth->soc->reg_map[MTK_QDMA_BASE] + 0x20c) /* QDMA Flow Control Register */ -#define MTK_QDMA_FC_THRES 0x1A10 +#define MTK_QDMA_FC_THRES (eth->soc->reg_map[MTK_QDMA_BASE] + 0x210) #define FC_THRES_DROP_MODE BIT(20) #define FC_THRES_DROP_EN (7 << 16) #define FC_THRES_MIN 0x4444 /* QDMA Interrupt Status Register */ -#define MTK_QDMA_INT_STATUS 0x1A18 +#define MTK_QDMA_INT_STATUS (eth->soc->reg_map[MTK_QDMA_BASE] + 0x218) #define MTK_RX_DONE_DLY BIT(30) #define MTK_TX_DONE_DLY BIT(28) #define MTK_RX_DONE_INT3 BIT(19) @@ -243,55 +289,55 @@ #define MTK_TX_DONE_INT MTK_TX_DONE_DLY /* QDMA Interrupt grouping registers */ -#define MTK_QDMA_INT_GRP1 0x1a20 -#define MTK_QDMA_INT_GRP2 0x1a24 +#define MTK_QDMA_INT_GRP1 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x220) +#define MTK_QDMA_INT_GRP2 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x224) #define MTK_RLS_DONE_INT BIT(0) /* QDMA Interrupt Status Register */ -#define MTK_QDMA_INT_MASK 0x1A1C +#define MTK_QDMA_INT_MASK (eth->soc->reg_map[MTK_QDMA_BASE] + 0x21c) /* QDMA Interrupt Mask Register */ -#define MTK_QDMA_HRED2 0x1A44 +#define MTK_QDMA_HRED2 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x244) /* QDMA TX Forward CPU Pointer Register */ -#define MTK_QTX_CTX_PTR 0x1B00 +#define MTK_QTX_CTX_PTR (eth->soc->reg_map[MTK_QDMA_BASE] + 0x300) /* QDMA TX Forward DMA Pointer Register */ -#define MTK_QTX_DTX_PTR 0x1B04 +#define MTK_QTX_DTX_PTR (eth->soc->reg_map[MTK_QDMA_BASE] + 0x304) /* QDMA TX Release CPU Pointer Register */ -#define MTK_QTX_CRX_PTR 0x1B10 +#define MTK_QTX_CRX_PTR (eth->soc->reg_map[MTK_QDMA_BASE] + 0x310) /* QDMA TX Release DMA Pointer Register */ -#define MTK_QTX_DRX_PTR 0x1B14 +#define MTK_QTX_DRX_PTR (eth->soc->reg_map[MTK_QDMA_BASE] + 0x314) /* QDMA FQ Head Pointer Register */ -#define MTK_QDMA_FQ_HEAD 0x1B20 +#define MTK_QDMA_FQ_HEAD (eth->soc->reg_map[MTK_QDMA_BASE] + 0x320) /* QDMA FQ Head Pointer Register */ -#define MTK_QDMA_FQ_TAIL 0x1B24 +#define MTK_QDMA_FQ_TAIL (eth->soc->reg_map[MTK_QDMA_BASE] + 0x324) /* QDMA FQ Free Page Counter Register */ -#define MTK_QDMA_FQ_CNT 0x1B28 +#define MTK_QDMA_FQ_CNT (eth->soc->reg_map[MTK_QDMA_BASE] + 0x328) /* QDMA FQ Free Page Buffer Length Register */ -#define MTK_QDMA_FQ_BLEN 0x1B2C +#define MTK_QDMA_FQ_BLEN (eth->soc->reg_map[MTK_QDMA_BASE] + 0x32c) /* GMA1 counter / statics register */ -#define MTK_GDM1_RX_GBCNT_L 0x2400 -#define MTK_GDM1_RX_GBCNT_H 0x2404 -#define MTK_GDM1_RX_GPCNT 0x2408 -#define MTK_GDM1_RX_OERCNT 0x2410 -#define MTK_GDM1_RX_FERCNT 0x2414 -#define MTK_GDM1_RX_SERCNT 0x2418 -#define MTK_GDM1_RX_LENCNT 0x241c -#define MTK_GDM1_RX_CERCNT 0x2420 -#define MTK_GDM1_RX_FCCNT 0x2424 -#define MTK_GDM1_TX_SKIPCNT 0x2428 -#define MTK_GDM1_TX_COLCNT 0x242c -#define MTK_GDM1_TX_GBCNT_L 0x2430 -#define MTK_GDM1_TX_GBCNT_H 0x2434 -#define MTK_GDM1_TX_GPCNT 0x2438 +#define MTK_GDM1_RX_GBCNT_L (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE]) +#define MTK_GDM1_RX_GBCNT_H (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x4) +#define MTK_GDM1_RX_GPCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x8) +#define MTK_GDM1_RX_OERCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x10) +#define MTK_GDM1_RX_FERCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x14) +#define MTK_GDM1_RX_SERCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x18) +#define MTK_GDM1_RX_LENCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x1c) +#define MTK_GDM1_RX_CERCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x20) +#define MTK_GDM1_RX_FCCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x24) +#define MTK_GDM1_TX_SKIPCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x28) +#define MTK_GDM1_TX_COLCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x2c) +#define MTK_GDM1_TX_GBCNT_L (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x30) +#define MTK_GDM1_TX_GBCNT_H (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x34) +#define MTK_GDM1_TX_GPCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x38) #define MTK_STAT_OFFSET 0x40 #define MTK_WDMA0_BASE 0x2800 @@ -857,6 +903,7 @@ struct mtk_tx_dma_desc_info { /* struct mtk_eth_data - This is the structure holding all differences * among various plaforms + * @reg_map: Device register map * @ana_rgc3: The offset for register ANA_RGC3 related to * sgmiisys syscon * @caps Flags shown the extra capability for the SoC @@ -869,6 +916,7 @@ struct mtk_tx_dma_desc_info { * @rxd_size RX DMA descriptor size. */ struct mtk_soc_data { + const u32 *reg_map; u32 ana_rgc3; u32 caps; u32 required_clks; From patchwork Mon May 16 16:06:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851042 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F78AC433EF for ; Mon, 16 May 2022 16:08:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245666AbiEPQIp (ORCPT ); Mon, 16 May 2022 12:08:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245660AbiEPQIh (ORCPT ); Mon, 16 May 2022 12:08:37 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5764387A0; Mon, 16 May 2022 09:08:21 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 4210FB81262; Mon, 16 May 2022 16:08:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DBA39C385AA; Mon, 16 May 2022 16:08:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717298; bh=bqRrGEoslTKGIdX7RJMT09747G7fzI1Rh0bOJoh3Q94=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MyoAfymV59aKkCKNMxWb91/2uG5v/nBOuBGQaHvxNnMADxvW8Gvxt5PI4HSliYqnr jPX6zoUBCHwjDrheI6M8uMsQOsHgKIGV57lVgBNE64OoK20jeTMw3w35m8Wkc84I4h p1Ut6A18lcbqvt7poYRPowHN9Zg89O1cDn4+XBrkLSE2/q2TQ/M2gzMYZOlegSAmoV Nockx1yiwKfWtZ3A4Ts5mAxM2vm6qGiH/989RDV+lfeMLqR/DqZVsSW4p02o4CWIm4 j3wRlVHv3PEWA62pN+ElzUvO19ajU35lzzyw46ldY7AK5mnkZGSIqtyBpvcEIfa2oK Ou5sI4+RCFZaA== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 12/15] net: ethernet: mtk_eth_soc: introduce MTK_NETSYS_V2 support Date: Mon, 16 May 2022 18:06:39 +0200 Message-Id: X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Introduce MTK_NETSYS_V2 support. MTK_NETSYS_V2 defines 32B TX/RX DMA descriptors. This is a preliminary patch to add mt7986 ethernet support. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 312 ++++++++++++++++---- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 129 +++++++- 2 files changed, 366 insertions(+), 75 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 4dfd43023d80..50ffdcb8d35a 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -778,8 +778,8 @@ static inline int mtk_max_buf_size(int frag_size) return buf_size; } -static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd, - struct mtk_rx_dma *dma_rxd) +static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, + struct mtk_rx_dma_v2 *dma_rxd) { rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); if (!(rxd->rxd2 & RX_DMA_DONE)) @@ -788,6 +788,10 @@ static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd, rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); + rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); + } return true; } @@ -821,7 +825,7 @@ static int mtk_init_fq_dma(struct mtk_eth *eth) phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); for (i = 0; i < cnt; i++) { - struct mtk_tx_dma *txd; + struct mtk_tx_dma_v2 *txd; txd = (void *)eth->scratch_ring + i * soc->txrx.txd_size; txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; @@ -831,6 +835,12 @@ static int mtk_init_fq_dma(struct mtk_eth *eth) txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); txd->txd4 = 0; + if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { + txd->txd5 = 0; + txd->txd6 = 0; + txd->txd7 = 0; + txd->txd8 = 0; + } } mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); @@ -934,10 +944,12 @@ static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, } } -static void mtk_tx_set_dma_desc(struct net_device *dev, struct mtk_tx_dma *desc, - struct mtk_tx_dma_desc_info *info) +static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, + struct mtk_tx_dma_desc_info *info) { struct mtk_mac *mac = netdev_priv(dev); + struct mtk_eth *eth = mac->hw; + struct mtk_tx_dma *desc = txd; u32 data; WRITE_ONCE(desc->txd1, info->addr); @@ -961,6 +973,59 @@ static void mtk_tx_set_dma_desc(struct net_device *dev, struct mtk_tx_dma *desc, WRITE_ONCE(desc->txd4, data); } +static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, + struct mtk_tx_dma_desc_info *info) +{ + struct mtk_mac *mac = netdev_priv(dev); + struct mtk_tx_dma_v2 *desc = txd; + struct mtk_eth *eth = mac->hw; + u32 data; + + WRITE_ONCE(desc->txd1, info->addr); + + data = TX_DMA_PLEN0(info->size); + if (info->last) + data |= TX_DMA_LS0; + WRITE_ONCE(desc->txd3, data); + + if (!info->qid && mac->id) + info->qid = MTK_QDMA_GMAC2_QID; + + data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ + data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); + WRITE_ONCE(desc->txd4, data); + + data = 0; + if (info->first) { + if (info->gso) + data |= TX_DMA_TSO_V2; + /* tx checksum offload */ + if (info->csum) + data |= TX_DMA_CHKSUM_V2; + } + WRITE_ONCE(desc->txd5, data); + + data = 0; + if (info->first && info->vlan) + data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; + WRITE_ONCE(desc->txd6, data); + + WRITE_ONCE(desc->txd7, 0); + WRITE_ONCE(desc->txd8, 0); +} + +static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, + struct mtk_tx_dma_desc_info *info) +{ + struct mtk_mac *mac = netdev_priv(dev); + struct mtk_eth *eth = mac->hw; + + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + mtk_tx_set_dma_desc_v2(dev, txd, info); + else + mtk_tx_set_dma_desc_v1(dev, txd, info); +} + static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, int tx_num, struct mtk_tx_ring *ring, bool gso) { @@ -969,6 +1034,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, .gso = gso, .csum = skb->ip_summed == CHECKSUM_PARTIAL, .vlan = skb_vlan_tag_present(skb), + .qid = skb->mark & MTK_QDMA_TX_MASK, .vlan_tci = skb_vlan_tag_get(skb), .first = true, .last = !skb_is_nonlinear(skb), @@ -1028,7 +1094,9 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, } memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); - txd_info.size = min(frag_size, MTK_TX_DMA_BUF_LEN); + txd_info.size = min_t(unsigned int, frag_size, + soc->txrx.dma_max_len); + txd_info.qid = skb->mark & MTK_QDMA_TX_MASK; txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && !(frag_size - txd_info.size); txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, @@ -1109,17 +1177,16 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, return -ENOMEM; } -static inline int mtk_cal_txd_req(struct sk_buff *skb) +static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) { - int i, nfrags; + int i, nfrags = 1; skb_frag_t *frag; - nfrags = 1; if (skb_is_gso(skb)) { for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { frag = &skb_shinfo(skb)->frags[i]; nfrags += DIV_ROUND_UP(skb_frag_size(frag), - MTK_TX_DMA_BUF_LEN); + eth->soc->txrx.dma_max_len); } } else { nfrags += skb_shinfo(skb)->nr_frags; @@ -1171,7 +1238,7 @@ static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) if (unlikely(test_bit(MTK_RESETTING, ð->state))) goto drop; - tx_num = mtk_cal_txd_req(skb); + tx_num = mtk_cal_txd_req(eth, skb); if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { netif_stop_queue(dev); netif_err(eth, tx_queued, dev, @@ -1263,7 +1330,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, int idx; struct sk_buff *skb; u8 *data, *new_data; - struct mtk_rx_dma *rxd, trxd; + struct mtk_rx_dma_v2 *rxd, trxd; int done = 0, bytes = 0; while (done < budget) { @@ -1271,7 +1338,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, unsigned int pktlen; dma_addr_t dma_addr; u32 hash, reason; - int mac; + int mac = 0; ring = mtk_get_rx_ring(eth); if (unlikely(!ring)) @@ -1281,16 +1348,15 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size; data = ring->data[idx]; - if (!mtk_rx_get_desc(&trxd, rxd)) + if (!mtk_rx_get_desc(eth, &trxd, rxd)) break; /* find out which mac the packet come from. values start at 1 */ - if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) || - (trxd.rxd4 & RX_DMA_SPECIAL_TAG)) - mac = 0; - else - mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & - RX_DMA_FPORT_MASK) - 1; + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; + else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && + !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) + mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || !eth->netdev[mac])) @@ -1333,7 +1399,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); skb->dev = netdev; skb_put(skb, pktlen); - if (trxd.rxd4 & eth->rx_dma_l4_valid) + if (trxd.rxd4 & eth->soc->txrx.rx_dma_l4_valid) skb->ip_summed = CHECKSUM_UNNECESSARY; else skb_checksum_none_assert(skb); @@ -1351,10 +1417,25 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, mtk_ppe_check_skb(eth->ppe, skb, trxd.rxd4 & MTK_RXD4_FOE_ENTRY); - if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && - (trxd.rxd2 & RX_DMA_VTAG)) - __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), - RX_DMA_VID(trxd.rxd3)); + if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (trxd.rxd3 & RX_DMA_VTAG_V2) + __vlan_hwaccel_put_tag(skb, + htons(RX_DMA_VPID(trxd.rxd4)), + RX_DMA_VID(trxd.rxd4)); + } else if (trxd.rxd2 & RX_DMA_VTAG) { + __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), + RX_DMA_VID(trxd.rxd3)); + } + + /* If the device is attached to a dsa switch, the special + * tag inserted in VLAN field by hw switch can * be offloaded + * by RX HW VLAN offload. Clear vlan info. + */ + if (netdev_uses_dsa(netdev)) + __vlan_hwaccel_clear_tag(skb); + } + skb_record_rx_queue(skb, 0); napi_gro_receive(napi, skb); @@ -1366,7 +1447,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) rxd->rxd2 = RX_DMA_LSO; else - rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); + rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); ring->calc_idx = idx; @@ -1565,7 +1646,8 @@ static int mtk_napi_rx(struct napi_struct *napi, int budget) do { int rx_done; - mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); + mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, + MTK_PDMA_INT_STATUS); rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); rx_done_total += rx_done; @@ -1579,10 +1661,11 @@ static int mtk_napi_rx(struct napi_struct *napi, int budget) if (rx_done_total == budget) return budget; - } while (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT); + } while (mtk_r32(eth, MTK_PDMA_INT_STATUS) & + eth->soc->txrx.rx_irq_done_mask); if (napi_complete_done(napi, rx_done_total)) - mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); + mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); return rx_done_total; } @@ -1591,7 +1674,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) { const struct mtk_soc_data *soc = eth->soc; struct mtk_tx_ring *ring = ð->tx_ring; - struct mtk_tx_dma *txd; + struct mtk_tx_dma_v2 *txd; int i; ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), @@ -1613,13 +1696,19 @@ static int mtk_tx_alloc(struct mtk_eth *eth) txd->txd2 = next_ptr; txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; txd->txd4 = 0; + if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { + txd->txd5 = 0; + txd->txd6 = 0; + txd->txd7 = 0; + txd->txd8 = 0; + } } /* On MT7688 (PDMA only) this driver uses the ring->dma structs * only as the framework. The real HW descriptors are the PDMA * descriptors in ring->dma_pdma. */ - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { + if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * soc->txrx.txd_size, &ring->phys_pdma, GFP_ATOMIC); @@ -1700,13 +1789,11 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) struct mtk_rx_ring *ring; int rx_data_len, rx_dma_size; int i; - u32 offset = 0; if (rx_flag == MTK_RX_FLAGS_QDMA) { if (ring_no) return -EINVAL; ring = ð->rx_ring_qdma; - offset = 0x1000; } else { ring = ð->rx_ring[ring_no]; } @@ -1739,7 +1826,7 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) return -ENOMEM; for (i = 0; i < rx_dma_size; i++) { - struct mtk_rx_dma *rxd; + struct mtk_rx_dma_v2 *rxd; dma_addr_t dma_addr = dma_map_single(eth->dma_dev, ring->data[i] + NET_SKB_PAD + eth->ip_align, @@ -1754,24 +1841,39 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) rxd->rxd2 = RX_DMA_LSO; else - rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); + rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); rxd->rxd3 = 0; rxd->rxd4 = 0; + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + rxd->rxd5 = 0; + rxd->rxd6 = 0; + rxd->rxd7 = 0; + rxd->rxd8 = 0; + } } ring->dma_size = rx_dma_size; ring->calc_idx_update = false; ring->calc_idx = rx_dma_size - 1; - ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); + if (rx_flag == MTK_RX_FLAGS_QDMA) + ring->crx_idx_reg = MTK_QRX_CRX_IDX_CFG(ring_no); + else + ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); /* make sure that all changes to the dma ring are flushed before we * continue */ wmb(); - mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); - mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); - mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); - mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); + if (rx_flag == MTK_RX_FLAGS_QDMA) { + mtk_w32(eth, ring->phys, MTK_QRX_BASE_PTR_CFG(ring_no)); + mtk_w32(eth, rx_dma_size, MTK_QRX_MAX_CNT_CFG(ring_no)); + mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_QDMA_RST_IDX); + } else { + mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no)); + mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no)); + mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX); + } + mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); return 0; } @@ -2190,7 +2292,7 @@ static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) eth->rx_events++; if (likely(napi_schedule_prep(ð->rx_napi))) { __napi_schedule(ð->rx_napi); - mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); + mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); } return IRQ_HANDLED; @@ -2213,8 +2315,10 @@ static irqreturn_t mtk_handle_irq(int irq, void *_eth) { struct mtk_eth *eth = _eth; - if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { - if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) + if (mtk_r32(eth, MTK_PDMA_INT_MASK) & + eth->soc->txrx.rx_irq_done_mask) { + if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & + eth->soc->txrx.rx_irq_done_mask) mtk_handle_irq_rx(irq, _eth); } if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) { @@ -2232,16 +2336,16 @@ static void mtk_poll_controller(struct net_device *dev) struct mtk_eth *eth = mac->hw; mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); - mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); + mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); mtk_handle_irq_rx(eth->irq[2], dev); mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); - mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); + mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); } #endif static int mtk_start_dma(struct mtk_eth *eth) { - u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; + u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; int err; err = mtk_dma_init(eth); @@ -2251,12 +2355,18 @@ static int mtk_start_dma(struct mtk_eth *eth) } if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { - mtk_w32(eth, - MTK_TX_WB_DDONE | MTK_TX_DMA_EN | - MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | - MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | - MTK_RX_BT_32DWORDS, - MTK_QDMA_GLO_CFG); + val = mtk_r32(eth, MTK_QDMA_GLO_CFG); + val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | + MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | + MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; + + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + val |= MTK_MUTLI_CNT | MTK_RESV_BUF | + MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | + MTK_CHK_DDONE_EN; + else + val |= MTK_RX_BT_32DWORDS; + mtk_w32(eth, val, MTK_QDMA_GLO_CFG); mtk_w32(eth, MTK_RX_DMA_EN | rx_2b_offset | @@ -2328,7 +2438,7 @@ static int mtk_open(struct net_device *dev) napi_enable(ð->tx_napi); napi_enable(ð->rx_napi); mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); - mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); + mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); refcount_set(ð->dma_refcnt, 1); } else @@ -2380,7 +2490,7 @@ static int mtk_stop(struct net_device *dev) mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); - mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); + mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); napi_disable(ð->tx_napi); napi_disable(ð->rx_napi); @@ -2517,7 +2627,7 @@ static int mtk_hw_init(struct mtk_eth *eth) if (eth->ethsys) regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, - of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); + of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { ret = device_reset(eth->dev); @@ -2537,9 +2647,25 @@ static int mtk_hw_init(struct mtk_eth *eth) return 0; } - /* Non-MT7628 handling... */ - ethsys_reset(eth, RSTCTRL_FE); - ethsys_reset(eth, RSTCTRL_PPE); + val = RSTCTRL_FE | RSTCTRL_PPE; + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); + + val |= RSTCTRL_ETH; + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) + val |= RSTCTRL_PPE1; + } + + ethsys_reset(eth, val); + + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, + 0x3ffffff); + + /* Set FE to PDMAv2 if necessary */ + val = mtk_r32(eth, MTK_FE_GLO_MISC); + mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); + } if (eth->pctl) { /* Set GE2 driving and slew rate */ @@ -2578,11 +2704,47 @@ static int mtk_hw_init(struct mtk_eth *eth) /* FE int grouping */ mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); - mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); + mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, MTK_PDMA_INT_GRP2); mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); - mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); + mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, MTK_QDMA_INT_GRP2); mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + /* PSE should not drop port8 and port9 packets */ + mtk_w32(eth, 0x00000300, PSE_DROP_CFG); + + /* PSE Free Queue Flow Control */ + mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); + + /* PSE config input queue threshold */ + mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); + mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); + mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); + mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); + mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); + mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); + mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); + mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); + + /* PSE config output queue threshold */ + mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); + mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); + mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); + mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); + mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); + mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); + mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); + mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); + + /* GDM and CDM Threshold */ + mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); + mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); + mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); + mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); + mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); + mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); + } + return 0; err_disable_pm: @@ -3154,12 +3316,8 @@ static int mtk_probe(struct platform_device *pdev) eth->tx_int_status_reg = MTK_PDMA_INT_STATUS; } - if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { - eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA; + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) eth->ip_align = NET_IP_ALIGN; - } else { - eth->rx_dma_l4_valid = RX_DMA_L4_VALID; - } spin_lock_init(ð->page_lock); spin_lock_init(ð->tx_irq_lock); @@ -3395,6 +3553,10 @@ static const struct mtk_soc_data mt2701_data = { .txrx = { .txd_size = sizeof(struct mtk_tx_dma), .rxd_size = sizeof(struct mtk_rx_dma), + .rx_irq_done_mask = MTK_RX_DONE_INT, + .rx_dma_l4_valid = RX_DMA_L4_VALID, + .dma_max_len = MTK_TX_DMA_BUF_LEN, + .dma_len_offset = 16, }, }; @@ -3408,6 +3570,10 @@ static const struct mtk_soc_data mt7621_data = { .txrx = { .txd_size = sizeof(struct mtk_tx_dma), .rxd_size = sizeof(struct mtk_rx_dma), + .rx_irq_done_mask = MTK_RX_DONE_INT, + .rx_dma_l4_valid = RX_DMA_L4_VALID, + .dma_max_len = MTK_TX_DMA_BUF_LEN, + .dma_len_offset = 16, }, }; @@ -3422,6 +3588,10 @@ static const struct mtk_soc_data mt7622_data = { .txrx = { .txd_size = sizeof(struct mtk_tx_dma), .rxd_size = sizeof(struct mtk_rx_dma), + .rx_irq_done_mask = MTK_RX_DONE_INT, + .rx_dma_l4_valid = RX_DMA_L4_VALID, + .dma_max_len = MTK_TX_DMA_BUF_LEN, + .dma_len_offset = 16, }, }; @@ -3435,6 +3605,10 @@ static const struct mtk_soc_data mt7623_data = { .txrx = { .txd_size = sizeof(struct mtk_tx_dma), .rxd_size = sizeof(struct mtk_rx_dma), + .rx_irq_done_mask = MTK_RX_DONE_INT, + .rx_dma_l4_valid = RX_DMA_L4_VALID, + .dma_max_len = MTK_TX_DMA_BUF_LEN, + .dma_len_offset = 16, }, }; @@ -3448,6 +3622,10 @@ static const struct mtk_soc_data mt7629_data = { .txrx = { .txd_size = sizeof(struct mtk_tx_dma), .rxd_size = sizeof(struct mtk_rx_dma), + .rx_irq_done_mask = MTK_RX_DONE_INT, + .rx_dma_l4_valid = RX_DMA_L4_VALID, + .dma_max_len = MTK_TX_DMA_BUF_LEN, + .dma_len_offset = 16, }, }; @@ -3460,6 +3638,10 @@ static const struct mtk_soc_data rt5350_data = { .txrx = { .txd_size = sizeof(struct mtk_tx_dma), .rxd_size = sizeof(struct mtk_rx_dma), + .rx_irq_done_mask = MTK_RX_DONE_INT, + .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, + .dma_max_len = MTK_TX_DMA_BUF_LEN, + .dma_len_offset = 16, }, }; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 2b98f0812655..654ad3b00154 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -35,6 +35,7 @@ enum mtk_reg_base { #define MTK_MAX_RX_LENGTH 1536 #define MTK_MAX_RX_LENGTH_2K 2048 #define MTK_TX_DMA_BUF_LEN 0x3fff +#define MTK_TX_DMA_BUF_LEN_V2 0xffff #define MTK_DMA_SIZE 512 #define MTK_MAC_COUNT 2 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) @@ -92,6 +93,10 @@ enum mtk_reg_base { #define MTK_CDMQ_IG_CTRL 0x1400 #define MTK_CDMQ_STAG_EN BIT(0) +/* CDMP Ingress Control Register */ +#define MTK_CDMP_IG_CTRL 0x400 +#define MTK_CDMP_STAG_EN BIT(0) + /* CDMP Exgress Control Register */ #define MTK_CDMP_EG_CTRL 0x404 @@ -111,6 +116,28 @@ enum mtk_reg_base { /* Unicast Filter MAC Address Register - High */ #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) +/* FE global misc reg*/ +#define MTK_FE_GLO_MISC 0x124 + +/* PSE Free Queue Flow Control */ +#define PSE_FQFC_CFG1 0x100 +#define PSE_FQFC_CFG2 0x104 +#define PSE_DROP_CFG 0x108 + +/* PSE Input Queue Reservation Register*/ +#define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) + +/* PSE Output Queue Threshold Register*/ +#define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) + +/* GDM and CDM Threshold */ +#define MTK_GDM2_THRES 0x1530 +#define MTK_CDMW0_THRES 0x164c +#define MTK_CDMW1_THRES 0x1650 +#define MTK_CDME0_THRES 0x1654 +#define MTK_CDME1_THRES 0x1658 +#define MTK_CDMM_THRES 0x165c + /* PDMA RX Base Pointer Register */ #define MTK_PRX_BASE_PTR0 (eth->soc->reg_map[MTK_PDMA_BASE] + 0x100) #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) @@ -131,9 +158,12 @@ enum mtk_reg_base { #define MTK_PDMA_LRO_CTRL_DW0 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL]) #define MTK_LRO_EN BIT(0) #define MTK_L3_CKS_UPD_EN BIT(7) +#define MTK_L3_CKS_UPD_EN_V2 BIT(19) #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) +#define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) +#define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) #define MTK_PDMA_LRO_CTRL_DW1 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x04) #define MTK_PDMA_LRO_CTRL_DW2 (eth->soc->reg_map[MTK_PDMA_LRO_CTRL] + 0x08) @@ -158,6 +188,7 @@ enum mtk_reg_base { /* PDMA Global Configuration Register */ #define MTK_PDMA_GLO_CFG (eth->soc->reg_map[MTK_PDMA_BASE] + 0x204) +#define MTK_RX_DMA_LRO_EN BIT(8) #define MTK_MULTI_EN BIT(10) #define MTK_PDMA_SIZE_8DWORDS (1 << 4) @@ -261,6 +292,13 @@ enum mtk_reg_base { #define MTK_TX_DMA_EN BIT(0) #define MTK_DMA_BUSY_TIMEOUT_US 1000000 +/* QDMA V2 Global Configuration Register */ +#define MTK_CHK_DDONE_EN BIT(28) +#define MTK_DMAD_WR_WDONE BIT(26) +#define MTK_WCOMP_EN BIT(24) +#define MTK_RESV_BUF (0x40 << 16) +#define MTK_MUTLI_CNT (0x4 << 12) + /* QDMA Reset Index Register */ #define MTK_QDMA_RST_IDX (eth->soc->reg_map[MTK_QDMA_BASE] + 0x208) @@ -288,6 +326,8 @@ enum mtk_reg_base { #define MTK_RX_DONE_INT MTK_RX_DONE_DLY #define MTK_TX_DONE_INT MTK_TX_DONE_DLY +#define MTK_RX_DONE_INT_V2 BIT(14) + /* QDMA Interrupt grouping registers */ #define MTK_QDMA_INT_GRP1 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x220) #define MTK_QDMA_INT_GRP2 (eth->soc->reg_map[MTK_QDMA_BASE] + 0x224) @@ -340,6 +380,25 @@ enum mtk_reg_base { #define MTK_GDM1_TX_GPCNT (eth->soc->reg_map[MTK_GDM1_TX_STAT_BASE] + 0x38) #define MTK_STAT_OFFSET 0x40 +/* QDMA TX NUM */ +#define MTK_QDMA_TX_NUM 16 +#define MTK_QDMA_TX_MASK (MTK_QDMA_TX_NUM - 1) +#define QID_BITS_V2(x) (((x) & 0x3f) << 16) +#define MTK_QDMA_GMAC2_QID 8 + +#define MTK_TX_DMA_BUF_SHIFT 8 + +/* QDMA V2 descriptor txd6 */ +#define TX_DMA_INS_VLAN_V2 BIT(16) +/* QDMA V2 descriptor txd5 */ +#define TX_DMA_CHKSUM_V2 (0x7 << 28) +#define TX_DMA_TSO_V2 BIT(31) + +/* QDMA V2 descriptor txd4 */ +#define TX_DMA_FPORT_SHIFT_V2 8 +#define TX_DMA_FPORT_MASK_V2 0xf +#define TX_DMA_SWC_V2 BIT(30) + #define MTK_WDMA0_BASE 0x2800 #define MTK_WDMA1_BASE 0x2c00 @@ -353,10 +412,9 @@ enum mtk_reg_base { /* QDMA descriptor txd3 */ #define TX_DMA_OWNER_CPU BIT(31) #define TX_DMA_LS0 BIT(30) -#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) -#define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN) +#define TX_DMA_PLEN0(_x) (((_x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) +#define TX_DMA_PLEN1(_x) ((_x) & eth->soc->txrx.dma_max_len) #define TX_DMA_SWC BIT(14) -#define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) /* PDMA on MT7628 */ #define TX_DMA_DONE BIT(31) @@ -366,12 +424,14 @@ enum mtk_reg_base { /* QDMA descriptor rxd2 */ #define RX_DMA_DONE BIT(31) #define RX_DMA_LSO BIT(30) -#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) -#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) +#define RX_DMA_PREP_PLEN0(_x) (((_x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) +#define RX_DMA_GET_PLEN0(_x) (((_x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) #define RX_DMA_VTAG BIT(15) /* QDMA descriptor rxd3 */ -#define RX_DMA_VID(_x) ((_x) & 0xfff) +#define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) +#define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) +#define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) /* QDMA descriptor rxd4 */ #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) @@ -382,10 +442,15 @@ enum mtk_reg_base { /* QDMA descriptor rxd4 */ #define RX_DMA_L4_VALID BIT(24) #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ -#define RX_DMA_FPORT_SHIFT 19 -#define RX_DMA_FPORT_MASK 0x7 #define RX_DMA_SPECIAL_TAG BIT(22) +#define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0xf) +#define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0x7) + +/* PDMA V2 descriptor rxd3 */ +#define RX_DMA_VTAG_V2 BIT(0) +#define RX_DMA_L4_VALID_V2 BIT(2) + /* PHY Indirect Access Control registers */ #define MTK_PHY_IAC 0x10004 #define PHY_IAC_ACCESS BIT(31) @@ -508,6 +573,16 @@ enum mtk_reg_base { #define ETHSYS_TRGMII_MT7621_APLL BIT(6) #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) +/* ethernet reset control register */ +#define ETHSYS_RSTCTRL 0x34 +#define RSTCTRL_FE BIT(6) +#define RSTCTRL_PPE BIT(31) +#define RSTCTRL_PPE1 BIT(30) +#define RSTCTRL_ETH BIT(23) + +/* ethernet reset check idle register */ +#define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 + /* ethernet reset control register */ #define ETHSYS_RSTCTRL 0x34 #define RSTCTRL_FE BIT(6) @@ -592,6 +667,17 @@ struct mtk_rx_dma { unsigned int rxd4; } __packed __aligned(4); +struct mtk_rx_dma_v2 { + unsigned int rxd1; + unsigned int rxd2; + unsigned int rxd3; + unsigned int rxd4; + unsigned int rxd5; + unsigned int rxd6; + unsigned int rxd7; + unsigned int rxd8; +} __packed __aligned(4); + struct mtk_tx_dma { unsigned int txd1; unsigned int txd2; @@ -599,6 +685,17 @@ struct mtk_tx_dma { unsigned int txd4; } __packed __aligned(4); +struct mtk_tx_dma_v2 { + unsigned int txd1; + unsigned int txd2; + unsigned int txd3; + unsigned int txd4; + unsigned int txd5; + unsigned int txd6; + unsigned int txd7; + unsigned int txd8; +} __packed __aligned(4); + struct mtk_eth; struct mtk_mac; @@ -785,7 +882,9 @@ enum mkt_eth_capabilities { MTK_SHARED_INT_BIT, MTK_TRGMII_MT7621_CLK_BIT, MTK_QDMA_BIT, + MTK_NETSYS_V2_BIT, MTK_SOC_MT7628_BIT, + MTK_RSTCTRL_PPE1_BIT, /* MUX BITS*/ MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, @@ -817,7 +916,9 @@ enum mkt_eth_capabilities { #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) #define MTK_QDMA BIT(MTK_QDMA_BIT) +#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) +#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) @@ -894,6 +995,7 @@ struct mtk_tx_dma_desc_info { dma_addr_t addr; u32 size; u16 vlan_tci; + u16 qid; u8 gso:1; u8 csum:1; u8 vlan:1; @@ -913,7 +1015,11 @@ struct mtk_tx_dma_desc_info { * @required_pctl A bool value to show whether the SoC requires * the extra setup for those pins used by GMAC. * @txd_size TX DMA descriptor size. - * @rxd_size RX DMA descriptor size. + * @rxd_size Rx DMA descriptor size. + * @rx_irq_done_mask Rx irq done register mask. + * @rx_dma_l4_valid Rx DMA valid register mask. + * @dma_max_len Max DMA tx/rx buffer length. + * @dma_len_offset Tx/Rx DMA length field offset. */ struct mtk_soc_data { const u32 *reg_map; @@ -926,6 +1032,10 @@ struct mtk_soc_data { struct { u32 txd_size; u32 rxd_size; + u32 rx_irq_done_mask; + u32 rx_dma_l4_valid; + u32 dma_max_len; + u32 dma_len_offset; } txrx; }; @@ -1046,7 +1156,6 @@ struct mtk_eth { u32 tx_int_mask_reg; u32 tx_int_status_reg; - u32 rx_dma_l4_valid; int ip_align; struct mtk_ppe *ppe; From patchwork Mon May 16 16:06:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851041 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1346DC4321E for ; Mon, 16 May 2022 16:08:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241556AbiEPQIr (ORCPT ); Mon, 16 May 2022 12:08:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245672AbiEPQIi (ORCPT ); Mon, 16 May 2022 12:08:38 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B3693819C; Mon, 16 May 2022 09:08:24 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5A46DB81261; Mon, 16 May 2022 16:08:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 579EAC34115; Mon, 16 May 2022 16:08:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717302; bh=g+8ZHx5azfc9wFAICouyVaIiKamwB274z8h8s7EKO50=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n+bT1o961RfEthuRGTK+eC1Vxkq7IDhths0YeT9ujxeKaCKEBSFwtrYiS670ZQOmm Op77K6qCb4MWCahtuv8zCfQFoXZANS8318gHlVu4kf7IFpn9/OIBhUmSz1sugTF2bw vlHERXGn6eKmAnaqStvX0Q3ObytcJe49oAUguRVFQLjk1G9u7ducTfxV0bbQQY93PD UfIYOqbpVgaMR9Bg4t4rq3Df8M0a+WS90d1Es9L6rmijfe8AM1A43c1vHoMb/rPJNj dPwBmS+c/2G4mj8E683OFAVQKb6lX6vIsqi3iE5nzWS7CEWvdudIqCgnk+0cHZb4ae qGH937UWTMuPg== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 13/15] net: ethernet: mtk_eth_soc: convert ring dma pointer to void Date: Mon, 16 May 2022 18:06:40 +0200 Message-Id: X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Simplify the code converting {tx,rx} ring dma pointer to void Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 32 +++++++++------------ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 +-- 2 files changed, 16 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 50ffdcb8d35a..4190172ba902 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -851,18 +851,15 @@ static int mtk_init_fq_dma(struct mtk_eth *eth) return 0; } -static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) +static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) { - void *ret = ring->dma; - - return ret + (desc - ring->phys); + return ring->dma + (desc - ring->phys); } static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, - struct mtk_tx_dma *txd, - u32 txd_size) + void *txd, u32 txd_size) { - int idx = ((void *)txd - (void *)ring->dma) / txd_size; + int idx = (txd - ring->dma) / txd_size; return &ring->buf[idx]; } @@ -870,13 +867,12 @@ static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma) { - return ring->dma_pdma - ring->dma + dma; + return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; } -static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma, - u32 txd_size) +static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) { - return ((void *)dma - (void *)ring->dma) / txd_size; + return (dma - ring->dma) / txd_size; } static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, @@ -1293,7 +1289,7 @@ static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) ring = ð->rx_ring[i]; idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); - rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size; + rxd = ring->dma + idx * eth->soc->txrx.rxd_size; if (rxd->rxd2 & RX_DMA_DONE) { ring->calc_idx_update = true; return ring; @@ -1345,7 +1341,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, goto rx_done; idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); - rxd = (void *)ring->dma + idx * eth->soc->txrx.rxd_size; + rxd = ring->dma + idx * eth->soc->txrx.rxd_size; data = ring->data[idx]; if (!mtk_rx_get_desc(eth, &trxd, rxd)) @@ -1548,7 +1544,7 @@ static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, mtk_tx_unmap(eth, tx_buf, true); - desc = (void *)ring->dma + cpu * eth->soc->txrx.txd_size; + desc = ring->dma + cpu * eth->soc->txrx.txd_size; ring->last_free = desc; atomic_inc(&ring->free_count); @@ -1692,7 +1688,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) int next = (i + 1) % MTK_DMA_SIZE; u32 next_ptr = ring->phys + next * soc->txrx.txd_size; - txd = (void *)ring->dma + i * soc->txrx.txd_size; + txd = ring->dma + i * soc->txrx.txd_size; txd->txd2 = next_ptr; txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; txd->txd4 = 0; @@ -1723,7 +1719,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) ring->dma_size = MTK_DMA_SIZE; atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); - ring->next_free = &ring->dma[0]; + ring->next_free = ring->dma; ring->last_free = (void *)txd; ring->last_free_ptr = (u32)(ring->phys + (MTK_DMA_SIZE - 1) * soc->txrx.txd_size); @@ -1835,7 +1831,7 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) return -ENOMEM; - rxd = (void *)ring->dma + i * eth->soc->txrx.rxd_size; + rxd = ring->dma + i * eth->soc->txrx.rxd_size; rxd->rxd1 = (unsigned int)dma_addr; if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) @@ -1889,7 +1885,7 @@ static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) if (!ring->data[i]) continue; - rxd = (void *)ring->dma + i * eth->soc->txrx.rxd_size; + rxd = ring->dma + i * eth->soc->txrx.rxd_size; if (!rxd->rxd1) continue; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 654ad3b00154..57501dd5adcc 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -828,7 +828,7 @@ struct mtk_tx_buf { * are present */ struct mtk_tx_ring { - struct mtk_tx_dma *dma; + void *dma; struct mtk_tx_buf *buf; dma_addr_t phys; struct mtk_tx_dma *next_free; @@ -858,7 +858,7 @@ enum mtk_rx_flags { * @calc_idx: The current head of ring */ struct mtk_rx_ring { - struct mtk_rx_dma *dma; + void *dma; u8 **data; dma_addr_t phys; u16 frag_size; From patchwork Mon May 16 16:06:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851043 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FC8CC433F5 for ; Mon, 16 May 2022 16:08:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245664AbiEPQIr (ORCPT ); Mon, 16 May 2022 12:08:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245722AbiEPQIj (ORCPT ); Mon, 16 May 2022 12:08:39 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 967E638BCF; Mon, 16 May 2022 09:08:26 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0F42660FEB; Mon, 16 May 2022 16:08:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9CA66C3411D; Mon, 16 May 2022 16:08:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717305; bh=5zNfSJuhI4dXzdSVVXLUoVyHOoDat1Fm5kjHvHG5PMc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ks7uA+fl+FeuvZlHYmnKmrD776FtLfDc+fAM+Ost1IyAlSABNxHfoofa3zKXT9LQ5 tHjloy/FGGR4BeMt0T4515mBuSQwpmxT3F7rWwBNp+WfhZVYVKlzQAP7TJP6fDNM5Z 4h+6E5kYT3Kr3THRyexKYMRE44MNzk1J3iVYP2K26K1sJJ6veofoYJ/voG7/us68un 2n9KM1rxzab8S002CdwjYGHo4Mgk2PG/u19zBZNHQoJguN7KYXVBNSa1SaHHicnMnx QBUYqqE7iUpZ8Fyg755PJJ/Q3InORUrYAO3Jmb9CtR56FseZNCaMZQF31ynzS+/17y TGKctzsfIW6wQ== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 14/15] net: ethernet: mtk_eth_soc: convert scratch_ring pointer to void Date: Mon, 16 May 2022 18:06:41 +0200 Message-Id: <235146c3d8620deef0d831cbca76452776ca6a04.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Simplify the code converting scratch_ring pointer to void Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 4190172ba902..373d9733e66f 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -827,7 +827,7 @@ static int mtk_init_fq_dma(struct mtk_eth *eth) for (i = 0; i < cnt; i++) { struct mtk_tx_dma_v2 *txd; - txd = (void *)eth->scratch_ring + i * soc->txrx.txd_size; + txd = eth->scratch_ring + i * soc->txrx.txd_size; txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; if (i < cnt - 1) txd->txd2 = eth->phy_scratch_ring + diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 57501dd5adcc..d955af42ad93 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -1131,7 +1131,7 @@ struct mtk_eth { struct mtk_rx_ring rx_ring_qdma; struct napi_struct tx_napi; struct napi_struct rx_napi; - struct mtk_tx_dma *scratch_ring; + void *scratch_ring; dma_addr_t phy_scratch_ring; void *scratch_head; struct clk *clks[MTK_CLK_MAX]; From patchwork Mon May 16 16:06:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 12851044 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45DC0C433FE for ; Mon, 16 May 2022 16:08:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245719AbiEPQIw (ORCPT ); Mon, 16 May 2022 12:08:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245726AbiEPQIj (ORCPT ); Mon, 16 May 2022 12:08:39 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0798F38795; Mon, 16 May 2022 09:08:29 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 569B460FC9; Mon, 16 May 2022 16:08:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E46D9C385AA; Mon, 16 May 2022 16:08:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652717308; bh=uM3ccAJWdxDoSZRLhAr0NaFqOgPx8bqnk2xxzO/IuVI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oO4zdUWmjDwrudVQk++1yhWHpuI30+WM5WktqlkYfCcNzj6W4Oe7NHz0BdvW0fj3G jJn551vhucEYa8Mb1+qKJdXOZRDWLF00DFr12zsxVmLF/21LeCQu2lkODd2NCR6U1m pCKtSLJ6twW+Mh+wftLj2j4+dkG5OgDtDIOOQax59mamKsLkiIZ6XbKpDXcg17tPap 5oeW295IHSZztTsRxmwT/ELdvhbY0l6+iVlcnhJf4iIBzeI0PBi6gwk9kkJmxGFuqe 7YPSOx3uWQmFoyHq+Se1l6JXTElwjfRH2Fg6+s4ONwqWhPenAl0CwgygP6kLcMqLCk Rhm338CZyo8SA== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Sam.Shih@mediatek.com, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, lorenzo.bianconi@redhat.com Subject: [PATCH v2 net-next 15/15] net: ethernet: mtk_eth_soc: introduce support for mt7986 chipset Date: Mon, 16 May 2022 18:06:42 +0200 Message-Id: <5b8e9a0256bd1da216ff508d70bd5a8b9f3113f1.1652716741.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add support for mt7986-eth driver available on mt7986 soc. Tested-by: Sam Shih Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 29 ++++++++++++++++++++- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 18 +++++++++++++ 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 373d9733e66f..ce3c242f14fa 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -45,6 +45,17 @@ static const u32 mtk_reg_map[] = { [MTK_PDMA_RSS_GLO_BASE] = 0x3000, }; +static const u32 mt7986_reg_map[] = { + [MTK_PDMA_BASE] = 0x6000, + [MTK_PDMA_LRO_CTRL] = 0x6408, + [MTK_PDMA_ALT_SCORE_DELTA_BASE] = 0x641c, + [MTK_PDMA_LRO_RX_RING_DIP_BASE] = 0x6414, + [MTK_PDMA_LRO_RX_RING_CTRL_BASE] = 0x6438, + [MTK_QDMA_BASE] = 0x4400, + [MTK_GDM1_TX_STAT_BASE] = 0x1c00, + [MTK_PDMA_RSS_GLO_BASE] = 0x6800, +}; + /* strings used by ethtool */ static const struct mtk_ethtool_stats { char str[ETH_GSTRING_LEN]; @@ -68,7 +79,7 @@ static const char * const mtk_clks_source_name[] = { "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "sgmii_ck", "eth2pll", + "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" }; void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) @@ -3625,6 +3636,21 @@ static const struct mtk_soc_data mt7629_data = { }, }; +static const struct mtk_soc_data mt7986_data = { + .reg_map = mt7986_reg_map, + .ana_rgc3 = 0x128, + .caps = MT7986_CAPS, + .required_clks = MT7986_CLKS_BITMAP, + .required_pctl = false, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), + .rx_irq_done_mask = MTK_RX_DONE_INT_V2, + .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, + .dma_len_offset = 8, + }, +}; + static const struct mtk_soc_data rt5350_data = { .reg_map = mtk_reg_map, .caps = MT7628_CAPS, @@ -3647,6 +3673,7 @@ const struct of_device_id of_mtk_match[] = { { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, + { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, {}, }; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index d955af42ad93..1972bc18af0c 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -763,6 +763,10 @@ enum mtk_clks_map { MTK_CLK_SGMII2_CDR_FB, MTK_CLK_SGMII_CK, MTK_CLK_ETH2PLL, + MTK_CLK_WOCPU0, + MTK_CLK_WOCPU1, + MTK_CLK_NETSYS0, + MTK_CLK_NETSYS1, MTK_CLK_MAX }; @@ -793,6 +797,16 @@ enum mtk_clks_map { BIT(MTK_CLK_SGMII2_CDR_FB) | \ BIT(MTK_CLK_SGMII_CK) | \ BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) +#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ + BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ + BIT(MTK_CLK_SGMII_TX_250M) | \ + BIT(MTK_CLK_SGMII_RX_250M) | \ + BIT(MTK_CLK_SGMII_CDR_REF) | \ + BIT(MTK_CLK_SGMII_CDR_FB) | \ + BIT(MTK_CLK_SGMII2_TX_250M) | \ + BIT(MTK_CLK_SGMII2_RX_250M) | \ + BIT(MTK_CLK_SGMII2_CDR_REF) | \ + BIT(MTK_CLK_SGMII2_CDR_FB)) enum mtk_dev_state { MTK_HW_INIT, @@ -991,6 +1005,10 @@ enum mkt_eth_capabilities { MTK_MUX_U3_GMAC2_TO_QPHY | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) +#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ + MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) + struct mtk_tx_dma_desc_info { dma_addr_t addr; u32 size;