From patchwork Tue May 17 12:50:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D300C43217 for ; Tue, 17 May 2022 12:51:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346455AbiEQMvv (ORCPT ); Tue, 17 May 2022 08:51:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346427AbiEQMvr (ORCPT ); Tue, 17 May 2022 08:51:47 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B84D340A12; Tue, 17 May 2022 05:51:40 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id B7985BB3; Tue, 17 May 2022 15:52:33 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru B7985BB3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791953; bh=byo7LdWAOntp9CHllRKOliNs4EMYYCQa53BtH26Ghrw=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=rJ2lXTr4YB4apAAZuUuBZtaghhWL+Uw5NEz82MDjGYCIuU88xbd6PwHVGbej2QT50 x9LIw/pedOkU4kVe9dasa0w2fnK41yU8ZtrAQYHmAmK17js75O5qgiLJg92Zc9xLk5 B/4WX0aVFn8ou9tIORRyalDwcWAHymDnqp/+7crg= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:36 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 01/13] PCI: dwc: Stop link in the host init error and de-initialization Date: Tue, 17 May 2022 15:50:46 +0300 Message-ID: <20220517125058.18488-2-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org It's logically correct to undo everything what was done in case of an error is discovered or in the corresponding cleanup counterpart. Otherwise the host controller will be left in an undetermined state. Seeing the link is set up in the Host-initialization method it will be right to de-activate it there in the cleanup-on-error block and stop the link in the antagonistic routine - dw_pcie_host_deinit(). The link de-activation is a platform-specific thing and is supposed to be implemented in the framework of the dw_pcie_ops.stop_link() operation. Fixes: 886a9c134755 ("PCI: dwc: Move link handling into common code") Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../pci/controller/dwc/pcie-designware-host.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 2fa86f32d964..7403b1709726 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -420,8 +420,14 @@ int dw_pcie_host_init(struct pcie_port *pp) bridge->sysdata = pp; ret = pci_host_probe(bridge); - if (!ret) - return 0; + if (ret) + goto err_stop_link; + + return 0; + +err_stop_link: + if (pci->ops && pci->ops->stop_link) + pci->ops->stop_link(pci); err_free_msi: if (pp->has_msi_ctrl) @@ -432,8 +438,14 @@ EXPORT_SYMBOL_GPL(dw_pcie_host_init); void dw_pcie_host_deinit(struct pcie_port *pp) { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + pci_stop_root_bus(pp->bridge->bus); pci_remove_root_bus(pp->bridge->bus); + + if (pci->ops && pci->ops->stop_link) + pci->ops->stop_link(pci); + if (pp->has_msi_ctrl) dw_pcie_free_msi(pp); } From patchwork Tue May 17 12:50:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852396 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D91CFC433FE for ; Tue, 17 May 2022 12:51:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346451AbiEQMvu (ORCPT ); Tue, 17 May 2022 08:51:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245694AbiEQMvr (ORCPT ); Tue, 17 May 2022 08:51:47 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 100F121814; Tue, 17 May 2022 05:51:39 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id ACB59BB4; Tue, 17 May 2022 15:52:34 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru ACB59BB4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791954; bh=83qWmKr71o9pT+7jAoONXJ9hQkpgLzXh+CyfIGI7J+c=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=koMZrwuZeN3KdU/nMUv0yoV4pQkkLu0RrZ9XWEXmgQEc2QQVWNVi1gDw8WnP1MSBa rm4Piw/a9MP0Q+fnu9IFAd+1wyVxTg3AmpvIBiEVIYCPxhCoOhyWWDXVBlZ3zy4aI9 GAicLf5jAGsofHFVFPwNPO6Y2U3lhQELHOs07rRE= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:37 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 02/13] PCI: dwc: Don't use generic IO-ops for DBI-space access Date: Tue, 17 May 2022 15:50:47 +0300 Message-ID: <20220517125058.18488-3-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Commit c2b0c098fbd1 ("PCI: dwc: Use generic config accessors") replaced the locally defined DW PCIe host controller config-space accessors with the generic methods pci_generic_config_read() and pci_generic_config_write(). It was intended that the corresponding bus-mapping callback returned a correct virtual address of the passed PCI config-space register. The problem of the proposed solution was that it didn't take into account the way the host config-space is accessed on the DW PCIe. Depending on the DW PCIe IP-core synthesize parameters different interfaces can be used to access the host and peripheral config/memory spaces. The former one can be accessed via the DBI interface, while the later ones is reached via the AHB/AXI application bus. In case if the DW PCIe controller is configured to have a dedicated DBI interface, the way it is mapped into the IO-memory turns to be platform-specific. For such setups the DWC PCIe driver provides a set of the callbacks dw_pcie_ops.{read_dbi,write_dbi} so the platforms glue-drivers would be able to take into account the DBI bus IO peculiarities. Since commit c2b0c098fbd1 ("PCI: dwc: Use generic config accessors") these methods haven't been utilized during the generic host initialization performed by the PCIe subsystem code. I don't really know how come there have been no problems spotted for the Histb/Exynos/Kirin PCIe controllers so far, but in our case with dword aligned IO requirement the generic config-space accessors can't be utilized for the host config-space. Thus in order to make sure the host config-space is properly accessed via the DBI bus let's get back the dw_pcie_rd_own_conf() and dw_pcie_wr_own_conf() methods. They are going to be just wrappers around the already defined dw_pcie_read_dbi()/dw_pcie_write_dbi() functions with proper arguments conversion. These methods perform the platform-specific config-space IO if the DBI accessors are specified, otherwise they call normal MMIO operations. Fixes: c2b0c098fbd1 ("PCI: dwc: Use generic config accessors") Signed-off-by: Serge Semin Tested-by: Manivannan Sadhasivam --- .../pci/controller/dwc/pcie-designware-host.c | 34 +++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 7403b1709726..a250869334a5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -534,10 +534,40 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, } EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); +static int dw_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + struct pcie_port *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + if (PCI_SLOT(devfn) > 0) { + *val = ~0U; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + *val = dw_pcie_read_dbi(pci, where, size); + + return PCIBIOS_SUCCESSFUL; +} + +static int dw_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + struct pcie_port *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + if (PCI_SLOT(devfn) > 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + dw_pcie_write_dbi(pci, where, size, val); + + return PCIBIOS_SUCCESSFUL; +} + static struct pci_ops dw_pcie_ops = { .map_bus = dw_pcie_own_conf_map_bus, - .read = pci_generic_config_read, - .write = pci_generic_config_write, + .read = dw_pcie_rd_own_conf, + .write = dw_pcie_wr_own_conf, }; void dw_pcie_setup_rc(struct pcie_port *pp) From patchwork Tue May 17 12:50:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7A4CC433F5 for ; Tue, 17 May 2022 12:51:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346459AbiEQMvv (ORCPT ); Tue, 17 May 2022 08:51:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346417AbiEQMvr (ORCPT ); Tue, 17 May 2022 08:51:47 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 48CF23F889; Tue, 17 May 2022 05:51:39 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id B184EBD4; Tue, 17 May 2022 15:52:35 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru B184EBD4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791955; bh=HvFRjLfRZVpB1a2dJ+Y3tW+LbZlq0RtxiS2ht743LVQ=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=GZINoVA2cAE0s74DZOslmcgg+RVjJqa0Yu+dH52V7n5FiZ88SUN2JtUEUhAD00Oht b2KQdUEQqH/1hTaA282qN7kIWiZ/BAPSY1vPa46TKMVBpkrxHKgae52gikT9uVwfFt yPRxGka2qPU2fq31JQQvnVVJKNZEASyEeDWkHEPo= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:38 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 03/13] PCI: dwc: Add unroll iATU space support to the regions disable method Date: Tue, 17 May 2022 15:50:48 +0300 Message-ID: <20220517125058.18488-4-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The dw_pcie_disable_atu() method was introduced in the commit f8aed6ec624f ("PCI: dwc: designware: Add EP mode support"). Since then it hasn't changed at all. For all that time the method has supported the viewport version of the iATU CSRs only. Basically it works for the DW PCIe IP-cores older than v4.80a since the newer controllers are equipped with the unrolled iATU/eDMA space. It means the methods using it like pci_epc_ops.clear_bar and pci_epc_ops.unmap_addr callbacks just don't work correctly for the DW PCIe controllers with unrolled iATU CSRs. The same concerns the dw_pcie_setup_rc() method, which disables the outbound iATU entries before re-initializing them. So in order to fix the problems denoted above let's convert the dw_pcie_disable_atu() method to disabling the iATU inbound and outbound regions in the unrolled iATU CSRs in case the DW PCIe controller has been synthesized with the ones support. The former semantics will be remained for the controller having iATU mapped over the viewport. Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- Changelog v3: - Convert region variable type to u32 in order to fix the implicit type conversion peculiarity. (@kbot) --- drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index d92c8a25094f..84fef21efdbc 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -491,7 +491,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, void dw_pcie_disable_atu(struct dw_pcie *pci, int index, enum dw_pcie_region_type type) { - int region; + u32 region; switch (type) { case DW_PCIE_REGION_INBOUND: @@ -504,8 +504,18 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index, return; } - dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); - dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE); + if (pci->iatu_unroll_enabled) { + if (region == PCIE_ATU_REGION_INBOUND) { + dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, + ~(u32)PCIE_ATU_ENABLE); + } else { + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, + ~(u32)PCIE_ATU_ENABLE); + } + } else { + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); + dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE); + } } int dw_pcie_wait_for_link(struct dw_pcie *pci) From patchwork Tue May 17 12:50:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F4CFC433F5 for ; Tue, 17 May 2022 12:51:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346434AbiEQMvs (ORCPT ); Tue, 17 May 2022 08:51:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346419AbiEQMvr (ORCPT ); Tue, 17 May 2022 08:51:47 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E7C7541310; Tue, 17 May 2022 05:51:40 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id B71EEBD5; Tue, 17 May 2022 15:52:36 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru B71EEBD5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791956; bh=X91Eb7i1pO+lRymwUnCcZj2+zZX4JThyCF/DCQW4gW0=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=IX4B2HB3Ib6XpiNwfQ+1Q62K21PUWcQTzYU2yNSOGc3NCVj4B8iDwm8vIVlMaa0Zc 5TY/jGrB/Lre6WS9SfRSsNOCBu/1VU393CeatwAbk2CKEGJxB63p5t1Fljb5c5ni+A HyzNMR6E7KEhFQwLnTfC6x7oqHDluPlEnjn1ONb8= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:39 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 04/13] PCI: dwc: Disable outbound windows for controllers with iATU Date: Tue, 17 May 2022 15:50:49 +0300 Message-ID: <20220517125058.18488-5-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In accordance with the dw_pcie_setup_rc() method semantics and judging by what the comment added in commit dd193929d91e ("PCI: designware: Explain why we don't program ATU for some platforms") states there are DWC PCIe-available platforms like Keystone (pci-keystone.c) or Amazon's Annapurna Labs (pcie-al.c) which don't have the DW PCIe internal ATU enabled and use it's own address translation approach implemented. In these cases at the very least there is no point in touching the DW PCIe iATU CSRs. Moreover depending on the vendor-specific address translation implementation it might be even erroneous. So let's move the iATU windows disabling procedure to being under the corresponding conditional statement clause thus performing that procedure only if the iATU is expected to be available on the platform. Fixes: 458ad06c4cdd ("PCI: dwc: Ensure all outbound ATU windows are reset") Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index a250869334a5..4e5c89c19f78 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -572,7 +572,6 @@ static struct pci_ops dw_pcie_ops = { void dw_pcie_setup_rc(struct pcie_port *pp) { - int i; u32 val, ctrl, num_ctrls; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -623,19 +622,22 @@ void dw_pcie_setup_rc(struct pcie_port *pp) PCI_COMMAND_MASTER | PCI_COMMAND_SERR; dw_pcie_writel_dbi(pci, PCI_COMMAND, val); - /* Ensure all outbound windows are disabled so there are multiple matches */ - for (i = 0; i < pci->num_ob_windows; i++) - dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND); - /* * If the platform provides its own child bus config accesses, it means * the platform uses its own address translation component rather than * ATU, so we should not program the ATU here. */ if (pp->bridge->child_ops == &dw_child_pcie_ops) { - int atu_idx = 0; + int i, atu_idx = 0; struct resource_entry *entry; + /* + * Ensure all outbound windows are disabled so there are + * multiple matches + */ + for (i = 0; i < pci->num_ob_windows; i++) + dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND); + /* Get last memory resource entry */ resource_list_for_each_entry(entry, &pp->bridge->windows) { if (resource_type(entry->res) != IORESOURCE_MEM) From patchwork Tue May 17 12:50:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 127A0C433F5 for ; Tue, 17 May 2022 12:52:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346502AbiEQMwB (ORCPT ); Tue, 17 May 2022 08:52:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346465AbiEQMvw (ORCPT ); Tue, 17 May 2022 08:51:52 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B581E21834; Tue, 17 May 2022 05:51:45 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id CEBC0BD6; Tue, 17 May 2022 15:52:37 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru CEBC0BD6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791958; bh=EOVES41k44a8aiGRCiFSCyFxTqVIh9wxi/EixTfGm+s=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=SmPmlx6qGvUsWFLTvFBJfzFDejvEAoC2dRctHcun3JnmN8GZfZUZMK2/izUdj2hrk oFapl8BzqIDgJqsAQT6TIDMaEIMLm/ebchAE9yf0kj5UYWnTK19VNf84pQWNQf+Y0R P2HfyudqP/iaiDo/3EThO/9FdP8Ir7USEovvT1EY= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:40 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Pankaj Dubey , Shradha Todi CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 05/13] PCI: dwc: Set INCREASE_REGION_SIZE flag based on limit address Date: Tue, 17 May 2022 15:50:50 +0300 Message-ID: <20220517125058.18488-6-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org It was wrong to use the region size parameter in order to determine whether the INCREASE_REGION_SIZE flag needs to be set for the outbound iATU entry because in general there are cases when combining a region base address and size together produces the out of bounds upper range limit while upper_32_bits(size) still returns zero. So having a region size within the permitted values doesn't mean the region limit address will fit to the corresponding CSR. Here is the way iATU calculates the in- and outbound untranslated regions if the INCREASE_REGION_SIZE flag is cleared [1]: Start address: End address: 63 31 0 63 31 0 +---------------+---------------+ +---------------+---------------+ | | | 0s | | | | Fs | +---------------+---------------+ +---------------+---------------+ upper base | lower base !upper! base | limit address address address address So the region start address is determined by the iATU lower and upper base address registers, while the region upper boundary is calculated based on the 32-bits limit address register and the upper part of the base address. In accordance with that logic for instance the range 0xf0000000 @ 0x20000000 does have the size smaller than 4GB, but the actual limit address turns to be invalid forming the untranslated address map as [0xf0000000; 0x1000FFFF], which isn't what the original range was. In order to fix that we need to check whether the size after being added to the lower part of the base address causes the 4GB range overflow. If it does then we need to set the INCREASE_REGION_SIZE flag thus activating the extended limit address by means of an additional iATU CSR (upper limit address register) [2]: Start address: End address: 63 31 0 63 x 31 0 +---------------+---------------+ +---------------+---------------+ | | | 0s | | | | | Fs | +---------------+---------------+ +---------------+---------------+ upper base | lower base upper | upper | limit address address address base | limit | address|address| Otherwise there is enough room in the 32-bits wide limit address register, and the flag can be left unset. Note the case when the size-based flag setting approach is correct implies requiring to have the size-aligned base addresses only. But that constraint isn't relevant to the PCIe ranges accepted by the kernel. There is also no point in implementing it either seeing the problem can be easily fixed by checking the whole limit address instead of the region size. [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, v5.40a, March 2019, fig.3-36, p.175 [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, v5.40a, March 2019, fig.3-37, p.176 Fixes: 5b4cf0f65324 ("PCI: dwc: Add upper limit address for outbound iATU") Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- Changelog v2: - Fix the end address in the example of the patch log. It should be 0x1000FFFF and not 0x0000FFFF (@Manivannan). --- drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 84fef21efdbc..347251bf87d0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -287,8 +287,8 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no, dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, upper_32_bits(pci_addr)); val = type | PCIE_ATU_FUNC_NUM(func_no); - val = upper_32_bits(size - 1) ? - val | PCIE_ATU_INCREASE_REGION_SIZE : val; + if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr)) + val |= PCIE_ATU_INCREASE_REGION_SIZE; if (pci->version == 0x490A) val = dw_pcie_enable_ecrc(val); dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val); @@ -315,6 +315,7 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, u64 pci_addr, u64 size) { u32 retries, val; + u64 limit_addr; if (pci->ops && pci->ops->cpu_addr_fixup) cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); @@ -325,6 +326,8 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, return; } + limit_addr = cpu_addr + size - 1; + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | index); dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE, @@ -332,17 +335,18 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE, upper_32_bits(cpu_addr)); dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT, - lower_32_bits(cpu_addr + size - 1)); + lower_32_bits(limit_addr)); if (pci->version >= 0x460A) dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT, - upper_32_bits(cpu_addr + size - 1)); + upper_32_bits(limit_addr)); dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(pci_addr)); dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(pci_addr)); val = type | PCIE_ATU_FUNC_NUM(func_no); - val = ((upper_32_bits(size - 1)) && (pci->version >= 0x460A)) ? - val | PCIE_ATU_INCREASE_REGION_SIZE : val; + if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && + pci->version >= 0x460A) + val |= PCIE_ATU_INCREASE_REGION_SIZE; if (pci->version == 0x490A) val = dw_pcie_enable_ecrc(val); dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val); From patchwork Tue May 17 12:50:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852398 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6D0FC4321E for ; Tue, 17 May 2022 12:51:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343506AbiEQMvw (ORCPT ); Tue, 17 May 2022 08:51:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346440AbiEQMvv (ORCPT ); Tue, 17 May 2022 08:51:51 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9D6682C662; Tue, 17 May 2022 05:51:45 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id E878BBD7; Tue, 17 May 2022 15:52:38 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru E878BBD7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791958; bh=tpvLBnqOsvw+Y9Lu79MzBU/091077M9EeMSrXis1gw0=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=lagX7xf7vcSXEeBdOj+Fn2hOfqi583SbYNCVU435nGXvIkRa9WC1bxqddqloOlxZx cTYnOiCdxbg6GvXK2CTx8cA+T9SW24NMnuVYTiMq+ZaFAK3o9TgdWip2JBdXyTYu8p u7FrdpIxpndpbd9bAlPXIiBS+7TUd6pwywrgbbIA= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:41 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 06/13] PCI: dwc: Add braces to the multi-line if-else statements Date: Tue, 17 May 2022 15:50:51 +0300 Message-ID: <20220517125058.18488-7-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In accordance with [1] if there is at least one multi-line if-else clause in the statement, then each clause will need to be surrounded by the braces. The driver code violates that coding style rule in a few places. Let's fix it. [1] Documentation/process/coding-style.rst Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 4 ++-- drivers/pci/controller/dwc/pcie-designware.c | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 0eda8236c125..7c9315fffe24 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -699,9 +699,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (!pci->dbi_base2) { res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); - if (!res) + if (!res) { pci->dbi_base2 = pci->dbi_base + SZ_4K; - else { + } else { pci->dbi_base2 = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pci->dbi_base2)) return PTR_ERR(pci->dbi_base2); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 347251bf87d0..ef995e006cf0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -699,8 +699,9 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) pci->atu_size = SZ_4K; dw_pcie_iatu_detect_regions_unroll(pci); - } else + } else { dw_pcie_iatu_detect_regions(pci); + } dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? "enabled" : "disabled"); From patchwork Tue May 17 12:50:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852399 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37A32C43219 for ; Tue, 17 May 2022 12:51:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346463AbiEQMvw (ORCPT ); Tue, 17 May 2022 08:51:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346457AbiEQMvv (ORCPT ); Tue, 17 May 2022 08:51:51 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C2BF13FD89; Tue, 17 May 2022 05:51:45 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 37424BD8; Tue, 17 May 2022 15:52:40 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 37424BD8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791960; bh=j0eQpM4tEI5c0/99FoG5IzT1I/D94sTFv5xoRji7Djg=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=Yt/Mt/3b8GBVviehGvvjctYPCbPB7adIueqGv+GU3/AagfgKDifpEG1fStjz64kN2 klqxTGU3Xgv4e75BLCkpO+MSlxDAbrKvkFYQUkC3JuV5zzii0p5zFzXb96/cjfBfpC WH7ZSy1zG1IXiNk5lmBEeTytedTU+Y1iysv/hiCE= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:43 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 07/13] PCI: dwc: Add trailing new-line literals to the log messages Date: Tue, 17 May 2022 15:50:52 +0300 Message-ID: <20220517125058.18488-8-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org There are two places in the DW PCIe controller driver, which omit the trailing newlines in the log info and warn messages. Not having them there will cause leaving the messages in the printk ring buffer until a next '\n'-terminated message is printed (it will consequently cause the buffer flush). As it isn't what the corresponding code implies let's add the new-line characters in the messages. Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 +- drivers/pci/controller/dwc/pcie-designware.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 4e5c89c19f78..1c815d3bead9 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -662,7 +662,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) } if (pci->num_ob_windows <= atu_idx) - dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)", + dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)\n", pci->num_ob_windows); } diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index ef995e006cf0..62382eda5533 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -706,7 +706,7 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? "enabled" : "disabled"); - dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound", + dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound\n", pci->num_ob_windows, pci->num_ib_windows); } From patchwork Tue May 17 12:50:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852402 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1ABD2C433EF for ; Tue, 17 May 2022 12:51:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346495AbiEQMvz (ORCPT ); Tue, 17 May 2022 08:51:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346464AbiEQMvw (ORCPT ); Tue, 17 May 2022 08:51:52 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9D7DD3A72C; Tue, 17 May 2022 05:51:45 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 3FF74BD9; Tue, 17 May 2022 15:52:41 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 3FF74BD9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791961; bh=MBFfEYWBn9NnwWI6fHyW8yfe6AKk/ZfnrvWbq2mNjbE=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=CajE4rL1xH31fJIgayx2K2Ar1MzU/xvx0llhqeNCl4mkZSgesvo7RGwC5Q5/hdfHE 1icQBuBUlRqRiBB2HTNAY5azXxl3p3nv4wFmZiEtxbAio4nL5oOyDfqMl7qOauRWJ/ j0ZFIVTujoyunj6JXFC1gbt8Yxn3H2VUi0sR9qTs= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:44 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 08/13] PCI: dwc: Discard IP-core version checking on unrolled iATU detection Date: Tue, 17 May 2022 15:50:53 +0300 Message-ID: <20220517125058.18488-9-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org It's pretty much pointless. Even though unrolled version of the internal ATU has been indeed available since DWC PCIe v4.80a IP-core, there is no guarantee it was enabled during the IP-core configuration (Synopsys suggests to contact the Solvnet support for guidance of how to do that for the newer IP-cores). So the only reliable way to find out the unrolled iATU feature availability is indeed to check the iATU viewport register content. In accordance with the reference manual [1] if the register doesn't exist (unrolled iATU is enabled) it's content is fixed with 0xff-s, otherwise it will contain some zeros. So we can freely drop the IP-core version checking in this matter then and use the dw_pcie_iatu_unroll_enabled() method only to detect whether iATU/eDMA space is unrolled. [1] DesignWare Cores, PCI Express Controller, Register Desciptions, v.4.90a, December 2016, p.855 Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 62382eda5533..f4d9184258c4 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -600,15 +600,15 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) } -static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) +static bool dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) { u32 val; val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); if (val == 0xffffffff) - return 1; + return true; - return 0; + return false; } static void dw_pcie_iatu_detect_regions_unroll(struct dw_pcie *pci) @@ -680,9 +680,8 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) struct device *dev = pci->dev; struct platform_device *pdev = to_platform_device(dev); - if (pci->version >= 0x480A || (!pci->version && - dw_pcie_iatu_unroll_enabled(pci))) { - pci->iatu_unroll_enabled = true; + pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); + if (pci->iatu_unroll_enabled) { if (!pci->atu_base) { struct resource *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); From patchwork Tue May 17 12:50:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852406 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AADEC433FE for ; Tue, 17 May 2022 12:52:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346507AbiEQMwD (ORCPT ); Tue, 17 May 2022 08:52:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346467AbiEQMvw (ORCPT ); Tue, 17 May 2022 08:51:52 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A83C33F889; Tue, 17 May 2022 05:51:46 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 4DA93BDA; Tue, 17 May 2022 15:52:42 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 4DA93BDA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791962; bh=QJGvEdv+cPwRZepqgKrf1uDoBkpFTaUqJhcoUL9aBho=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=NeRlCf1fJ6MRYDhlHR4dS4MoNwpX3BvpDPG61+vDkoBFiPBeTzeVi6iJfG112wCjD +0tW8UP4jtdUE7zCx6QQGFUbYYOWNtT5cRLRX2eCAmHrL7DNnW78gPkSkpJH1b5U9w Hrav2zwlOzyXYrqYm9EExpD0WxU2JwJAWQTx7GeI= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:45 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 09/13] PCI: dwc: Convert Link-up status method to using dw_pcie_readl_dbi() Date: Tue, 17 May 2022 15:50:54 +0300 Message-ID: <20220517125058.18488-10-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org While the rest of the generic DWC PCIe code is using the dedicated IO-mem accessors, the dw_pcie_link_up() method for some unobvious reason directly calls readl() to get PortLogic.DEBUG1 register content. Since the way the dbi-bus is accessed can be platform-specific let's replace the direct dbi memory space read procedure with the readl-wrapper invocation. Thus we'll have a slightly more generic dw_pcie_link_up() method. Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index f4d9184258c4..0ed5b9a08dfd 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -548,7 +548,7 @@ int dw_pcie_link_up(struct dw_pcie *pci) if (pci->ops && pci->ops->link_up) return pci->ops->link_up(pci); - val = readl(pci->dbi_base + PCIE_PORT_DEBUG1); + val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1); return ((val & PCIE_PORT_DEBUG1_LINK_UP) && (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); } From patchwork Tue May 17 12:50:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852401 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 977E6C433F5 for ; Tue, 17 May 2022 12:51:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346484AbiEQMvy (ORCPT ); Tue, 17 May 2022 08:51:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346461AbiEQMvw (ORCPT ); Tue, 17 May 2022 08:51:52 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1396540A12; Tue, 17 May 2022 05:51:48 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 52046BDB; Tue, 17 May 2022 15:52:43 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 52046BDB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791964; bh=GDpe6sxaX1HL2b20b4PQZVdtCQsuX7sYvlNk4XwXwtk=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=cOlvGk5EYSx2G73TGf45crGao3YfwKPVm8JaBDw9ciAaVXD7HnIZhA+aQVN9m7b9z qv3u3mTb1CJD+7HGzUq+sK1VTtxb7asNijSiRy/Ve+6fPbibhfunGx8nFq9Dg5POVM YNaNkVlw6SknMAwL+7qlSoFp0PNf1fkAg29q/DMs= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:46 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Joao Pinto , Niklas Cassel CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 10/13] PCI: dwc: Deallocate EPC memory on EP init error Date: Tue, 17 May 2022 15:50:55 +0300 Message-ID: <20220517125058.18488-11-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org If the dw_pcie_ep_init() method fails to perform any action after the EPC memory is initialized and the MSI memory region is allocated, the later parts won't be undone thus causing the memory leak. Let's fix that by introducing the cleanup-on-error path in the dw_pcie_ep_init() method, which will be taken should any consequent erroneous situation happens. Fixes: 2fd0c9d966cc ("PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init") Signed-off-by: Serge Semin Tested-by: Manivannan Sadhasivam --- Changelog v2: - This is a new patch create as a result of the discussion in: Link: https://lore.kernel.org/linux-pci/20220324014836.19149-26-Sergey.Semin@baikalelectronics.ru --- .../pci/controller/dwc/pcie-designware-ep.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 7c9315fffe24..7ad349c32082 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -780,8 +780,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, epc->mem->window.page_size); if (!ep->msi_mem) { + ret = -ENOMEM; dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); - return -ENOMEM; + goto err_exit_epc_mem; } if (ep->ops->get_features) { @@ -790,6 +791,19 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) return 0; } - return dw_pcie_ep_init_complete(ep); + ret = dw_pcie_ep_init_complete(ep); + if (ret) + goto err_free_epc_mem; + + return 0; + +err_free_epc_mem: + pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, + epc->mem->window.page_size); + +err_exit_epc_mem: + pci_epc_mem_exit(epc); + + return ret; } EXPORT_SYMBOL_GPL(dw_pcie_ep_init); From patchwork Tue May 17 12:50:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852400 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 918E1C433FE for ; Tue, 17 May 2022 12:51:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345424AbiEQMvx (ORCPT ); Tue, 17 May 2022 08:51:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346419AbiEQMvw (ORCPT ); Tue, 17 May 2022 08:51:52 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3C04841310; Tue, 17 May 2022 05:51:48 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 58648BDC; Tue, 17 May 2022 15:52:44 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 58648BDC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791964; bh=cM5u3ySm5KFAZtnNJUew4vub5mlpNgTTcbb9LtXOqVo=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=ksog2Mdu/U3Au8fYhEKQwQxS7FFK3gklUsscqrhifTGEgYD/qf+uY6h9ph5R9A22T KuOzVta1CTkLz2auYdpbKlK2jCP7FN92Ii5g+XAIk8xg19JlQF+Va/7awp7r+kOfoJ jsutibdVJ5qRWTcl18vSyQYvsrSKHoGftU1d9j38= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:47 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 11/13] PCI: dwc-plat: Simplify the probe method return value handling Date: Tue, 17 May 2022 15:50:56 +0300 Message-ID: <20220517125058.18488-12-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The whole switch-case-logic implemented in the DWC PCIe RC/EP probe procedure doesn't seem well thought through. First of all the ret variable is unused in the EP-case and is only partly involved in the RC-case of the switch-case statement, which unnecessary complicates the code. Secondly the probe method will return zero if an unknown mode is detected. That is improbable situation since the OF-device data is initialized only with valid modes, but such code is still wrong at least from maintainability point of view. So let's convert the switch-case part of the probe function to being more coherent. We suggest to use the local ret variable to preserve the status of the case-clauses and return its value from the probe procedure after the work is done. Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-plat.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 0c5de87d3cc6..fea785096261 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -153,20 +153,21 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) return -ENODEV; ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev); - if (ret < 0) - return ret; break; case DW_PCIE_EP_TYPE: if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP)) return -ENODEV; pci->ep.ops = &pcie_ep_ops; - return dw_pcie_ep_init(&pci->ep); + ret = dw_pcie_ep_init(&pci->ep); + break; default: dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode); + ret = -EINVAL; + break; } - return 0; + return ret; } static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = { From patchwork Tue May 17 12:50:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30775C433EF for ; Tue, 17 May 2022 12:52:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346496AbiEQMv4 (ORCPT ); Tue, 17 May 2022 08:51:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346477AbiEQMvx (ORCPT ); Tue, 17 May 2022 08:51:53 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1BFB421814; Tue, 17 May 2022 05:51:49 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 3EEF3BDD; Tue, 17 May 2022 15:52:45 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 3EEF3BDD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791965; bh=UfWVf1OqmdouqYPgUtKoC9/yssJVHDHj0nx0QhN9x/0=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=ZoYnNdc7jq914aBvikzdPDLnpqXN1gw09LIiqm7nbN0BZfELVSphkbe7dRzFZ4PG0 GDpFIrZDDyxdWuQZdFTfUHwraRF93czTs8USv1Y8cGhW5/BpVScqiFHDRCk0wZ7LI3 ASnhYgTe0L2eOADO3cWmDcCRyLV6AfQvOWU40+Hg= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:48 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 12/13] PCI: dwc-plat: Discard unused regmap pointer Date: Tue, 17 May 2022 15:50:57 +0300 Message-ID: <20220517125058.18488-13-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The regmap pointer was added into the dw_plat_pcie structure in commit 1d906b22076e ("PCI: dwc: Add support for EP mode"), but it hasn't been utilized neither in the code submitted in the denoted so far nor in the platform driver evolving afterwards. Drop it then for good. Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-plat.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index fea785096261..99cf2ac5b0ba 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -17,13 +17,11 @@ #include #include #include -#include #include "pcie-designware.h" struct dw_plat_pcie { struct dw_pcie *pci; - struct regmap *regmap; enum dw_pcie_device_mode mode; }; From patchwork Tue May 17 12:50:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12852404 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EAB8C433EF for ; Tue, 17 May 2022 12:52:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346501AbiEQMwA (ORCPT ); Tue, 17 May 2022 08:52:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346472AbiEQMvw (ORCPT ); Tue, 17 May 2022 08:51:52 -0400 Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1C35848319; Tue, 17 May 2022 05:51:50 -0700 (PDT) Received: from mail.baikalelectronics.ru (unknown [192.168.51.25]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 34E81BDE; Tue, 17 May 2022 15:52:46 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.ru 34E81BDE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1652791966; bh=HZHoV9nR2DIKYsbB+TvwdZXcaoF4FGsdbHzcXXADxzY=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=fuTlpm6+qjpTzy6X/gRzVwfBT7mXwOgMveNtpLauN9jmBAFtTW7x0G655OdJ0rNqs 6QmJWGi43OLn7HuFLK7gbc86TMIp9f0mSVZl5YO8ae2P1OAlf7Xp7kESzi65uDZAnn fIyz9Vfrm+2mWWKMvIFVU5FrPOcF73th6I8iUORg= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 17 May 2022 15:51:49 +0300 From: Serge Semin To: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: Serge Semin , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , , Subject: [PATCH v3 13/13] PCI: dwc-plat: Drop dw_plat_pcie_of_match forward declaration Date: Tue, 17 May 2022 15:50:58 +0300 Message-ID: <20220517125058.18488-14-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The denoted forward declaration used to be required to get the OF-device ID structure by calling the of_match_device() method. The later method invocation has been replaced with the of_device_get_match_data() call in the commit 5c204204cf24 ("PCI: designware-plat: Prefer of_device_get_match_data()"). Thus the forward declaration of the OF-compatible device strings no longer needed. Drop it for good. Signed-off-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Tested-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-plat.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 99cf2ac5b0ba..e606c5d5f06f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -29,8 +29,6 @@ struct dw_plat_pcie_of_data { enum dw_pcie_device_mode mode; }; -static const struct of_device_id dw_plat_pcie_of_match[]; - static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { };