From patchwork Wed May 18 03:17:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 12853113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F37EFC433EF for ; Wed, 18 May 2022 03:19:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=e1/8x0dNQGJ7ieD/PxhCKDCsYEqFrUGTzSvBlPzhxsw=; b=3+GnbEVXly8Fhb dQ/fJ9hI4GySU9lviz4k7bp9kw/p0GPdqIdythZFhoA8+IoTdGddp/ap8YqJOobvOpSTLQKK5zSVB mG4qQW0fr6dVbWbwJtxfY8m8E5VqaMcDrRhGjDfBg2eyo9a1p7LmKvG1D6QqtJBKOoX0pp5JJPzae a29suM9XM8xsSq0npze2m00eRzp/FaOcYahy+gbl07vQX26IkOzZLWx++tCZU3TZFRwSCJaRUhVGX x4j9KnK3n8Qmj5Dc9PjNpWjYOIQUfMTzv10ksWYZxOFa2kSVgM0FGUrHT7eX5jV1Kpy3mcy8cuVVO 8iCMYr/jRrnFGudUtLvQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrAC7-00GrEH-4Z; Wed, 18 May 2022 03:17:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrAC4-00GrDI-3e for linux-arm-kernel@lists.infradead.org; Wed, 18 May 2022 03:17:49 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D77A41063; Tue, 17 May 2022 20:17:46 -0700 (PDT) Received: from a077893.blr.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 620623F66F; Tue, 17 May 2022 20:17:44 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, Ard Biesheuvel , Anshuman Khandual Subject: [PATCH 1/6] arm64: don't override idmap t0sz Date: Wed, 18 May 2022 08:47:20 +0530 Message-Id: <20220518031725.3128044-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220518031725.3128044-1-anshuman.khandual@arm.com> References: <20220518031725.3128044-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220517_201748_242515_F84DA1A4 X-CRM114-Status: GOOD ( 10.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mark Rutland When the kernel is built with CONFIG_ARM64_VA_BITS_52, __cpu_setup will override `idmap_t0sz`, and program TCR_EL1.T0SZ based on `vabits_actual`. This is inconsistent with cpu_set_idmap_tcr_t0sz(), which will use `idmap_t0sz`, but happens to work as CONFIG_ARM64_VA_BITS_52 requires 64K pages where 48-bit VAs and 52-bit VAs required the same number of page table levels and TTBR0 addresses grow upwards from the base of the PGD table (for which the entire page is zeroed). When switching away from the idmap, cpu_set_default_tcr_t0sz() will use `vabits_actual`, and so the T0SZ value used for the idmap does not have to match the T0SZ used during regular kernel/userspace execution. This patch ensures we *always* use `idmap_t0sz` as the TCR_EL1.T0SZ value used while the idmap is active. Cc: Ard Biesheuvel Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Mark Rutland Signed-off-by: Anshuman Khandual Acked-by: Ard Biesheuvel --- arch/arm64/mm/proc.S | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 50bbed947bec..c1f76bf3276c 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -468,9 +468,8 @@ SYM_FUNC_START(__cpu_setup) sub x9, xzr, x9 add x9, x9, #64 tcr_set_t1sz tcr, x9 -#else - ldr_l x9, idmap_t0sz #endif + ldr_l x9, idmap_t0sz tcr_set_t0sz tcr, x9 /* From patchwork Wed May 18 03:17:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 12853115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15475C433EF for ; Wed, 18 May 2022 03:19:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2/2ZHsDfeh94AEt+xhMWv+uiuKNVy5TfqzjerxzX73o=; b=TqAJa6wUTn5eUe VcrcG0mQQj8cQAtH6+m2OE/Ji3GybwNqKQSbkTBQNY/OPSLYMXIPiO9YI0Ep/BTR+HRSiT7KHU45+ fbSngNY90TmVBqq7rb9Nez47b7aXpJSCP9dhSyf4mgrXPHeYPxglCZ/rVHNedR5JHS/jcJH5Lc/f4 JdAqeLQoiNkP1Y3Aln6l/icWeZ8gDfbG8jaW5/ovhlBpTp0zEtP6ze49qa7X0cUN3ytJwBcmA6QlK 9qyhe9zEthaN0FOOxSyjRPAe42Sj9oceNhdpHefrfALkHgKPwHaM77J1nfmMy8THLlroMvyX/yAjE MDCmjrJdgpffgLFt0R/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrACR-00GrIu-3Y; Wed, 18 May 2022 03:18:11 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrAC6-00GrEB-I6 for linux-arm-kernel@lists.infradead.org; Wed, 18 May 2022 03:17:52 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CFA961042; Tue, 17 May 2022 20:17:49 -0700 (PDT) Received: from a077893.blr.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 73E693F66F; Tue, 17 May 2022 20:17:47 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, Ard Biesheuvel , Anshuman Khandual Subject: [PATCH 2/6] arm64: head: remove __PHYS_OFFSET Date: Wed, 18 May 2022 08:47:21 +0530 Message-Id: <20220518031725.3128044-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220518031725.3128044-1-anshuman.khandual@arm.com> References: <20220518031725.3128044-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220517_201750_684844_583714DC X-CRM114-Status: GOOD ( 12.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mark Rutland It's very easy to confuse __PHYS_OFFSET and PHYS_OFFSET. To clarify things, let's remove __PHYS_OFFSET and use KERNEL_START directly, with comments to show that we're using physical address, as we do for other objects. At the same time, update the comment regarding the kernel entry address to mention __pa(KERNEL_START) rather than __pa(PAGE_OFFSET). There should be no functional change as a result of this patch. Cc: Ard Biesheuvel Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Mark Rutland Signed-off-by: Anshuman Khandual Acked-by: Ard Biesheuvel --- arch/arm64/kernel/head.S | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 6a98f1a38c29..aaad76680495 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -37,8 +37,6 @@ #include "efi-header.S" -#define __PHYS_OFFSET KERNEL_START - #if (PAGE_OFFSET & 0x1fffff) != 0 #error PAGE_OFFSET must be at least 2MB aligned #endif @@ -52,7 +50,7 @@ * x0 = physical address to the FDT blob. * * This code is mostly position independent so you call this at - * __pa(PAGE_OFFSET). + * __pa(KERNEL_START). * * Note that the callee-saved registers are used for storing variables * that are useful before the MMU is enabled. The allocations are described @@ -91,7 +89,7 @@ SYM_CODE_START(primary_entry) bl preserve_boot_args bl init_kernel_el // w0=cpu_boot_mode - adrp x23, __PHYS_OFFSET + adrp x23, KERNEL_START // __pa(KERNEL_START) and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 bl set_cpu_boot_mode_flag bl __create_page_tables @@ -420,7 +418,7 @@ SYM_FUNC_END(__create_page_tables) /* * The following fragment of code is executed with the MMU enabled. * - * x0 = __PHYS_OFFSET + * x0 = __pa(KERNEL_START) */ SYM_FUNC_START_LOCAL(__primary_switched) adr_l x4, init_task @@ -870,7 +868,7 @@ SYM_FUNC_START_LOCAL(__primary_switch) bl __relocate_kernel #ifdef CONFIG_RANDOMIZE_BASE ldr x8, =__primary_switched - adrp x0, __PHYS_OFFSET + adrp x0, KERNEL_START // __pa(KERNEL_START) blr x8 /* @@ -893,6 +891,6 @@ SYM_FUNC_START_LOCAL(__primary_switch) #endif #endif ldr x8, =__primary_switched - adrp x0, __PHYS_OFFSET + adrp x0, KERNEL_START // __pa(KERNEL_START) br x8 SYM_FUNC_END(__primary_switch) From patchwork Wed May 18 03:17:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 12853116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D572C433EF for ; Wed, 18 May 2022 03:19:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/J1iwgeJKYYSa7qh1uWvzaeCyFB9FvgBl11ziqZK1IY=; b=oPyepYBslW6LZA LW9Rh33l9lRRbv8GqDioFL5sLnRoW8tA4ae2ogdbGSRlwHF6wpW2p/heDs65HkZaS2GKvVleBh6bu S7E5zq04x86kSEGEHksxk0vQm7YfAQDiUpqIQ/Vu4KnWxem6mIo2p8g/WBKEA40YTI+9LjSjwVWaq 8jQtnIoojeA/Ni9ifaV+bBoQYKvsrdr5vHz5qPUSXrj8MSxpVxg3Tlj4h+WNxQlfWYVuHFWsBuzwG Gh1u1bt0QXWEA1ES9w3XkVWu+Fb44WAuTUN/oqQLD3qdyQwTDERG64Wc1z4csjUUbcEqAITvZ6Q4+ 7GDPv3fiwyKJGceaw33w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrACf-00GrNl-L6; Wed, 18 May 2022 03:18:25 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrAC9-00GrEo-S2 for linux-arm-kernel@lists.infradead.org; Wed, 18 May 2022 03:17:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E17C41042; Tue, 17 May 2022 20:17:52 -0700 (PDT) Received: from a077893.blr.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6CA3D3F66F; Tue, 17 May 2022 20:17:50 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, Ard Biesheuvel , Anshuman Khandual Subject: [PATCH 3/6] arm64: head: clarify `populate_entries` Date: Wed, 18 May 2022 08:47:22 +0530 Message-Id: <20220518031725.3128044-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220518031725.3128044-1-anshuman.khandual@arm.com> References: <20220518031725.3128044-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220517_201754_045065_DDE95D7E X-CRM114-Status: GOOD ( 12.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mark Rutland For a few reasons, `populate_entries` can be harder than necessary to understand. This patch improves the commentary and naming to make it easier to follow: * Commentary is update to explicitly describe the span of adjacent pages which `populate_entries` operates on, and what entries correspond to at each level. * As `rtbl` is not always a table, is renamed to `phys`, as it always represents a physical address. * `index` and `eindex` are renamed to `istart` and `iend` respectively, to match the naming used in `compute_indices` where these values are generated. * As "to or in" can be difficult to read, the commentary for `flags` is reworded in terms of "bits to set". There should be no functional change as a result of this patch. Cc: Ard Biesheuvel Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Mark Rutland Signed-off-by: Anshuman Khandual --- arch/arm64/kernel/head.S | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index aaad76680495..b5d7dacbbb2c 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -144,28 +144,30 @@ SYM_CODE_END(preserve_boot_args) .endm /* - * Macro to populate page table entries, these entries can be pointers to the next level - * or last level entries pointing to physical memory. + * Populate a span of adjacent page tables with entries. For non-leaf levels, + * each entry points to a table in a span of adjacent page tables at the next + * level. For the leaf level these entries point to a span of physical memory + * being mapped. * - * tbl: page table address - * rtbl: pointer to page table or physical memory - * index: start index to write - * eindex: end index to write - [index, eindex] written to - * flags: flags for pagetable entry to or in - * inc: increment to rtbl between each entry + * tbl: physical address of the first table in this span + * phys: physical address of memory or next-level table span + * istart: index of the first entry to write + * iend: index of the last entry to write - [index, eindex] written to + * flags: bits to set in each page table entry + * inc: increment to phys between each entry * tmp1: temporary variable * - * Preserves: tbl, eindex, flags, inc - * Corrupts: index, tmp1 - * Returns: rtbl + * Preserves: tbl, iend, flags, inc + * Corrupts: istart, tmp1 + * Returns: phys */ - .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1 -.Lpe\@: phys_to_pte \tmp1, \rtbl + .macro populate_entries, tbl, phys, istart, iend, flags, inc, tmp1 +.Lpe\@: phys_to_pte \tmp1, \phys orr \tmp1, \tmp1, \flags // tmp1 = table entry - str \tmp1, [\tbl, \index, lsl #3] - add \rtbl, \rtbl, \inc // rtbl = pa next level - add \index, \index, #1 - cmp \index, \eindex + str \tmp1, [\tbl, \istart, lsl #3] + add \phys, \phys, \inc + add \istart, \istart, #1 + cmp \istart, \iend b.ls .Lpe\@ .endm From patchwork Wed May 18 03:17:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 12853117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE655C433F5 for ; Wed, 18 May 2022 03:19:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IqMqzUH69wTlPi+RmGNvk+1DoKgVikpWEDKwsFuIp4U=; b=PG6M57nvHJglve AkMsj/uGddtk8dpFqVuAHfszeedDwLDYLFNSirxPEE5N8+Jt8AMjrRX8EfNGzU2IOB1Y/ZXI+4kVk SKW9fntJizls0tnoeOU9C1PDPQkH1qsfgYhcPP+/OkoloSGSnGbUQTjhMsRmmb9PBZyDYwiR+rmEW nCflWE7fDZ32vQe25XgxpfiTL9PkHTZsQesvDd8qp/x1QhAmQtUQXJEuTl/z89LfPAU+rdK/+AHE2 V6GMDYQ3rf2ffN+KbY1RWMX8r8J4rKgr/0pjMsJIMqIXuqWIrUWhdnmPzodhYWNkxc/Lb1O6Ha4ZQ f/ZftoLmH/L7No8t0dTA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrACq-00GrRH-GP; Wed, 18 May 2022 03:18:36 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrACC-00GrFK-CX for linux-arm-kernel@lists.infradead.org; Wed, 18 May 2022 03:17:58 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C26DC1042; Tue, 17 May 2022 20:17:55 -0700 (PDT) Received: from a077893.blr.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7E8113F66F; Tue, 17 May 2022 20:17:53 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, Ard Biesheuvel , Anshuman Khandual Subject: [PATCH 4/6] arm64: head: clarify `compute_indices` Date: Wed, 18 May 2022 08:47:23 +0530 Message-Id: <20220518031725.3128044-5-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220518031725.3128044-1-anshuman.khandual@arm.com> References: <20220518031725.3128044-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220517_201756_574708_23F076E1 X-CRM114-Status: UNSURE ( 9.69 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mark Rutland The logic in the `compute_indices` macro can be difficult to follow, as it transiently uses output operands for unrelated temporary values. Let's make this clearer by using a `tmp` parameter, and splitting the logic into commented blocks. By folding a MUL and ADD into a single MADD we avoid the need for a second temporary. As `ptrs` is sometimes a register and sometimes an immediate, we cannot simplify this much further at present. If it were always a register, we could remove redundant MOVs, and if it were always an immediate we could use `(\ptrs - 1)` as an immediate for the ANDs when extracting index bits (or replace the LSR; SUB; AND sequence with a single UBFX). There should be no funcitonal change as a result of this patch. Cc: Ard Biesheuvel Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Mark Rutland Signed-off-by: Anshuman Khandual --- arch/arm64/kernel/head.S | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index b5d7dacbbb2c..01739f5ec3de 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -189,20 +189,23 @@ SYM_CODE_END(preserve_boot_args) * Preserves: vstart, vend, shift, ptrs * Returns: istart, iend, count */ - .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count + .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count, tmp + // iend = (vend >> shift) & (ptrs - 1) lsr \iend, \vend, \shift - mov \istart, \ptrs - sub \istart, \istart, #1 - and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1) - mov \istart, \ptrs - mul \istart, \istart, \count - add \iend, \iend, \istart // iend += count * ptrs - // our entries span multiple tables + mov \tmp, \ptrs + sub \tmp, \tmp, #1 + and \iend, \iend, \tmp + // iend += count * ptrs + // our entries span multiple tables + mov \tmp, \ptrs + madd \iend, \count, \tmp, \iend + + // istart = (vend >> shift) & (ptrs - 1) lsr \istart, \vstart, \shift - mov \count, \ptrs - sub \count, \count, #1 - and \istart, \istart, \count + mov \tmp, \ptrs + sub \tmp, \tmp, #1 + and \istart, \istart, \tmp sub \count, \iend, \istart .endm @@ -229,25 +232,25 @@ SYM_CODE_END(preserve_boot_args) add \rtbl, \tbl, #PAGE_SIZE mov \sv, \rtbl mov \count, #0 - compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count + compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count, \tmp populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp mov \tbl, \sv mov \sv, \rtbl #if SWAPPER_PGTABLE_LEVELS > 3 - compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count + compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count, \tmp populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp mov \tbl, \sv mov \sv, \rtbl #endif #if SWAPPER_PGTABLE_LEVELS > 2 - compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count + compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count, \tmp populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp mov \tbl, \sv #endif - compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count + compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count, \tmp bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1 populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp .endm From patchwork Wed May 18 03:17:24 2022 Content-Type: text/plain; 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Tue, 17 May 2022 20:17:56 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, Anshuman Khandual Subject: [PATCH 5/6] arm64: head: clarify `map_memory` Date: Wed, 18 May 2022 08:47:24 +0530 Message-Id: <20220518031725.3128044-6-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220518031725.3128044-1-anshuman.khandual@arm.com> References: <20220518031725.3128044-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220517_201758_968584_02A92E63 X-CRM114-Status: UNSURE ( 9.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mark Rutland In the `map_memory` macro we repurpose the `count` temporary register to hold the physical address `phys` aligned downwards to SWAPPER_BLOCK_SIZE. Due to the subtle usage of `count` elsewhere, this is a little confusing, and is also unnecessary as we can safely corrupt `phys`, which is not used after `map_memory` completes. This patch makes `map_memory` manipulate `phys` in-place, and updates the documentation to mention that it corrupts `phys`. Signed-off-by: Mark Rutland Signed-off-by: Anshuman Khandual --- arch/arm64/kernel/head.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 01739f5ec3de..107275e06212 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -225,7 +225,7 @@ SYM_CODE_END(preserve_boot_args) * * Temporaries: istart, iend, tmp, count, sv - these need to be different registers * Preserves: vstart, flags - * Corrupts: tbl, rtbl, vend, istart, iend, tmp, count, sv + * Corrupts: tbl, rtbl, vend, phys, istart, iend, tmp, count, sv */ .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv sub \vend, \vend, #1 @@ -251,8 +251,8 @@ SYM_CODE_END(preserve_boot_args) #endif compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count, \tmp - bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1 - populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp + bic \phys, \phys, #SWAPPER_BLOCK_SIZE - 1 + populate_entries \tbl, \phys, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp .endm /* From patchwork Wed May 18 03:17:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 12853119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44416C433EF for ; Wed, 18 May 2022 03:20:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JzDVIzKjHiJp6EGXFAaIVKQWhGwOoeKfsnnXxm5Lh1A=; b=cx0w2XleOY0uW0 sTfZ8p+e4xcq/94oeNyKOC8fUuwsNxJvWRgXrEivYSVmrzN8c4kV1E10kAF/r9oV/5XV1Z78lHyUJ yZssjWVCOCkUUzRQApdlyiTv4A5z/GYWof97UR2dCUvzIVf5Z8/JfhgyZdiGq2eMOvcJAuwebaM5z ZxH6symAF90DXxSTTnfdqtpk1vgrWjsHozQ5ZzFYqFdoVO5syQxPVYM/MIauE9YvaJA0HTu6hkNgr xWm/z0IBltMha93YswjvsDlc5dezKZK37gi8aZQ9RIw4vWw3R5AIi+EAIXpPrFLBY+NdjwI1L/Fjr H3U0e+ctJ2BX/TsaArYQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrADJ-00Grge-R8; Wed, 18 May 2022 03:19:05 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrACH-00GrGm-MR for linux-arm-kernel@lists.infradead.org; Wed, 18 May 2022 03:18:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DE45F1042; Tue, 17 May 2022 20:18:00 -0700 (PDT) Received: from a077893.blr.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AC5DB3F66F; Tue, 17 May 2022 20:17:58 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, Ard Biesheuvel , Anshuman Khandual Subject: [PATCH 6/6] arm64: head: clarify commentary for __create_page_tables Date: Wed, 18 May 2022 08:47:25 +0530 Message-Id: <20220518031725.3128044-7-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220518031725.3128044-1-anshuman.khandual@arm.com> References: <20220518031725.3128044-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220517_201801_848150_38FB8EE0 X-CRM114-Status: GOOD ( 12.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mark Rutland The comments in __create_page_tables have become stale and potentially misleading over time. The kernel tables cover all of the kernel image but none of the linear map (which is created separately later), and the kernel mapping does not start at PHYS_OFFSET (which is the physical start of the linear map). Update the comments to be more precise. There should be no functional change as a result of this patch. Cc: Ard Biesheuvel Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Mark Rutland Signed-off-by: Anshuman Khandual --- arch/arm64/kernel/head.S | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 107275e06212..349ef0ed9aa9 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -256,11 +256,14 @@ SYM_CODE_END(preserve_boot_args) .endm /* - * Setup the initial page tables. We only setup the barest amount which is - * required to get the kernel running. The following sections are required: - * - identity mapping to enable the MMU (low address, TTBR0) - * - first few MB of the kernel linear mapping to jump to once the MMU has - * been enabled + * Setup the initial page tables. + * + * The idmap page tables map the idmap page in TTBR0, with VA == PA. This + * covers the interval [__idmap_text_start, __idmap_text_end - 1] + * + * The initial kernel page tables map the kernel image in TTBR1, with _text + * mapped to VA (KIMAGE_VADDR + KASLR offset). This covers the interval + * [_text, _end - 1] */ SYM_FUNC_START_LOCAL(__create_page_tables) mov x28, lr @@ -363,7 +366,7 @@ SYM_FUNC_START_LOCAL(__create_page_tables) map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14 /* - * Map the kernel image (starting with PHYS_OFFSET). + * Map the kernel image */ adrp x0, init_pg_dir mov_q x5, KIMAGE_VADDR // compile time __va(_text)