From patchwork Wed May 18 07:48:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Kumar X-Patchwork-Id: 12853287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B920C433F5 for ; Wed, 18 May 2022 07:49:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232508AbiERHtP (ORCPT ); Wed, 18 May 2022 03:49:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232514AbiERHtM (ORCPT ); Wed, 18 May 2022 03:49:12 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD06A11E4AA; Wed, 18 May 2022 00:49:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652860150; x=1684396150; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=IJmTyyhkjw1/0964q9JMarha0/iXW7c0hLj3X9s0kmc=; b=jWtLWKthHw9QzoAhlnMTCv/1rdU/ZIlpwaiwiBiZJiqk/lRFACHUNb/u MWxGBwhWX/lMASlmdAmZGlUMZRX5Lp213/yXt8W7IyPDGmTwyZjzT4pC2 w1KClwj7triO73WwW+y69yPJDbji8xPh74mwa/EHT9Yr5XyvoIXQ6Q7Yd g=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 18 May 2022 00:49:10 -0700 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 00:49:09 -0700 Received: from blr-ubuntu-185.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 18 May 2022 00:49:00 -0700 From: Vivek Kumar To: , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , Vivek Kumar , Prasanna Kumar Subject: [RFC 1/6] arm64: hibernate: Introduce new entry point to kernel Date: Wed, 18 May 2022 13:18:36 +0530 Message-ID: <1652860121-24092-2-git-send-email-quic_vivekuma@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652860121-24092-1-git-send-email-quic_vivekuma@quicinc.com> References: <1652860121-24092-1-git-send-email-quic_vivekuma@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce a new entry point to hibernated kernel image. This is generally needed when bootloader restores the hibernated image from disc to ddr and passes control to it by turning off the mmu, also initialize this new entry point with cpu_resume which turns on the mmu and then proceeds with restore routines. Signed-off-by: Vivek Kumar Signed-off-by: Prasanna Kumar --- arch/arm64/kernel/hibernate.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c index 6328308..4e294b3 100644 --- a/arch/arm64/kernel/hibernate.c +++ b/arch/arm64/kernel/hibernate.c @@ -74,6 +74,14 @@ static struct arch_hibernate_hdr { void (*reenter_kernel)(void); /* + * Another entry point if jump to kernel happens with mmu disabled, + * generally done when restoring hibernation image from bootloader + * context + */ + + phys_addr_t phys_reenter_kernel; + + /* * We need to know where the __hyp_stub_vectors are after restore to * re-configure el2. */ @@ -116,6 +124,7 @@ int arch_hibernation_header_save(void *addr, unsigned int max_size) arch_hdr_invariants(&hdr->invariants); hdr->ttbr1_el1 = __pa_symbol(swapper_pg_dir); hdr->reenter_kernel = _cpu_resume; + hdr->phys_reenter_kernel = __pa(cpu_resume); /* We can't use __hyp_get_vectors() because kvm may still be loaded */ if (el2_reset_needed()) From patchwork Wed May 18 07:48:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Kumar X-Patchwork-Id: 12853288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7ED93C433FE for ; Wed, 18 May 2022 07:49:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232514AbiERHtX (ORCPT ); Wed, 18 May 2022 03:49:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232503AbiERHtS (ORCPT ); Wed, 18 May 2022 03:49:18 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D780C11E4B6; Wed, 18 May 2022 00:49:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652860158; x=1684396158; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=rOYdWmdQCnEpAHcJFCYdRtOeaAOYF7eoFxilIXHP6Bo=; b=f76IxhdMGRpcFIVZl4IoTOvtiIGxMgmbcF5O68qO3WRp3t0i5EFlC3nQ GP2f97x2etzlO2ZE3TygF0xsWdZsNTQTcZEDjgvE+cYvxJvuRuRLVpGse YjdmChiVaYpg0oHfvMguDJ/JPDTve9Qy17U7qma1wL+izhjsTabITBwxt Y=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 18 May 2022 00:49:17 -0700 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 00:49:17 -0700 Received: from blr-ubuntu-185.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 18 May 2022 00:49:09 -0700 From: Vivek Kumar To: , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , Vivek Kumar , Prasanna Kumar Subject: [RFC 2/6] PM: Hibernate: Add option to disable disk offset randomization Date: Wed, 18 May 2022 13:18:37 +0530 Message-ID: <1652860121-24092-3-git-send-email-quic_vivekuma@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652860121-24092-1-git-send-email-quic_vivekuma@quicinc.com> References: <1652860121-24092-1-git-send-email-quic_vivekuma@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add a kernel parameter to disable the disk offset randomization for SSD devices in which such feature is available at the firmware level. This is helpful in improving hibernation resume time. Signed-off-by: Vivek Kumar Signed-off-by: Prasanna Kumar --- Documentation/admin-guide/kernel-parameters.txt | 11 +++++++++++ kernel/power/swap.c | 9 +++++++++ 2 files changed, 20 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 666ade9..06b4f10 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5192,6 +5192,17 @@ Useful for devices that are detected asynchronously (e.g. USB and MMC devices). + noswap_randomize + Kernel uses random disk offsets to help with wear-levelling + of SSD devices, while saving the hibernation snapshot image to + disk. Use this parameter to disable this feature for SSD + devices in scenarios when, such randomization is addressed at + the firmware level and hibenration image is not re-generated + frequently. + (Useful for improving hibernation resume time as snapshot pages + are available in disk serially and can be read in bigger chunks + without seeking) + retain_initrd [RAM] Keep initrd memory after extraction rfkill.default_state= diff --git a/kernel/power/swap.c b/kernel/power/swap.c index 91fffdd..8d5c811 100644 --- a/kernel/power/swap.c +++ b/kernel/power/swap.c @@ -44,6 +44,7 @@ u32 swsusp_hardware_signature; */ static bool clean_pages_on_read; static bool clean_pages_on_decompress; +static bool noswap_randomize; /* * The swap map is a data structure used for keeping track of each page @@ -1616,3 +1617,11 @@ static int __init swsusp_header_init(void) } core_initcall(swsusp_header_init); + +static int __init noswap_randomize_setup(char *str) +{ + noswap_randomize = true; + return 1; +} + +__setup("noswap_randomize", noswap_randomize_setup); From patchwork Wed May 18 07:48:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Kumar X-Patchwork-Id: 12853289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6E36C4332F for ; Wed, 18 May 2022 07:49:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232541AbiERHt1 (ORCPT ); Wed, 18 May 2022 03:49:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232518AbiERHt0 (ORCPT ); Wed, 18 May 2022 03:49:26 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1EA991207DE; Wed, 18 May 2022 00:49:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652860166; x=1684396166; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=2p+D/WdtUzo7ZNUrDbOnD9yJq+2AeopkckDysa1nz80=; b=tQCfcPvOz6bnrV7muXGxEVPBWt6WJvrrfLTOEre3u2lkQ8TkOCcAx2t7 XiPj5NJhPPDSdAuaysQOrwJlpYhFBcyE6zrOytBeO5iUKxnCE400PPXo/ yNShTkQSMcSyekk99XrTz2cqTZQFozC8BfhqwJiwcvL9mT0Qeq/09ywMk 0=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 18 May 2022 00:49:25 -0700 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 00:49:25 -0700 Received: from blr-ubuntu-185.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 18 May 2022 00:49:17 -0700 From: Vivek Kumar To: , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , Vivek Kumar , Prasanna Kumar Subject: [RFC 3/6] block: gendisk: Add a new genhd capability flag Date: Wed, 18 May 2022 13:18:38 +0530 Message-ID: <1652860121-24092-4-git-send-email-quic_vivekuma@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652860121-24092-1-git-send-email-quic_vivekuma@quicinc.com> References: <1652860121-24092-1-git-send-email-quic_vivekuma@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add a new genhd capability flag to serialize offsets for swap partition. This flag is enabled for the gendisk of the block device which will be used for saving the snapshot of the hibernation image, based on a kernel parameter "noswap_randomize". Serializing offset in swap partition helps in improving hibernation resume time from bootloader. Signed-off-by: Vivek Kumar Signed-off-by: Prasanna Kumar --- include/linux/blkdev.h | 1 + kernel/power/swap.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index 1b24c1f..be094e7 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -92,6 +92,7 @@ enum { GENHD_FL_REMOVABLE = 1 << 0, GENHD_FL_HIDDEN = 1 << 1, GENHD_FL_NO_PART = 1 << 2, + GENHD_FL_NO_RANDOMIZE = 1 << 3, }; enum { diff --git a/kernel/power/swap.c b/kernel/power/swap.c index 8d5c811..0a40eda 100644 --- a/kernel/power/swap.c +++ b/kernel/power/swap.c @@ -1526,6 +1526,9 @@ int swsusp_check(void) FMODE_READ | FMODE_EXCL, &holder); if (!IS_ERR(hib_resume_bdev)) { set_blocksize(hib_resume_bdev, PAGE_SIZE); + if (noswap_randomize) + hib_resume_bdev->bd_disk->flags |= + GENHD_FL_NO_RANDOMIZE; clear_page(swsusp_header); error = hib_submit_io(REQ_OP_READ, 0, swsusp_resume_block, From patchwork Wed May 18 07:48:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Kumar X-Patchwork-Id: 12853290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B48FC433FE for ; Wed, 18 May 2022 07:49:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232535AbiERHtm (ORCPT ); Wed, 18 May 2022 03:49:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232570AbiERHtg (ORCPT ); Wed, 18 May 2022 03:49:36 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A51841207F2; Wed, 18 May 2022 00:49:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652860175; x=1684396175; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=99lVhG/h33c7dvn7i8VK817/c8neC8rVGDsrRyn9LtQ=; b=hziupHJXDuE1SsLmTiu5/jMaI/SkNdo/9lvNqRxcvhM1piLfW0Pb8Xq6 bh+tRMO6G4rfhSTzrpEre1ZPbVWw70ReNx1GJdryyqVOdmZjEVh3bI3sE 7Ak/8oqQIKTO0XpQjdz2/59rQdj+Tw9Cv9hkGtyl3zFxEAwclVmqMEC0G Q=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 18 May 2022 00:49:34 -0700 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 00:49:33 -0700 Received: from blr-ubuntu-185.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 18 May 2022 00:49:25 -0700 From: Vivek Kumar To: , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , Vivek Kumar , Prasanna Kumar Subject: [RFC 4/6] mm: swap: Add randomization check for swapon/off calls Date: Wed, 18 May 2022 13:18:39 +0530 Message-ID: <1652860121-24092-5-git-send-email-quic_vivekuma@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652860121-24092-1-git-send-email-quic_vivekuma@quicinc.com> References: <1652860121-24092-1-git-send-email-quic_vivekuma@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add addtional check on swapon/swapoff sycalls to disable randomization of swap offsets if GENHD_FL_NO_RANDOMIZE flag is passed. Signed-off-by: Vivek Kumar Signed-off-by: Prasanna Kumar --- mm/swapfile.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/mm/swapfile.c b/mm/swapfile.c index 1c3d5b9..a3eeab6 100644 --- a/mm/swapfile.c +++ b/mm/swapfile.c @@ -2474,7 +2474,8 @@ SYSCALL_DEFINE1(swapoff, const char __user *, specialfile) if (p->flags & SWP_CONTINUED) free_swap_count_continuations(p); - if (!p->bdev || !bdev_nonrot(p->bdev)) + if (!p->bdev || (p->bdev->bd_disk->flags & GENHD_FL_NO_RANDOMIZE) + || !bdev_nonrot(p->bdev)) atomic_dec(&nr_rotate_swap); mutex_lock(&swapon_mutex); @@ -3065,7 +3066,8 @@ SYSCALL_DEFINE2(swapon, const char __user *, specialfile, int, swap_flags) if (p->bdev && p->bdev->bd_disk->fops->rw_page) p->flags |= SWP_SYNCHRONOUS_IO; - if (p->bdev && bdev_nonrot(p->bdev)) { + if (p->bdev && !(p->bdev->bd_disk->flags & GENHD_FL_NO_RANDOMIZE) && + bdev_nonrot(p->bdev)) { int cpu; unsigned long ci, nr_cluster; From patchwork Wed May 18 07:48:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Kumar X-Patchwork-Id: 12853291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65719C433EF for ; Wed, 18 May 2022 07:49:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232578AbiERHto (ORCPT ); Wed, 18 May 2022 03:49:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232566AbiERHtn (ORCPT ); Wed, 18 May 2022 03:49:43 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 993AD122B47; Wed, 18 May 2022 00:49:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652860182; x=1684396182; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=lSIe3VyW9rMeUh0m88iIR7bL+fGEX4/7scgZGDYUqTo=; b=uniKWtko1U15hq26Pc97dk32cb/2DgbGq8AzopcSzEqXWnFVBo5eRxvT 4LY69pQjZChG9ZBm78Yk8ofRluRWgY9oPXx6AObkdiapiBszGy20vu3k1 MhCGi8wfIs4UGetnuiMSx5apcy0Iy+RNRw3/4Hqn3NmHNSu9L0Y4fA5pG g=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 18 May 2022 00:49:42 -0700 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 00:49:42 -0700 Received: from blr-ubuntu-185.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 18 May 2022 00:49:33 -0700 From: Vivek Kumar To: , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , Vivek Kumar , Prasanna Kumar Subject: [RFC 5/6] Hibernate: Add check for pte_valid in saveable page Date: Wed, 18 May 2022 13:18:40 +0530 Message-ID: <1652860121-24092-6-git-send-email-quic_vivekuma@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652860121-24092-1-git-send-email-quic_vivekuma@quicinc.com> References: <1652860121-24092-1-git-send-email-quic_vivekuma@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add check for pte_valid in saveable page after being checked for the rest. This is required as PTE is removed for pages allocated with dma_alloc_coherent with DMA_ATTR_NO_KERNEL_MAPPING flag set. This patch makes sure that these pages are not considered for snapshot. Signed-off-by: Vivek Kumar Signed-off-by: Prasanna Kumar --- kernel/power/snapshot.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/kernel/power/snapshot.c b/kernel/power/snapshot.c index 2a40675..a6ad2a5 100644 --- a/kernel/power/snapshot.c +++ b/kernel/power/snapshot.c @@ -1308,6 +1308,41 @@ static inline void *saveable_highmem_page(struct zone *z, unsigned long p) } #endif /* CONFIG_HIGHMEM */ +static bool kernel_pte_present(struct page *page) +{ + pgd_t *pgdp; + p4d_t *p4dp; + pud_t *pudp, pud; + pmd_t *pmdp, pmd; + pte_t *ptep; + unsigned long addr = (unsigned long)page_address(page); + + pgdp = pgd_offset_k(addr); + if (pgd_none(READ_ONCE(*pgdp))) + return false; + + p4dp = p4d_offset(pgdp, addr); + if (p4d_none(READ_ONCE(*p4dp))) + return false; + + pudp = pud_offset(p4dp, addr); + pud = READ_ONCE(*pudp); + if (pud_none(pud)) + return false; + if (pud_sect(pud)) + return true; + + pmdp = pmd_offset(pudp, addr); + pmd = READ_ONCE(*pmdp); + if (pmd_none(pmd)) + return false; + if (pmd_sect(pmd)) + return true; + + ptep = pte_offset_kernel(pmdp, addr); + return pte_valid(READ_ONCE(*ptep)); +} + /** * saveable_page - Check if the given page is saveable. * @@ -1341,6 +1376,14 @@ static struct page *saveable_page(struct zone *zone, unsigned long pfn) && (!kernel_page_present(page) || pfn_is_nosave(pfn))) return NULL; + /* + * Even if page is not reserved and if it's not present in kernel PTE; + * don't snapshot it ! This happens to the pages allocated using + * __dma_alloc_coherent with DMA_ATTR_NO_KERNEL_MAPPING flag set. + */ + if (!kernel_pte_present(page)) + return NULL; + if (page_is_guard(page)) return NULL; From patchwork Wed May 18 07:48:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Kumar X-Patchwork-Id: 12853292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 916E5C4332F for ; Wed, 18 May 2022 07:49:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232596AbiERHty (ORCPT ); Wed, 18 May 2022 03:49:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232600AbiERHtw (ORCPT ); Wed, 18 May 2022 03:49:52 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0AC21207F0; Wed, 18 May 2022 00:49:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652860191; x=1684396191; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=YXZfjMQjUYv74UOxyPEdQftsBYoYCO06rHvgPycGMF8=; b=ZAvNySM6n3yl2pZeG1iXhTqolcDLZaADSHpvy3vuynfXl/faTsnXvTAW 9dYy498KbpKXU2t4bxZ5yBApZyWpfAVS11h2a6re6tcPbsnmG86W+IrGZ aID367ji8W1AhFCNt2YXWmv931bK5OejVxrKjvYE8Dqvewi0z7wx/+3GS c=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 18 May 2022 00:49:50 -0700 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 00:49:50 -0700 Received: from blr-ubuntu-185.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 18 May 2022 00:49:41 -0700 From: Vivek Kumar To: , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , Vivek Kumar , Prasanna Kumar Subject: [RFC 6/6] irqchip/gic-v3: Re-init GIC hardware upon hibernation restore Date: Wed, 18 May 2022 13:18:41 +0530 Message-ID: <1652860121-24092-7-git-send-email-quic_vivekuma@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1652860121-24092-1-git-send-email-quic_vivekuma@quicinc.com> References: <1652860121-24092-1-git-send-email-quic_vivekuma@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Code added in this patch takes backup of different set of registers during hibernation suspend. On receiving hibernation restore callback, it restores register values from backup. This ensures state of hardware to be same just before hibernation and after restore. Signed-off-by: Vivek Kumar Signed-off-by: Prasanna Kumar --- drivers/irqchip/irq-gic-v3.c | 138 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 136 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 2be8dea..442d32f 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -29,6 +29,10 @@ #include #include +#include +#include +#include + #include "irq-gic-common.h" #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) @@ -56,6 +60,14 @@ struct gic_chip_data { bool has_rss; unsigned int ppi_nr; struct partition_desc **ppi_descs; +#ifdef CONFIG_HIBERNATION + unsigned int enabled_irqs[32]; + unsigned int active_irqs[32]; + unsigned int irq_edg_lvl[64]; + unsigned int ppi_edg_lvl; + unsigned int enabled_sgis; + unsigned int pending_sgis; +#endif }; static struct gic_chip_data gic_data __read_mostly; @@ -170,6 +182,9 @@ static enum gic_intid_range get_intid_range(struct irq_data *d) return __get_intid_range(d->hwirq); } +static void gic_dist_init(void); +static void gic_cpu_init(void); + static inline unsigned int gic_irq(struct irq_data *d) { return d->hwirq; @@ -828,7 +843,7 @@ static bool gic_has_group0(void) return val != 0; } -static void __init gic_dist_init(void) +static void gic_dist_init(void) { unsigned int i; u64 affinity; @@ -1399,6 +1414,120 @@ static void gic_cpu_pm_init(void) static inline void gic_cpu_pm_init(void) { } #endif /* CONFIG_CPU_PM */ +#ifdef CONFIG_PM +#ifdef CONFIG_HIBERNATION +extern int in_suspend; +static bool hibernation; + +static int gic_suspend_notifier(struct notifier_block *nb, + unsigned long event, + void *dummy) +{ + if (event == PM_HIBERNATION_PREPARE) + hibernation = true; + else if (event == PM_POST_HIBERNATION) + hibernation = false; + return NOTIFY_OK; +} + +static struct notifier_block gic_notif_block = { + .notifier_call = gic_suspend_notifier, +}; + +static void gic_hibernation_suspend(void) +{ + int i; + void __iomem *base = gic_data.dist_base; + void __iomem *rdist_base = gic_data_rdist_sgi_base(); + + gic_data.enabled_sgis = readl_relaxed(rdist_base + GICD_ISENABLER); + gic_data.pending_sgis = readl_relaxed(rdist_base + GICD_ISPENDR); + /* Store edge level for PPIs by reading GICR_ICFGR1 */ + gic_data.ppi_edg_lvl = readl_relaxed(rdist_base + GICR_ICFGR0 + 4); + + for (i = 0; i * 32 < GIC_LINE_NR; i++) { + gic_data.enabled_irqs[i] = readl_relaxed(base + + GICD_ISENABLER + i * 4); + gic_data.active_irqs[i] = readl_relaxed(base + + GICD_ISPENDR + i * 4); + } + + for (i = 2; i < GIC_LINE_NR / 16; i++) + gic_data.irq_edg_lvl[i] = readl_relaxed(base + + GICD_ICFGR + i * 4); +} +#endif + +static int gic_suspend(void) +{ +#ifdef CONFIG_HIBERNATION + if (unlikely(hibernation)) + gic_hibernation_suspend(); +#endif + return 0; +} + +void gic_resume(void) +{ +#ifdef CONFIG_HIBERNATION + int i; + void __iomem *base = gic_data.dist_base; + void __iomem *rdist_base = gic_data_rdist_sgi_base(); + + /* + * in_suspend is defined in hibernate.c and will be 0 during + * hibernation restore case. Also it willl be 0 for suspend to ram case + * and similar cases. Underlying code will not get executed in regular + * cases and will be executed only for hibernation restore. + */ + if (unlikely((in_suspend == 0 && hibernation))) { + pr_info("Re-initializing gic in hibernation restore\n"); + gic_dist_init(); + gic_cpu_init(); + /* Activate and enable SGIs and PPIs */ + writel_relaxed(gic_data.enabled_sgis, + rdist_base + GICD_ISENABLER); + writel_relaxed(gic_data.pending_sgis, + rdist_base + GICD_ISPENDR); + /* Restore edge and level triggers for PPIs from GICR_ICFGR1 */ + writel_relaxed(gic_data.ppi_edg_lvl, + rdist_base + GICR_ICFGR0 + 4); + + /* Restore edge and level triggers */ + for (i = 2; i < GIC_LINE_NR / 16; i++) + writel_relaxed(gic_data.irq_edg_lvl[i], + base + GICD_ICFGR + i * 4); + gic_dist_wait_for_rwp(); + + /* Activate and enable interrupts from backup */ + for (i = 0; i * 32 < GIC_LINE_NR; i++) { + writel_relaxed(gic_data.active_irqs[i], + base + GICD_ISPENDR + i * 4); + + writel_relaxed(gic_data.enabled_irqs[i], + base + GICD_ISENABLER + i * 4); + } + gic_dist_wait_for_rwp(); + } +#endif +} +EXPORT_SYMBOL_GPL(gic_resume); + +static struct syscore_ops gic_syscore_ops = { + .suspend = gic_suspend, + .resume = gic_resume, +}; + +static void gic_syscore_init(void) +{ + register_syscore_ops(&gic_syscore_ops); +} + +#else +static inline void gic_syscore_init(void) { } +void gic_resume(void) { } +#endif + static struct irq_chip gic_chip = { .name = "GICv3", .irq_mask = gic_mask_irq, @@ -1887,6 +2016,7 @@ static int __init gic_init_bases(void __iomem *dist_base, gic_cpu_init(); gic_smp_init(); gic_cpu_pm_init(); + gic_syscore_init(); if (gic_dist_supports_lpis()) { its_init(handle, &gic_data.rdists, gic_data.domain); @@ -2092,7 +2222,11 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare redist_stride, &node->fwnode); if (err) goto out_unmap_rdist; - +#ifdef CONFIG_HIBERNATION + err = register_pm_notifier(&gic_notif_block); + if (err) + goto out_unmap_rdist; +#endif gic_populate_ppi_partitions(node); if (static_branch_likely(&supports_deactivate_key))