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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id y23-20020a1709027c9700b001619cebbad4sm989560pll.148.2022.05.18.01.18.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 May 2022 01:18:24 -0700 (PDT) From: Po-Kai Chi To: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Po-Kai Chi Subject: [PATCH] riscv: Invalid instruction cache after copy the xol area Date: Wed, 18 May 2022 16:17:53 +0800 Message-Id: <20220518081753.29589-1-po-kai.chi@sifive.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220518_011828_296643_F8D13C19 X-CRM114-Status: GOOD ( 11.01 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We need to invalid the relevant instruction cache after copying the xol area, to ensure the changes takes effect. Signed-off-by: Po-Kai Chi --- arch/riscv/kernel/probes/uprobes.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/probes/uprobes.c b/arch/riscv/kernel/probes/uprobes.c index 7a057b5f0adc..9d52beeac73c 100644 --- a/arch/riscv/kernel/probes/uprobes.c +++ b/arch/riscv/kernel/probes/uprobes.c @@ -165,6 +165,7 @@ void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr, /* Initialize the slot */ void *kaddr = kmap_atomic(page); void *dst = kaddr + (vaddr & ~PAGE_MASK); + unsigned long addr = (unsigned long)dst; memcpy(dst, src, len); @@ -177,10 +178,9 @@ void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr, kunmap_atomic(kaddr); /* - * We probably need flush_icache_user_page() but it needs vma. - * This should work on most of architectures by default. If - * architecture needs to do something different it can define - * its own version of the function. + * Flush both I/D cache to ensure instruction modification + * takes effect. */ flush_dcache_page(page); + flush_icache_range(addr, addr + len); }