From patchwork Wed May 18 11:33:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12853564 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6342DC433F5 for ; Wed, 18 May 2022 11:33:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BA7B389DD3; Wed, 18 May 2022 11:33:26 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5F2D88922F for ; Wed, 18 May 2022 11:33:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652873605; x=1684409605; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=meOkkwbpThdrMzcW5uVNAl7EsJMHv8duySpo/19eyY0=; b=kWLKdaa5u0xM68MEDCqlXV51wZ6VU20xVX7cebw8XBjJ11ZEVEV0cNgu 0N00WXY5OeOdEX0zCD1ckK9fHXaPvT2f7C+51v15Ubk0S9yT2x5juCmO9 YrqcHdPap1toFAZD3+dY6YAJtd68s1UnbScYT0UZHZCTt7BPe3L86HrAb 0/ES1tSH3+9LR6Y1G3OoHJCwyUnhz0lJfiX95yqploFdT6C66q0l6T3HO VAQvqqy/Lac8VWXZ4dSYW25MBEtGTR83UvriDR87tMaq1BRdTG/e9OMYo pabom4+Xrl06idL8BhrVtuHDtVolwbm5YhJO3K/jssZNoC3UlDIkiTlc5 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10350"; a="270452575" X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="270452575" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 04:33:23 -0700 X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="545409962" Received: from jwasiuki-mobl1.ger.corp.intel.com (HELO localhost) ([10.249.133.47]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 04:33:21 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Wed, 18 May 2022 14:33:14 +0300 Message-Id: <20220518113315.1305027-1-jani.nikula@intel.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 1/2] drm/i915/reg: fix undefined behavior due to shift overflowing the constant X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, Borislav Petkov , Randy Dunlap , Ruiqi GONG Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use REG_GENMASK() and REG_FIELD_PREP() to avoid errors due to -fsanitize=shift. References: https://lore.kernel.org/r/20220405151517.29753-12-bp@alien8.de Reported-by: Borislav Petkov Reported-by: Ruiqi GONG Cc: Randy Dunlap Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 321a08281a3f..dff3f88d8090 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7607,25 +7607,25 @@ enum skl_power_gate { #define _PORT_CLK_SEL_A 0x46100 #define _PORT_CLK_SEL_B 0x46104 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) -#define PORT_CLK_SEL_LCPLL_2700 (0 << 29) -#define PORT_CLK_SEL_LCPLL_1350 (1 << 29) -#define PORT_CLK_SEL_LCPLL_810 (2 << 29) -#define PORT_CLK_SEL_SPLL (3 << 29) -#define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29) -#define PORT_CLK_SEL_WRPLL1 (4 << 29) -#define PORT_CLK_SEL_WRPLL2 (5 << 29) -#define PORT_CLK_SEL_NONE (7 << 29) -#define PORT_CLK_SEL_MASK (7 << 29) +#define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) +#define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) +#define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) +#define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) +#define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) +#define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) +#define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) +#define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) +#define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) -#define DDI_CLK_SEL_NONE (0x0 << 28) -#define DDI_CLK_SEL_MG (0x8 << 28) -#define DDI_CLK_SEL_TBT_162 (0xC << 28) -#define DDI_CLK_SEL_TBT_270 (0xD << 28) -#define DDI_CLK_SEL_TBT_540 (0xE << 28) -#define DDI_CLK_SEL_TBT_810 (0xF << 28) -#define DDI_CLK_SEL_MASK (0xF << 28) +#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) +#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) +#define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) +#define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) +#define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) +#define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) +#define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) /* Transcoder clock selection */ #define _TRANS_CLK_SEL_A 0x46140 From patchwork Wed May 18 11:33:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12853565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 995C5C433EF for ; Wed, 18 May 2022 11:33:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C6DA610E07A; Wed, 18 May 2022 11:33:31 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1973010E07A for ; Wed, 18 May 2022 11:33:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652873610; x=1684409610; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5Km8N+uV+AaUsVtD57wv+Lb67wvB+pJZn5kXCN4xqwE=; b=Bdpn0hjXkCtOln45shosq1Zd3tBcm9KtcTLcfs5d0kzPlQEepjKIJ/5k Min0kDsMg5mZ+sU3U2OQgax4RRUq5gcMSuLA6uKCJtCgErVqTXC0Jn5e+ zbk7DqQh5cnlon6lMZUets1Xsv5ZzMC2eWseDL3Ct0Z+VltKTr/C7kzA5 guNU2RFmhpA3FjkwJiL65r22VvE3LeZRDXihiTtnI15UYccmQ6wZVWzdZ B02IgewGDeiBEiRLxro0kISijDUfwF4OjbKDg9DNcl2v5tBGgufydzCZ5 icjlrFwInV7Ech/Hi7b4xni6qmnc/h8Hv11wwbIekgq1+pIwQ76R9xc38 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10350"; a="251523798" X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="251523798" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 04:33:29 -0700 X-IronPort-AV: E=Sophos;i="5.91,234,1647327600"; d="scan'208";a="545410062" Received: from jwasiuki-mobl1.ger.corp.intel.com (HELO localhost) ([10.249.133.47]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2022 04:33:26 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Wed, 18 May 2022 14:33:15 +0300 Message-Id: <20220518113315.1305027-2-jani.nikula@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220518113315.1305027-1-jani.nikula@intel.com> References: <20220518113315.1305027-1-jani.nikula@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 2/2] drm/i915/uc: Fix undefined behavior due to shift overflowing the constant X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, Randy Dunlap , Ruiqi GONG , Borislav Petkov Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Borislav Petkov Fix: In file included from :0:0: drivers/gpu/drm/i915/gt/uc/intel_guc.c: In function ‘intel_guc_send_mmio’: ././include/linux/compiler_types.h:352:38: error: call to ‘__compiletime_assert_1047’ \ declared with attribute error: FIELD_PREP: mask is not constant _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) and other build errors due to shift overflowing values. See https://lore.kernel.org/r/YkwQ6%2BtIH8GQpuct@zn.tnic for the gory details as to why it triggers with older gccs only. v2 by Jani: - Drop the i915_reg.h changes Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Cc: Ruiqi GONG Cc: Randy Dunlap Signed-off-by: Borislav Petkov Signed-off-by: Jani Nikula Reviewed-by: Michal Wajdeczko --- drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 +- drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h | 2 +- drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h index be9ac47fa9d0..4ef9990ed7f8 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h @@ -50,7 +50,7 @@ #define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN (GUC_HXG_REQUEST_MSG_MIN_LEN + 3u) #define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0 -#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffff << 16) +#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffffU << 16) #define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN (0xffff << 0) #define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32 GUC_HXG_REQUEST_MSG_n_DATAn #define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64 GUC_HXG_REQUEST_MSG_n_DATAn diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h index c9086a600bce..df83c1cc7c7a 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h @@ -82,7 +82,7 @@ static_assert(sizeof(struct guc_ct_buffer_desc) == 64); #define GUC_CTB_HDR_LEN 1u #define GUC_CTB_MSG_MIN_LEN GUC_CTB_HDR_LEN #define GUC_CTB_MSG_MAX_LEN 256u -#define GUC_CTB_MSG_0_FENCE (0xffff << 16) +#define GUC_CTB_MSG_0_FENCE (0xffffU << 16) #define GUC_CTB_MSG_0_FORMAT (0xf << 12) #define GUC_CTB_FORMAT_HXG 0u #define GUC_CTB_MSG_0_RESERVED (0xf << 8) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h index 29ac823acd4c..7d5ba4d97d70 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h @@ -40,7 +40,7 @@ */ #define GUC_HXG_MSG_MIN_LEN 1u -#define GUC_HXG_MSG_0_ORIGIN (0x1 << 31) +#define GUC_HXG_MSG_0_ORIGIN (0x1U << 31) #define GUC_HXG_ORIGIN_HOST 0u #define GUC_HXG_ORIGIN_GUC 1u #define GUC_HXG_MSG_0_TYPE (0x7 << 28) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h index 2516705b9f36..8dc063f087eb 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h @@ -28,7 +28,7 @@ #define GS_MIA_HALT_REQUESTED (0x02 << GS_MIA_SHIFT) #define GS_MIA_ISR_ENTRY (0x04 << GS_MIA_SHIFT) #define GS_AUTH_STATUS_SHIFT 30 -#define GS_AUTH_STATUS_MASK (0x03 << GS_AUTH_STATUS_SHIFT) +#define GS_AUTH_STATUS_MASK (0x03U << GS_AUTH_STATUS_SHIFT) #define GS_AUTH_STATUS_BAD (0x01 << GS_AUTH_STATUS_SHIFT) #define GS_AUTH_STATUS_GOOD (0x02 << GS_AUTH_STATUS_SHIFT)