From patchwork Fri May 20 09:43:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 12856579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC975C433FE for ; Fri, 20 May 2022 09:44:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244446AbiETJn7 (ORCPT ); Fri, 20 May 2022 05:43:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347780AbiETJn4 (ORCPT ); Fri, 20 May 2022 05:43:56 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB913149AAF for ; Fri, 20 May 2022 02:43:55 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id bh5so6928374plb.6 for ; Fri, 20 May 2022 02:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N537kmXnIFF/B5MPYA58NfVjnsyjLkZ7UggoyVApuvw=; b=KC3c/8wyL3TWVMhL+5tSUJIk8jM4TdkimQNEt+YUcV/P3D4O9WrDmYeovQCEcsR1r5 XWSNKSVZ0WFawguQMabuNh3CoUu73KSTIFVsEoNKpo4D3eBbpFm0c9d9ubGLXmEXW5GW lQhnaIvUaUXAm8W1h0p1CQJLswQ7ZYLzUoC5w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N537kmXnIFF/B5MPYA58NfVjnsyjLkZ7UggoyVApuvw=; b=DmAFhWnclpsgSw/qyZwYoWZlTfgNB0ZadpVIbHRJJ1jqXXdcrjeb6xpzTdG2mFtagN PEOgG7z/J26WNNiNgehYW1vLp2ui6ufTiMiTuwEikMQU9CqRu7u85cH7FCuxDxZuJSqv FBHNj9KjXdaNDsYAFY18QCzo2lPoShoQMZUxgjbCYxStkPDPVzYwQ6Ctq418DzeqAlPc U3HE4BAQNDPoFUioxEJsmcYz47Kh0KQY3Cv0fJlTgcox/GREWUA3cbeFLYpmVXC8tnlM 194vWxecINc7mg4gb0isSfSIjVB0LqrchPqZKgyy1b5Tax9cUrRE/8Q40E21sVBdDRiM d3+w== X-Gm-Message-State: AOAM530PbNkhBosrHjxmIyKpyMq3qm9fnezc7mLZEyHzXH15BBm7iKzE SVbvI6SHUOISmKb4kyCTO69GHA== X-Google-Smtp-Source: ABdhPJx3Qh3cpJC+oik5Y71LHH8R8PjCzSbTcq79RW9UtXYQoOStcvHrjZaDjBr8UJjUlGm3KiM5lg== X-Received: by 2002:a17:90b:1e04:b0:1dc:9252:efbc with SMTP id pg4-20020a17090b1e0400b001dc9252efbcmr10148535pjb.39.1653039835451; Fri, 20 May 2022 02:43:55 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:ec49:9912:894:222d]) by smtp.gmail.com with ESMTPSA id 23-20020aa79217000000b0050dc76281bfsm1290597pfo.153.2022.05.20.02.43.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 May 2022 02:43:55 -0700 (PDT) From: Chen-Yu Tsai To: Michael Turquette , Stephen Boyd , Matthias Brugger Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Chun-Jie Chen , Miles Chen , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] arm64: dts: mt8183: Fix Mali GPU clock Date: Fri, 20 May 2022 17:43:20 +0800 Message-Id: <20220520094323.754971-2-wenst@chromium.org> X-Mailer: git-send-email 2.36.1.124.g0e6072fb45-goog In-Reply-To: <20220520094323.754971-1-wenst@chromium.org> References: <20220520094323.754971-1-wenst@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The actual clock feeding into the Mali GPU on the MT8183 is from the clock gate in the MFGCFG block, not CLK_TOP_MFGPLL_CK from the TOPCKGEN block, which itself is simply a pass-through placeholder for the MFGPLL in the APMIXEDSYS block. Fix the hardware description with the correct clock reference. Fixes: a8168cebf1bc ("arm64: dts: mt8183: Add node for the Mali GPU") Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 01e650251928..6ced76a60aab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1368,7 +1368,7 @@ gpu: gpu@13040000 { ; interrupt-names = "job", "mmu", "gpu"; - clocks = <&topckgen CLK_TOP_MFGPLL_CK>; + clocks = <&mfgcfg CLK_MFG_BG3D>; power-domains = <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, From patchwork Fri May 20 09:43:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 12856580 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3090BC4332F for ; Fri, 20 May 2022 09:44:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347888AbiETJoC (ORCPT ); Fri, 20 May 2022 05:44:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240410AbiETJn7 (ORCPT ); Fri, 20 May 2022 05:43:59 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC9FE14AA79 for ; Fri, 20 May 2022 02:43:58 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id gg20so7594564pjb.1 for ; Fri, 20 May 2022 02:43:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b4toybDv1M53GirTn8tpXa0Kt2GdamhkRh4OIAgDtc4=; b=WWvNjRlc9R3ylkT71F/0tYY4edxwlaAQp+Dvd7vVK/bnjQvRih4OUAVVzo1biCrAmn YkhIzbWoHtuygjdR112SzgAHPZOxtb/tDDeieVB2abJW58imdO1Eo9vL3NtIFG2nqgbw b1p6Sn1k7r4GowNho+ENI+EsKo91JVoN3LK/E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b4toybDv1M53GirTn8tpXa0Kt2GdamhkRh4OIAgDtc4=; b=EZgsva+VpjUjrTj9fZVsuqYEPoZ7ngynZPhYo07lBlQPT8ejAhnJDJYzgYqY1FUFol wlt9Pzapc8F6F6dFPKLHPME+W6F8jCgiq4kuK4QeY9nkSYy6USzzV6Yh5dw3rODibxm1 32RnO6MvA6nS7WkwpAp5ZYWapD7Xwhi18eUYlrtWOy4Qbrpr0VWPa7t/qUn5g1VmoDY4 vPSsOpOgKHlMK8+MjCXdi+0d2MyY1Gy9EQoOXPJdx0iuEpptoN/GFPrRW5jlhuv6Ovsg IPaRoU15BFb5nbP4oW7y89ZB6zltT0nT2kDNnLeAIaOIwbM80iZSaGw1AtusnCnLBkR8 xcnw== X-Gm-Message-State: AOAM531owiRP4xfwuY4vBwSSi64FRQXNmkaMGdKxOMAyrAxE/H46t8dp +hPQMmuYpVB9KFH/3KXnqwKTj2Y9JIrp5g== X-Google-Smtp-Source: ABdhPJwnbKiL/9EFkMezmfR/RGWpPtvvom3H3Yyp6HcfhsLZSqErmLrIH1CjIf5RMqWmmYanZhLuQA== X-Received: by 2002:a17:903:22c7:b0:161:cf2e:2ce2 with SMTP id y7-20020a17090322c700b00161cf2e2ce2mr8793814plg.59.1653039838197; Fri, 20 May 2022 02:43:58 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:ec49:9912:894:222d]) by smtp.gmail.com with ESMTPSA id 23-20020aa79217000000b0050dc76281bfsm1290597pfo.153.2022.05.20.02.43.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 May 2022 02:43:57 -0700 (PDT) From: Chen-Yu Tsai To: Michael Turquette , Stephen Boyd , Matthias Brugger Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Chun-Jie Chen , Miles Chen , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent Date: Fri, 20 May 2022 17:43:21 +0800 Message-Id: <20220520094323.754971-3-wenst@chromium.org> X-Mailer: git-send-email 2.36.1.124.g0e6072fb45-goog In-Reply-To: <20220520094323.754971-1-wenst@chromium.org> References: <20220520094323.754971-1-wenst@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its rate change requests to its parent, so that DVFS for the GPU can work properly. Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support") Signed-off-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c index d774edaf760b..230299728859 100644 --- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c @@ -18,9 +18,9 @@ static const struct mtk_gate_regs mfg_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_MFG(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \ - &mtk_clk_gate_ops_setclr) +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT) static const struct mtk_gate mfg_clks[] = { GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0) From patchwork Fri May 20 09:43:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 12856581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42A79C433EF for ; Fri, 20 May 2022 09:44:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347933AbiETJoV (ORCPT ); Fri, 20 May 2022 05:44:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347906AbiETJoM (ORCPT ); Fri, 20 May 2022 05:44:12 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8373714ACB1 for ; Fri, 20 May 2022 02:44:01 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id x143so7308143pfc.11 for ; Fri, 20 May 2022 02:44:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wYj0gPoFTJBwWJLt1P9KNSn0ODKjU0wkvs8hBSjSO3U=; b=ld8ZB0W0CyuE942AiXu7m9Pc6o1IzPm43tHOkNtsI9ja3+ZXuaz5Fsly3T/TPHc0qC yK669VzcVQuMW9FLnv0lGgD5gHPf1ru3oq88/XJN0uNcvMK8LxHYFhB6djP6naTFGtHJ JGWj6AJghQtC93LhJLnbHADNmKxzqBYvpUn18= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wYj0gPoFTJBwWJLt1P9KNSn0ODKjU0wkvs8hBSjSO3U=; b=KtwLc0JMjNLKx1pGgOAr+Ez4QpjNk9jIOsomSUaEtZzzlBPxTaUFX8UFNAJFOX5FXH jiaUollDQoW4aNUoVUBmD8FdCa5XWRjHAXbHlaYlqVgtTpgGHrtu5TiZiSQogtYPBBU/ GK02d0pvRDxF+uU8A08gY+cKo+TtzsaU8nHtBPY1Widv8+EGp5HstZnMeP1g8r8O5bJA 6tEWoUks6A/MyjebPKrrtAdLa4NSAkRdD5b2vG4HCrl24iRClXhyn8PR91Lg3FZ5TUIx TQRu6eEQ5DKZFI6ZDJFbjE00E7r1YPv9LuXWaJN7rjlCZeCzKXe9NFeR83qYDACNcjZ0 I19Q== X-Gm-Message-State: AOAM533fgDmHXpJUa2n8J2d10Z9NFOILiB35q8puDgaaqDgI0lsiJ0c0 BoFVfJBslNVkyERLs5qp0uNd9w== X-Google-Smtp-Source: ABdhPJziucUgkorNxj9E4BMmeKGpBafnohBlJChKVMYUEKtYijrw73Ok7dlvQG3idGaek2YoMaMHYw== X-Received: by 2002:a63:e655:0:b0:3c2:84a2:2ea0 with SMTP id p21-20020a63e655000000b003c284a22ea0mr7837735pgj.86.1653039841013; Fri, 20 May 2022 02:44:01 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:ec49:9912:894:222d]) by smtp.gmail.com with ESMTPSA id 23-20020aa79217000000b0050dc76281bfsm1290597pfo.153.2022.05.20.02.43.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 May 2022 02:44:00 -0700 (PDT) From: Chen-Yu Tsai To: Michael Turquette , Stephen Boyd , Matthias Brugger Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Chun-Jie Chen , Miles Chen , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] clk: mediatek: mux: add clk notifier functions Date: Fri, 20 May 2022 17:43:22 +0800 Message-Id: <20220520094323.754971-4-wenst@chromium.org> X-Mailer: git-send-email 2.36.1.124.g0e6072fb45-goog In-Reply-To: <20220520094323.754971-1-wenst@chromium.org> References: <20220520094323.754971-1-wenst@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org With device frequency scaling, the mux clock that (indirectly) feeds the device selects between a dedicated PLL, and some other stable clocks. When a clk rate change is requested, the (normally) upstream PLL is reconfigured. It's possible for the clock output of the PLL to become unstable during this process. To avoid causing the device to glitch, the mux should temporarily be switched over to another "stable" clock during the PLL rate change. This is done with clk notifiers. This patch adds common functions for notifiers to temporarily and transparently reparent mux clocks. This was loosely based on commit 8adfb08605a9 ("clk: sunxi-ng: mux: Add clk notifier functions"). Signed-off-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mux.c | 42 ++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-mux.h | 15 ++++++++++++ 2 files changed, 57 insertions(+) diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index cd5f9fd8cb98..f84a5a753c09 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -4,6 +4,7 @@ * Author: Owen Chen */ +#include #include #include #include @@ -259,4 +260,45 @@ void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num, } EXPORT_SYMBOL_GPL(mtk_clk_unregister_muxes); +/* + * This clock notifier is called when the frequency of the of the parent + * PLL clock is to be changed. The idea is to switch the parent to a + * stable clock, such as the main oscillator, while the PLL frequency + * stabilizes. + */ +static int mtk_clk_mux_notifier_cb(struct notifier_block *nb, + unsigned long event, void *_data) +{ + struct clk_notifier_data *data = _data; + struct mtk_mux_nb *mux_nb = to_mtk_mux_nb(nb); + const struct mtk_mux *mux = mux_nb->mux; + struct clk_hw *hw; + int ret = 0; + + hw = __clk_get_hw(data->clk); + + switch (event) { + case PRE_RATE_CHANGE: + mux_nb->original_index = mux->ops->get_parent(hw); + ret = mux->ops->set_parent(hw, mux_nb->bypass_index); + break; + + case POST_RATE_CHANGE: + case ABORT_RATE_CHANGE: + ret = mux->ops->set_parent(hw, mux_nb->original_index); + break; + } + + return notifier_from_errno(ret); +} + +int devm_mtk_clk_mux_notifier_register(struct device *dev, struct clk *clk, + struct mtk_mux_nb *mux_nb) +{ + mux_nb->nb.notifier_call = mtk_clk_mux_notifier_cb; + + return devm_clk_notifier_register(dev, clk, &mux_nb->nb); +} +EXPORT_SYMBOL_GPL(devm_mtk_clk_mux_notifier_register); + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h index 6539c58f5d7d..506e91125a3d 100644 --- a/drivers/clk/mediatek/clk-mux.h +++ b/drivers/clk/mediatek/clk-mux.h @@ -7,12 +7,14 @@ #ifndef __DRV_CLK_MTK_MUX_H #define __DRV_CLK_MTK_MUX_H +#include #include #include struct clk; struct clk_hw_onecell_data; struct clk_ops; +struct device; struct device_node; struct mtk_mux { @@ -89,4 +91,17 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes, void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num, struct clk_hw_onecell_data *clk_data); +struct mtk_mux_nb { + struct notifier_block nb; + const struct mtk_mux *mux; + + u8 bypass_index; /* Which parent to temporarily use */ + u8 original_index; /* Set by notifier callback */ +}; + +#define to_mtk_mux_nb(_nb) container_of(_nb, struct mtk_mux_nb, nb) + +int devm_mtk_clk_mux_notifier_register(struct device *dev, struct clk *clk, + struct mtk_mux_nb *mux_nb); + #endif /* __DRV_CLK_MTK_MUX_H */ From patchwork Fri May 20 09:43:23 2022 Content-Type: text/plain; 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Fri, 20 May 2022 02:44:03 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:ec49:9912:894:222d]) by smtp.gmail.com with ESMTPSA id 23-20020aa79217000000b0050dc76281bfsm1290597pfo.153.2022.05.20.02.44.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 May 2022 02:44:03 -0700 (PDT) From: Chen-Yu Tsai To: Michael Turquette , Stephen Boyd , Matthias Brugger Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Chun-Jie Chen , Miles Chen , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] clk: mediatek: mt8183: Add clk mux notifier for MFG mux Date: Fri, 20 May 2022 17:43:23 +0800 Message-Id: <20220520094323.754971-5-wenst@chromium.org> X-Mailer: git-send-email 2.36.1.124.g0e6072fb45-goog In-Reply-To: <20220520094323.754971-1-wenst@chromium.org> References: <20220520094323.754971-1-wenst@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org When the MFG PLL clock, which is upstream of the MFG clock, is changed, the downstream clock and consumers need to be switched away from the PLL over to a stable clock to avoid glitches. This is done through the use of the newly added clk mux notifier. The notifier is set on the mux itself instead of the upstream PLL, but in practice this works, as the rate change notifitcations are propogated throughout the sub-tree hanging off the PLL. Just before rate changes, the MFG mux is temporarily and transparently switched to the 26 MHz main crystal. After the rate change, the mux is switched back. Signed-off-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8183.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 8a755fadebb5..afef3738396e 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1192,6 +1192,8 @@ static int clk_mt8183_top_probe(struct platform_device *pdev) { void __iomem *base; struct device_node *node = pdev->dev.of_node; + struct mtk_mux_nb *mfg_mux_nb; + int i, ret; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -1217,6 +1219,25 @@ static int clk_mt8183_top_probe(struct platform_device *pdev) mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data); + /* Register mux notifier for MFG mux */ + mfg_mux_nb = devm_kzalloc(&pdev->dev, sizeof(*mfg_mux_nb), GFP_KERNEL); + if (!mfg_mux_nb) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(top_muxes); i++) + if (top_muxes[i].id == CLK_TOP_MUX_MFG) + break; + if (i == ARRAY_SIZE(top_muxes)) + return -EINVAL; + + mfg_mux_nb->mux = &top_muxes[i]; + mfg_mux_nb->bypass_index = 0; // Bypass to 26M crystal + ret = devm_mtk_clk_mux_notifier_register(&pdev->dev, + top_clk_data->hws[CLK_TOP_MUX_MFG]->clk, + mfg_mux_nb); + if (ret) + return ret; + return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); }