From patchwork Mon May 23 10:23:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Brugger X-Patchwork-Id: 12858768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 851F2C433FE for ; Mon, 23 May 2022 10:23:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233934AbiEWKX4 (ORCPT ); Mon, 23 May 2022 06:23:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233908AbiEWKXw (ORCPT ); Mon, 23 May 2022 06:23:52 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1AE941F9A; Mon, 23 May 2022 03:23:51 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5D9B8611E4; Mon, 23 May 2022 10:23:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 600D8C34119; Mon, 23 May 2022 10:23:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1653301430; bh=vUsnPjeIxXkyjg70eNAh8JZuEF/mFk5yfd2/sAihNms=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JfbsIsSyH3KzxP0Soh/5qiLLMFKa8ZgGOC5rI8NsETXsLEdTXaL5SqgQh0kpdIPJe SytazElEMl6XNx95MZY/Df16kjPyY5XuKoAdzXx+RSOqrUxwOK6oGR367FFhdpe6so Pdk2VHogUSWRUJcf1zLycF7pwjfb97f4fT5bupP/v1WweXd8iYwvqVMqxdojhpbgz9 PyukX45GlyPFwOnMJcjSJgTzeAOJ5eg8ACe0bYPJQ6G/pIniM3Xgn5GIziHsHYhGFb 2/OMJjDpBz16fgWoHqyG0eFWYiLbXR7nzW5nrMxMbIxLeIaDAQaVCXfxdeJI1HdnoZ TdGZ9cM8bU7fQ== From: matthias.bgg@kernel.org To: mturquette@baylibre.com, sboyd@kernel.org Cc: allen-kh.cheng@mediatek.com, weiyi.lu@mediatek.com, chun-jie.chen@mediatek.com, linux-kernel@vger.kernel.org, ikjn@chromium.org, miles.chen@mediatek.com, robh+dt@kernel.org, linux-mediatek@lists.infradead.org, krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com, Matthias Brugger , Krzysztof Kozlowski , devicetree@vger.kernel.org Subject: [PATCH v3 1/2] dt-bindings: ARM: Mediatek: Remove msdc binding of MT8192 clock Date: Mon, 23 May 2022 12:23:38 +0200 Message-Id: <20220523102339.21927-2-matthias.bgg@kernel.org> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220523102339.21927-1-matthias.bgg@kernel.org> References: <20220523102339.21927-1-matthias.bgg@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Matthias Brugger The code controlling msdc clock gate was moved inthe the consumer, the MMC driver. This node did never represent a working implementation of any peripheral. It was just a lonely clock gate that wasn't used. Delete the binding description of this node. Signed-off-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen Acked-by: Rob Herring --- Changes in v3: - Update commit message to explain better why we do ABI breakage here Changes in v2: - Delete compatible in binding descprition as well - Add RvB tags .../bindings/arm/mediatek/mediatek,mt8192-clock.yaml | 8 -------- 1 file changed, 8 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml index c8c67c033f8c..b57cc2e69efb 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml @@ -24,7 +24,6 @@ properties: - mediatek,mt8192-imp_iic_wrap_w - mediatek,mt8192-imp_iic_wrap_n - mediatek,mt8192-msdc_top - - mediatek,mt8192-msdc - mediatek,mt8192-mfgcfg - mediatek,mt8192-imgsys - mediatek,mt8192-imgsys2 @@ -107,13 +106,6 @@ examples: #clock-cells = <1>; }; - - | - msdc: clock-controller@11f60000 { - compatible = "mediatek,mt8192-msdc"; - reg = <0x11f60000 0x1000>; - #clock-cells = <1>; - }; - - | mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt8192-mfgcfg"; From patchwork Mon May 23 10:23:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Brugger X-Patchwork-Id: 12858769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F7EEC43217 for ; Mon, 23 May 2022 10:23:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234018AbiEWKX5 (ORCPT ); Mon, 23 May 2022 06:23:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233988AbiEWKX4 (ORCPT ); Mon, 23 May 2022 06:23:56 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 547DA403E8; Mon, 23 May 2022 03:23:55 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DCB9E611CA; Mon, 23 May 2022 10:23:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4A984C385A9; Mon, 23 May 2022 10:23:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1653301434; bh=y+sP4vTc6GXPb2q2jeON7sbrRR8FJJVBeRF9X7Rz+Fc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UMA00BlSIzMMi7wqj/fmwy8D9Uf5fSJz66AOEWfc6ECF219ZDuqs5y4UyrFMWJGpt bUq3+P4EZPrgf4v/7s/bwWxDaXoXZRBG6XzR5ngvrN6RvFIMSB35cxj6leENtOInIQ 4/I30rTjMIt8QCi4sAkpJUsk0ZMTurXC+wuF4HxtX6pEXUDHqChF3+LdDO3d0mxfao X1SFFs1RFIpIVhdrQB/Hhue0tMXZVI0ieCvqy8soIDAbkkOexpW/VAHhXITWzwQkK3 vkGWI089NJVKGFfKVRfhlcgBObeBawSRcnzcQDFBTae+h13N4A5oj7K2sWgi9G7bkv sc7bGflnzCPWw== From: matthias.bgg@kernel.org To: mturquette@baylibre.com, sboyd@kernel.org Cc: allen-kh.cheng@mediatek.com, weiyi.lu@mediatek.com, chun-jie.chen@mediatek.com, linux-kernel@vger.kernel.org, ikjn@chromium.org, miles.chen@mediatek.com, robh+dt@kernel.org, linux-mediatek@lists.infradead.org, krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com, Matthias Brugger Subject: [PATCH v3 2/2] clk: mediatek: Delete MT8192 msdc gate Date: Mon, 23 May 2022 12:23:39 +0200 Message-Id: <20220523102339.21927-3-matthias.bgg@kernel.org> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220523102339.21927-1-matthias.bgg@kernel.org> References: <20220523102339.21927-1-matthias.bgg@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Matthias Brugger The msdc gate is part of the MMC driver. Delete the not used code. Signed-off-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen --- Changes in v3: - add Reviewed-by tag Changes in v2: - add Reviewed-by tag drivers/clk/mediatek/clk-mt8192-msdc.c | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192-msdc.c b/drivers/clk/mediatek/clk-mt8192-msdc.c index 87c3b79b79cf..635f7a0b629a 100644 --- a/drivers/clk/mediatek/clk-mt8192-msdc.c +++ b/drivers/clk/mediatek/clk-mt8192-msdc.c @@ -12,28 +12,15 @@ #include -static const struct mtk_gate_regs msdc_cg_regs = { - .set_ofs = 0xb4, - .clr_ofs = 0xb4, - .sta_ofs = 0xb4, -}; - static const struct mtk_gate_regs msdc_top_cg_regs = { .set_ofs = 0x0, .clr_ofs = 0x0, .sta_ofs = 0x0, }; -#define GATE_MSDC(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &msdc_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) - #define GATE_MSDC_TOP(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) -static const struct mtk_gate msdc_clks[] = { - GATE_MSDC(CLK_MSDC_AXI_WRAP, "msdc_axi_wrap", "axi_sel", 22), -}; - static const struct mtk_gate msdc_top_clks[] = { GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p", "aes_msdcfde_sel", 0), GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p", "infra_msdc0_src", 1), @@ -52,11 +39,6 @@ static const struct mtk_gate msdc_top_clks[] = { GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi", "axi_sel", 14), }; -static const struct mtk_clk_desc msdc_desc = { - .clks = msdc_clks, - .num_clks = ARRAY_SIZE(msdc_clks), -}; - static const struct mtk_clk_desc msdc_top_desc = { .clks = msdc_top_clks, .num_clks = ARRAY_SIZE(msdc_top_clks), @@ -64,9 +46,6 @@ static const struct mtk_clk_desc msdc_top_desc = { static const struct of_device_id of_match_clk_mt8192_msdc[] = { { - .compatible = "mediatek,mt8192-msdc", - .data = &msdc_desc, - }, { .compatible = "mediatek,mt8192-msdc_top", .data = &msdc_top_desc, }, {