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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add new power domain for PL region. Signed-off-by: Nava kishore Manne Acked-by: Rob Herring --- Changes for v2: - None. include/dt-bindings/power/xlnx-zynqmp-power.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h index 0d9a412fd5e0..5f718759c38f 100644 --- a/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -35,5 +35,6 @@ #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 +#define PD_PL 69 #endif From patchwork Mon May 23 13:45:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12859096 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D769C433F5 for ; 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Signed-off-by: Nava kishore Manne Acked-by: Rob Herring --- Changes for v2: - Updated power-domains description. .../devicetree/bindings/fpga/fpga-region.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt index 7d3515264838..f299c3749505 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -196,6 +196,20 @@ Optional properties: - config-complete-timeout-us : The maximum time in microseconds time for the FPGA to go to operating mode after the region has been programmed. - child nodes : devices in the FPGA after programming. +- power-domains : A phandle and power domain specifier pair to the power domain + which is responsible for turning on/off the power to the FPGA/PL region. +Example: + fpga_full: fpga-full { + compatible = "fpga-region"; + fpga-mgr = <&zynqmp_pcap>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + power-domains = <&zynqmp_firmware PL_PD>; + }; + + The PL_PD power domain will be turned on before loading the bitstream +and turned off while removing/unloading the bitstream using overlays. In the example below, when an overlay is applied targeting fpga-region0, fpga_mgr is used to program the FPGA. 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(70586007)(70206006)(8676002)(356005)(6666004)(921005)(7696005)(6636002)(110136005)(508600001)(316002)(36860700001)(47076005)(426003)(336012)(186003)(40460700003)(83380400001)(26005)(2616005)(7636003)(1076003)(5660300002)(82310400005)(9786002)(8936002)(7416002)(2906002)(36756003)(102446001)(2101003)(83996005); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2022 13:45:56.3924 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e5547734-ee85-4cec-0f5e-08da3cc29011 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0026.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR02MB7750 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220523_064600_832592_7D987C29 X-CRM114-Status: GOOD ( 15.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support to handle FPGA/PL power domain. With this patch, the PL power domain will be turned on before loading the bitstream into the targeted region and turned off while removing/unloading the bitstream from the targeted region using overlays. This can be achieved by adding the runtime PM support to the fpga regions. Signed-off-by: Nava kishore Manne --- Changes for v2: - Updated commit message. - Updated runtime PM handling logic to fix the PM ref count imbalance issues. drivers/fpga/of-fpga-region.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c index ae82532fc127..f14bb5916d97 100644 --- a/drivers/fpga/of-fpga-region.c +++ b/drivers/fpga/of-fpga-region.c @@ -15,6 +15,7 @@ #include #include #include +#include static const struct of_device_id fpga_region_of_match[] = { { .compatible = "fpga-region", }, @@ -301,10 +302,17 @@ static int of_fpga_region_notify_pre_apply(struct fpga_region *region, return -EINVAL; } + ret = pm_runtime_resume_and_get(dev->parent); + if (ret < 0) { + fpga_image_info_free(info); + return ret; + } + region->info = info; ret = fpga_region_program_fpga(region); if (ret) { /* error; reject overlay */ + pm_runtime_put_sync(dev->parent); fpga_image_info_free(info); region->info = NULL; } @@ -324,10 +332,13 @@ static int of_fpga_region_notify_pre_apply(struct fpga_region *region, static void of_fpga_region_notify_post_remove(struct fpga_region *region, struct of_overlay_notify_data *nd) { + struct device *dev = ®ion->dev; + fpga_bridges_disable(®ion->bridge_list); fpga_bridges_put(®ion->bridge_list); fpga_image_info_free(region->info); region->info = NULL; + pm_runtime_put_sync(dev->parent); } /** @@ -411,6 +422,8 @@ static int of_fpga_region_probe(struct platform_device *pdev) goto eprobe_mgr_put; } + pm_runtime_enable(&pdev->dev); + of_platform_populate(np, fpga_region_of_match, NULL, ®ion->dev); platform_set_drvdata(pdev, region); @@ -430,6 +443,7 @@ static int of_fpga_region_remove(struct platform_device *pdev) fpga_region_unregister(region); fpga_mgr_put(mgr); + pm_runtime_disable(region->dev.parent); return 0; }