From patchwork Tue May 24 17:22:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 12860389 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E48BC433F5 for ; Tue, 24 May 2022 17:22:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234441AbiEXRWo (ORCPT ); Tue, 24 May 2022 13:22:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239933AbiEXRWo (ORCPT ); Tue, 24 May 2022 13:22:44 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C79517C17D; Tue, 24 May 2022 10:22:42 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,248,1647270000"; d="scan'208";a="120749712" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 25 May 2022 02:22:42 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 2D5E3400A8AA; Wed, 25 May 2022 02:22:36 +0900 (JST) From: Lad Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Sagar Kadam , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Phil Edworthy , Biju Das , Lad Prabhakar Subject: [PATCH RFC 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC Date: Tue, 24 May 2022 18:22:13 +0100 Message-Id: <20220524172214.5104-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220524172214.5104-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220524172214.5104-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Document Renesas RZ/Five (R9A07G043) SoC. Signed-off-by: Lad Prabhakar --- .../sifive,plic-1.0.0.yaml | 38 +++++++++++++++++-- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 27092c6a86c4..78ff31cb63e5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -28,7 +28,10 @@ description: While the PLIC supports both edge-triggered and level-triggered interrupts, interrupt handlers are oblivious to this distinction and therefore it is not - specified in the PLIC device-tree binding. + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's), + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need + to specify the interrupt type as the flow for EDGE interrupts is different + compared to LEVEL interrupts. While the RISC-V ISA doesn't specify a memory layout for the PLIC, the "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that @@ -57,6 +60,7 @@ properties: - enum: - allwinner,sun20i-d1-plic - const: thead,c900-plic + - const: renesas-r9a07g043-plic reg: maxItems: 1 @@ -64,8 +68,7 @@ properties: '#address-cells': const: 0 - '#interrupt-cells': - const: 1 + '#interrupt-cells': true interrupt-controller: true @@ -91,6 +94,35 @@ required: - interrupts-extended - riscv,ndev +if: + properties: + compatible: + contains: + const: renesas-r9a07g043-plic +then: + properties: + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#interrupt-cells': + const: 2 + + required: + - clocks + - resets + - power-domains + +else: + properties: + '#interrupt-cells': + const: 1 + additionalProperties: false examples: From patchwork Tue May 24 17:22:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 12860390 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78CFEC433EF for ; Tue, 24 May 2022 17:22:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239936AbiEXRWx (ORCPT ); Tue, 24 May 2022 13:22:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239937AbiEXRWw (ORCPT ); Tue, 24 May 2022 13:22:52 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C6B947DE0A; Tue, 24 May 2022 10:22:50 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,248,1647270000"; d="scan'208";a="122108004" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 25 May 2022 02:22:50 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 35404400A8AA; Wed, 25 May 2022 02:22:44 +0900 (JST) From: Lad Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Sagar Kadam , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Phil Edworthy , Biju Das , Lad Prabhakar Subject: [PATCH RFC 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Date: Tue, 24 May 2022 18:22:14 +0100 Message-Id: <20220524172214.5104-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220524172214.5104-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220524172214.5104-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt edge until the previous completion message has been received and NCEPLIC100 doesn't support pending interrupt counter, hence losing the interrupts if not acknowledged in time. So the workaround for edge-triggered interrupts to be handled correctly and without losing is that it needs to be acknowledged first and then handler must be run so that we don't miss on the next edge-triggered interrupt. This patch adds a new compatible string for Renesas RZ/Five SoC and adds support to change interrupt flow based on the interrupt type. It also implements irq_ack and irq_set_type callbacks. Signed-off-by: Lad Prabhakar --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-sifive-plic.c | 71 ++++++++++++++++++++++++++++++- 2 files changed, 70 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f3d071422f3b..aea0e4e7e547 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -537,6 +537,7 @@ config SIFIVE_PLIC bool "SiFive Platform-Level Interrupt Controller" depends on RISCV select IRQ_DOMAIN_HIERARCHY + select IRQ_FASTEOI_HIERARCHY_HANDLERS help This enables support for the PLIC chip found in SiFive (and potentially other) RISC-V systems. The PLIC controls devices diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index bb87e4c3b88e..abffce48e69c 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -60,10 +60,13 @@ #define PLIC_DISABLE_THRESHOLD 0x7 #define PLIC_ENABLE_THRESHOLD 0 +#define RENESAS_R9A07G043_PLIC 1 + struct plic_priv { struct cpumask lmask; struct irq_domain *irqdomain; void __iomem *regs; + u8 of_data; }; struct plic_handler { @@ -163,10 +166,31 @@ static int plic_set_affinity(struct irq_data *d, } #endif +static void plic_irq_ack(struct irq_data *d) +{ + struct plic_handler *handler = this_cpu_ptr(&plic_handlers); + + if (irqd_irq_masked(d)) { + plic_irq_unmask(d); + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); + plic_irq_mask(d); + } else { + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); + } +} + static void plic_irq_eoi(struct irq_data *d) { struct plic_handler *handler = this_cpu_ptr(&plic_handlers); + /* + * For Renesas R9A07G043 SoC if the interrupt type is EDGE + * we have already acknowledged it in ack callback. + */ + if (handler->priv->of_data == RENESAS_R9A07G043_PLIC && + !irqd_is_level_type(d)) + return; + if (irqd_irq_masked(d)) { plic_irq_unmask(d); writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); @@ -176,11 +200,37 @@ static void plic_irq_eoi(struct irq_data *d) } } +static int plic_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct plic_handler *handler = this_cpu_ptr(&plic_handlers); + + if (handler->priv->of_data != RENESAS_R9A07G043_PLIC) + return 0; + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + irq_set_handler_locked(d, handle_fasteoi_irq); + break; + + case IRQ_TYPE_EDGE_RISING: + irq_set_handler_locked(d, handle_fasteoi_ack_irq); + break; + + default: + return -EINVAL; + } + + return 0; +} + static struct irq_chip plic_chip = { .name = "SiFive PLIC", .irq_mask = plic_irq_mask, .irq_unmask = plic_irq_unmask, + .irq_ack = plic_irq_ack, .irq_eoi = plic_irq_eoi, + .irq_set_type = plic_irq_set_type, + #ifdef CONFIG_SMP .irq_set_affinity = plic_set_affinity, #endif @@ -198,6 +248,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, return 0; } +static int plic_irq_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct plic_priv *priv = d->host_data; + + if (priv->of_data == RENESAS_R9A07G043_PLIC) + return irq_domain_translate_twocell(d, fwspec, hwirq, type); + + return irq_domain_translate_onecell(d, fwspec, hwirq, type); +} + static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { @@ -206,7 +269,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int type; struct irq_fwspec *fwspec = arg; - ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type); if (ret) return ret; @@ -220,7 +283,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, } static const struct irq_domain_ops plic_irqdomain_ops = { - .translate = irq_domain_translate_onecell, + .translate = plic_irq_domain_translate, .alloc = plic_irq_domain_alloc, .free = irq_domain_free_irqs_top, }; @@ -293,6 +356,9 @@ static int __init plic_init(struct device_node *node, if (!priv) return -ENOMEM; + if (of_device_is_compatible(node, "renesas-r9a07g043-plic")) + priv->of_data = RENESAS_R9A07G043_PLIC; + priv->regs = of_iomap(node, 0); if (WARN_ON(!priv->regs)) { error = -EIO; @@ -411,5 +477,6 @@ static int __init plic_init(struct device_node *node, } IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); +IRQCHIP_DECLARE(renesas_r9a07g043_plic, "renesas-r9a07g043-plic", plic_init); IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */