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[66.90.144.107]) by smtp.googlemail.com with ESMTPSA id t16-20020a9d5910000000b00606aa4d5fcfsm6508340oth.29.2022.05.25.14.01.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 May 2022 14:01:23 -0700 (PDT) From: Rob Herring To: Kunihiko Hayashi , Bjorn Helgaas , Krzysztof Kozlowski , Masami Hiramatsu Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] dt-bindings: PCI: socionext,uniphier-pcie: Add missing child interrupt controller Date: Wed, 25 May 2022 16:01:16 -0500 Message-Id: <20220525210117.2489333-1-robh@kernel.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220525_140126_619007_4D4031C9 X-CRM114-Status: GOOD ( 12.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Socionext interrupt controller internal to the the PCI block isn't documented which causes warnings when unevaluatedProperties check is also fixed. Add the 'interrupt-controller' child node and properties and fixup the example so that interrupt properties can be parsed. Signed-off-by: Rob Herring Reviewed-by: Kunihiko Hayashi --- .../bindings/pci/socionext,uniphier-pcie.yaml | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml index f5926d0fb085..638b99db0433 100644 --- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml @@ -51,6 +51,19 @@ properties: phy-names: const: pcie-phy + interrupt-controller: + type: object + additionalProperties: false + + properties: + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + required: - compatible - reg @@ -62,6 +75,13 @@ unevaluatedProperties: false examples: - | + bus { + gic: interrupt-controller { + interrupt-controller; + #interrupt-cells = <3>; + }; + }; + pcie: pcie@66000000 { compatible = "socionext,uniphier-pcie"; reg-names = "dbi", "link", "config"; @@ -80,6 +100,7 @@ examples: phys = <&pcie_phy>; #interrupt-cells = <1>; interrupt-names = "dma", "msi"; + interrupt-parent = <&gic>; interrupts = <0 224 4>, <0 225 4>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc 0>, @@ -87,7 +108,7 @@ examples: <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; - pcie_intc: legacy-interrupt-controller { + pcie_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>;