From patchwork Thu May 26 05:58:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Virag X-Patchwork-Id: 12862001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A603C433FE for ; Thu, 26 May 2022 03:59:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345091AbiEZD7I (ORCPT ); Wed, 25 May 2022 23:59:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345052AbiEZD6v (ORCPT ); Wed, 25 May 2022 23:58:51 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29456C0383; Wed, 25 May 2022 20:58:50 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id j28so326155eda.13; Wed, 25 May 2022 20:58:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sGUo79V8IknEK9RaV+1rr5dfMkYi9KkvLOC/DC9705Q=; b=frTBXxzAzNw1OrGvbM+DJnEXiDhK6abfNuqcoFf6RXZBuVulVhnBMrxirE8v1dy1HN BT54dySSl0TSLpwqmsYoREhIDyA1y4nCE9JaGmr+hlPTZ/sjObzSkuqb6T0aQpZJ8ZQF r32y6L3rwSG09BLDG1lBr7eGDcS6HfNnvw8tB6Gd/G79mNU2qS3gg79xdNc+hNoHL1MD vG1s4xJjiZ9uiTkIZ96BtkUglGcW+lIb5zAAbqo7F3L+P8srUY6aZ6Vmk3HE7jlv/h2U hp6EuGYhY3nsR+gaAO30kja7je4iKTtwRHJ8q/fDTzASaiz4ZZVE1g9WQb0EWIyjYr5d Jp7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sGUo79V8IknEK9RaV+1rr5dfMkYi9KkvLOC/DC9705Q=; b=uqwQM297z6LhN8HS8bPI4gCSx1Tsq1tUfSzMMk2NPTIBeZD+PZEYoxuamZyHfVRpoV U0/IMtOrM8ZjWJBOXWvJlR47YrzemTorWflTvEFGQ3qeN+LB3dHg/tv5ZEUvbSQ7cl2X uDO+9lfMwmJLSZ+Kl6WjoOy32GHpGxP8cLEIFghMre4ZabBD07MD8DoP5PunD5Y5748Y w615a5mChkTZPc6Pwtti6SZy7nvEln6Bhs8phuTgPt7Oxzrr3HcPg4oU54RcsEFFy1F5 ocfvkOBLXV1zcVsr0MqmLoKXXqkXp+8SUucl+uNUWGM0TUdS+K0Vd1irtXpJl3BVn0V+ yZwg== X-Gm-Message-State: AOAM533+PEZHZonT5bODulHBN9inATzr0/ORTFJyzdYFvNEL5V+JBJ5+ YJlsTaNFXK2ZAEBZcytik94= X-Google-Smtp-Source: ABdhPJxUZkM4WISJm+sH+Os5S6DUAvBQ42HeFS0U92PtCs501xBQl3VhzcIgSaVFAEXnXvQHCp99HQ== X-Received: by 2002:a50:d7d7:0:b0:42b:d06c:33a with SMTP id m23-20020a50d7d7000000b0042bd06c033amr4235315edj.363.1653537528675; Wed, 25 May 2022 20:58:48 -0700 (PDT) Received: from localhost.localdomain ([2a02:ab88:368f:2080:5d6e:322:57b6:5f03]) by smtp.googlemail.com with ESMTPSA id c13-20020a50d64d000000b0042617ba63cfsm206621edj.89.2022.05.25.20.58.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 May 2022 20:58:48 -0700 (PDT) From: David Virag Cc: David Virag , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Sam Protsenko , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 1/2] clk: samsung: exynos7885: Correct "div4" clock parents Date: Thu, 26 May 2022 07:58:39 +0200 Message-Id: <20220526055840.45209-2-virag.david003@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220526055840.45209-1-virag.david003@gmail.com> References: <20220526055840.45209-1-virag.david003@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by 2 to achieve a by 4 division, thus their parents are the respective "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents. This leads to the kernel thinking "div4"s and everything under them run at 2x the clock speed. Fix this. Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver") Signed-off-by: David Virag Acked-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos7885.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c index a7b106302706..368c50badd15 100644 --- a/drivers/clk/samsung/clk-exynos7885.c +++ b/drivers/clk/samsung/clk-exynos7885.c @@ -182,7 +182,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), - DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll", + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3), @@ -190,7 +190,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), - DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll", + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), /* CORE */ From patchwork Thu May 26 05:58:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Virag X-Patchwork-Id: 12862002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05FB2C433EF for ; Thu, 26 May 2022 03:59:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345122AbiEZD7J (ORCPT ); Wed, 25 May 2022 23:59:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345080AbiEZD7I (ORCPT ); Wed, 25 May 2022 23:59:08 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A9E9C0384; Wed, 25 May 2022 20:58:51 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id f9so831812ejc.0; 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Wed, 25 May 2022 20:58:50 -0700 (PDT) Received: from localhost.localdomain ([2a02:ab88:368f:2080:5d6e:322:57b6:5f03]) by smtp.googlemail.com with ESMTPSA id c13-20020a50d64d000000b0042617ba63cfsm206621edj.89.2022.05.25.20.58.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 May 2022 20:58:49 -0700 (PDT) From: David Virag Cc: David Virag , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Sam Protsenko , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/2] arm64: dts: exynos: Correct UART clocks on Exynos7885 Date: Thu, 26 May 2022 07:58:40 +0200 Message-Id: <20220526055840.45209-3-virag.david003@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220526055840.45209-1-virag.david003@gmail.com> References: <20220526055840.45209-1-virag.david003@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The clocks in the serial UART nodes were swapped by mistake on Exynos7885. This only worked correctly because of a mistake in the clock driver which has been fixed. With the fixed clock driver in place, the baudrate of the UARTs get miscalculated. Fix this by correcting the clocks in the dtsi. Fixes: 06874015327b ("arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC") Signed-off-by: David Virag --- arch/arm64/boot/dts/exynos/exynos7885.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 3170661f5b67..9c233c56558c 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -280,8 +280,8 @@ serial_0: serial@13800000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart0_bus>; - clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>, - <&cmu_peri CLK_GOUT_UART0_PCLK>; + clocks = <&cmu_peri CLK_GOUT_UART0_PCLK>, + <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; status = "disabled"; @@ -293,8 +293,8 @@ serial_1: serial@13810000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart1_bus>; - clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>, - <&cmu_peri CLK_GOUT_UART1_PCLK>; + clocks = <&cmu_peri CLK_GOUT_UART1_PCLK>, + <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; status = "disabled"; @@ -306,8 +306,8 @@ serial_2: serial@13820000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart2_bus>; - clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>, - <&cmu_peri CLK_GOUT_UART2_PCLK>; + clocks = <&cmu_peri CLK_GOUT_UART2_PCLK>, + <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; status = "disabled";