From patchwork Fri May 27 08:58:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12863157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20FE4C43217 for ; Fri, 27 May 2022 08:58:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 20FDC10EB9C; Fri, 27 May 2022 08:58:46 +0000 (UTC) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1C46010E440; Fri, 27 May 2022 08:58:44 +0000 (UTC) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 14A3F61DA1; Fri, 27 May 2022 08:58:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 323BAC385A9; Fri, 27 May 2022 08:58:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1653641921; bh=zMEPRIvOxtolvSGdfKNn72JhOSa8qO+tUa865Q5G3/Y=; h=From:To:Cc:Subject:Date:From; b=rdMZQoOjHQst6A7c3TSCYMcgxXrNlvMsRL5cC3Va6gX1ySpnr3rFzdHu9491KTshy vBMX5vShoMgR/qyXD6nWh3iF/PI0jttJFAkEs/jEqlCCekkFGwHMDIMdCcKcxLIGRN 7OafZKxEHOD5VK3Zck6qmduMjDfoQMmysKxy9gz8j3kM9kRGiDyrfxbDFADjTSb7gu PO3Z7/OqvfiYYOk7lMwASYO3yF2c4BfVNtuGenzEfm5mZE4/Bx4lmPAXJ/BIdsjln8 DoUl4CNCnPJYhWVGckVHOet2PHH2oaxa4b8ZTrxJ8LbVUU7o6QH1h/4O23Ez85BFap z8H7f9IT4C2YA== Received: from mchehab by mail.kernel.org with local (Exim 4.95) (envelope-from ) id 1nuVnn-008Jvo-P8; Fri, 27 May 2022 10:58:35 +0200 From: Mauro Carvalho Chehab To: Daniel Vetter Subject: [PATCH] drm/i915: don't flush TLB on GEN8 Date: Fri, 27 May 2022 10:58:34 +0200 Message-Id: <8c1571f1a642c5c462da9f662aaab271756ca735.1653641899.git.mchehab@kernel.org> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio , Mauro Carvalho Chehab , Matthew Auld , Andi Shyti , Dave Airlie , Sushma Venkatesh Reddy , Jani Nikula , intel-gfx@lists.freedesktop.org, Lucas De Marchi , Rodrigo Vivi , Mauro Carvalho Chehab , Tvrtko Ursulin , mauro.chehab@linux.intel.com, Tvrtko Ursulin , linux-kernel@vger.kernel.org, stable@vger.kernel.org, Jon Bloomfield , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Mauro Carvalho Chehab i915 selftest hangcheck is causing the i915 driver timeouts, as reported by Intel CI: http://gfx-ci.fi.intel.com/cibuglog-ng/issuefilterassoc/24297?query_key=42a999f48fa6ecce068bc8126c069be7c31153b4 When such test runs, the only output is: [ 68.811639] i915: Performing live selftests with st_random_seed=0xe138eac7 st_timeout=500 [ 68.811792] i915: Running hangcheck [ 68.811859] i915: Running intel_hangcheck_live_selftests/igt_hang_sanitycheck [ 68.816910] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes [ 68.841597] i915: Running intel_hangcheck_live_selftests/igt_reset_nop [ 69.346347] igt_reset_nop: 80 resets [ 69.362695] i915: Running intel_hangcheck_live_selftests/igt_reset_nop_engine [ 69.863559] igt_reset_nop_engine(rcs0): 709 resets [ 70.364924] igt_reset_nop_engine(bcs0): 903 resets [ 70.866005] igt_reset_nop_engine(vcs0): 659 resets [ 71.367934] igt_reset_nop_engine(vcs1): 549 resets [ 71.869259] igt_reset_nop_engine(vecs0): 553 resets [ 71.882592] i915: Running intel_hangcheck_live_selftests/igt_reset_idle_engine [ 72.383554] rcs0: Completed 16605 idle resets [ 72.884599] bcs0: Completed 18641 idle resets [ 73.385592] vcs0: Completed 17517 idle resets [ 73.886658] vcs1: Completed 15474 idle resets [ 74.387600] vecs0: Completed 17983 idle resets [ 74.387667] i915: Running intel_hangcheck_live_selftests/igt_reset_active_engine [ 74.889017] rcs0: Completed 747 active resets [ 75.174240] intel_engine_reset(bcs0) failed, err:-110 [ 75.174301] bcs0: Completed 525 active resets After that, the machine just silently hangs. The root cause is that the flush TLB logic is not working as expected on GEN8. Tested on an Intel NUC5i7RYB with an i7-5557U Broadwell CPU. This patch partially reverts the logic by skipping GEN8 from the TLB cache flush. Cc: Tvrtko Ursulin Cc: Sushma Venkatesh Reddy Cc: Daniel Vetter Cc: Dave Airlie Cc: Jon Bloomfield Cc: Joonas Lahtinen Cc: Jani Nikula Cc: stable@vger.kernel.org # Kernel 5.17 and upper Fixes: 494c2c9b630e ("drm/i915: Flush TLBs before releasing backing store") Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Mauro Carvalho Chehab --- drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 034182f85501..7965a77e5046 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1191,10 +1191,10 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) if (GRAPHICS_VER(i915) == 12) { regs = gen12_regs; num = ARRAY_SIZE(gen12_regs); - } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) { + } else if (GRAPHICS_VER(i915) > 8 && GRAPHICS_VER(i915) <= 11) { regs = gen8_regs; num = ARRAY_SIZE(gen8_regs); - } else if (GRAPHICS_VER(i915) < 8) { + } else if (GRAPHICS_VER(i915) <= 8) { return; }