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x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?utf-8?q?f52p+6ySz38CSPaqbSaDJrMSuatD?= =?utf-8?q?jzT9wojDt51Oee/AJtCmza86Zh3P8z4PRfEKH9WpVEIR/ySMdKoKg0VvNwbzBPAkb?= =?utf-8?q?cwFMp8v9C9mPtY9XzKRt9ZUlPegoulEgKhxmc0WOkhVKFoc9bphm2coWAgPG5flW5?= =?utf-8?q?/8zjx2YQksSRCwpWapM/c/6CUpMTIConEXylwCAk5mFWPeEue5JV9Vcxq+iwOmVty?= =?utf-8?q?eRINUSv93vDxGnQq7H5i0MCK/VEm8jNVAlNt9xBMs2JRgFPi0dqBzPoCW6GLTvOGs?= =?utf-8?q?2GHlxZ+gJXFGAYiz6ns9C351f+arww76IWA+capr9uJd4WM/aY90Ef64obb6qjOoX?= =?utf-8?q?FP5rfLbbj03pvC8iaIgeaXMo9A7oEss3XE/XR+ZDVX5C/Su/0hyx/aFDJhqThMBPb?= =?utf-8?q?47a22/a8yoSW21N3UKRDkZrHaXtj9yxUpe8uevFiNU1CjgwyYIqrcF/7IB6jRtBtY?= =?utf-8?q?u7N3bQxDd7kKOQRPChKLOozMI/lbdQ+lvjbugDgn7yl0i+Qn9vKd+CcK3+22lzw9E?= =?utf-8?q?vLT37jsSK0GSLgnnO8R/JOqTBFGe0ihJn5dLArXACPEMLGcFBF4a2Sk42s+pVjaEQ?= =?utf-8?q?ykjkuQDZgzvravQ3vMUvAkhxdxDK+9tU0XeDn+Z925pkFiFTa++yhdE5wsAFRAF2J?= =?utf-8?q?uuQH1ac0Ta9iLTWTQIBrXkLrSu/Etf4x7J0ENCKxZ6Q/mmThwmghAAA+57SYjPgE/?= =?utf-8?q?Oktlw8zcp/jenYfmQ2d3/DjX7CzivZHv/omPkj6FeGRtra5RQ9+hfMhEKx++rfGTY?= =?utf-8?q?hja3wJdiSaa6/1KraiNLKnE+tgC7EKJbT4b+YPGI6+WDVbtmiQ6e4N5laEBgtDg5s?= =?utf-8?q?HJRJYdPg1QsDpP5AWhWV0dBIEkUfealCIjU3XqJkoK/wRkRAjQaW0dEd5K0nAInNS?= =?utf-8?q?XksQaTnLwWtAxNSpFYrnEyFvHiw1lFDU3Tni0ensVlVKwiNS4ZL8nqDQfJQH7K6oz?= =?utf-8?q?wRm6URKBYSi1nYyhZZzgyXkHb+o6MihGnhRPQEud/jll5MYUlbW6ZNRdv4J8mvuY7?= =?utf-8?q?OOyvr7+kjzFr6MLvzatJZdxb0vVm8LTJajyadxWH2q3nyBFo4beccX1HpNIBporMf?= =?utf-8?q?+NVFmn6S9tzpx7fRE9ZNXc8BXtpsESKUJ+2Sa7JLfIQJpaP5IbrS80Q7tKavft7K0?= =?utf-8?q?WfB16NDOiEoL2CFdeoBoVNpR6hRzLVGnD/92lLD3q/1U7SJOVvucNrMVE62ne4X1x?= =?utf-8?q?dIozTTc+f2BBLhBqFhiVxbWqu5zS2cDotkfRUKj4IPGGbpo1X6f0TqgsJPpUqr9Gg?= =?utf-8?q?hbQpTRRCwnvIZWWI8tk3MCuvfXn0iMoMnTyWO9O+Pawf6VYMdCngCDAnsONfkuXum?= =?utf-8?q?LQ6h9z8XQg9HBlCRblgNqJCSgigeKa71K0gKXQVJe0q9oclqeC16ZyskjG5UnYz2N?= =?utf-8?q?1JMbuldZz/DJS7Vh0BKVYQQGn0ihdopOemBZOTqm8va04cf941eXKJ9Wc0Lmzybcv?= =?utf-8?q?dqkykDgZQykX9DoMU0RA2K0+K+Sz3A9OyaRRXMC8SnYCX9a9OQPIe+fkKeblHoRnX?= =?utf-8?q?pKf2c9TPgVGj0e2OEWZw0PJDr+Cf1KEmCHSRARhM0S9p6eik4j22ALmSU5mJSktMa?= =?utf-8?q?l67tHdVR4F/QwdUdZg85L0HHKIgv9ycxRWlJGqpG2FnUTfOby2Wj4IaRGE8Rim9mZ?= =?utf-8?q?xeI+JhmReJua5Dl55hnMDbO6L9MM+yZQ=3D=3D?= Content-ID: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO1PR11MB5154.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4b160437-77ce-4e02-6db5-08da40107186 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 May 2022 18:40:59.4323 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hUKzlLyytZ5q8MilJ3rDTFlVEUyPjIzSysW6n62qGoLh+RnTaGZUmlVszkf2NGhkyuFY4e71NGGCKicxXHadpi5Som9/CbfkmT7tf7O6VAE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR11MB6213 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi Stephen, After I sent the fix for the broken resets in clk/microchip/clk-mpfs.c, [0] I started looking at making a proper reset controller driver a la clk/renesas/{renesas-cpg-mssr,rzgl2l-cpg}.c where the reset controller is part of the clock driver file. I did it that way b/c the reset controller is just a single reg, surrounded by registers used by clocks. It's roughly a +130,-10 line change to the existing driver. A /very/ rough version that will not apply without other cleanup is appended for context. Before I got around to testing properly and cleaning it up for submission, I saw a mail you had sent and wondered if I'd gone for the wrong approach [1]. Should I instead have my clock driver create a device for the reset controller to bind to, or is that overkill for a single register & Serge's situation is different b/c he'd created a file purely for a reset controller? Thanks, Conor. 0 - https://lore.kernel.org/linux-clk/20220411072340.740981-1-conor.dooley@microchip.com/ 1 - https://lore.kernel.org/linux-clk/20220517073729.2FAE2C385B8@smtp.kernel.org/ diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index ce3a48472fba..d9d1a4d9f131 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -29,7 +30,13 @@ #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u +#define MPFS_PERIPH_OFFSET 3u + struct mpfs_clock_data { + struct device *dev; +#ifdef CONFIG_RESET_CONTROLLER + struct reset_controller_dev rcdev; +#endif void __iomem *base; void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; @@ -344,10 +351,6 @@ static int mpfs_periph_clk_enable(struct clk_hw *hw) spin_lock_irqsave(&mpfs_clk_lock, flags); - reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - val = reg & ~(1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR); - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); val = reg | (1u << periph->shift); writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); @@ -381,12 +384,9 @@ static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) void __iomem *base_addr = periph_hw->base; u32 reg; - reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - if ((reg & (1u << periph->shift)) == 0u) { - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); - if (reg & (1u << periph->shift)) - return 1; - } + reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + if (reg & (1u << periph->shift)) + return 1; return 0; } @@ -472,6 +472,118 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c return 0; } +/* + * Peripheral clock resets + * + * CLK_RESERVED does not map to a clock, but it does map to a reset line, so it + * has to be accounted for here. + * + */ + +#ifdef CONFIG_RESET_CONTROLLER + +#define rcdev_to_clock_data(x) container_of((x), struct mpfs_clock_data, rcdev) + +// static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id) +// { +// struct mpfs_clock_data *clk_data = rcdev_to_clock_data(rcdev); +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// return 0; +// } + +static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct mpfs_clock_data *clk_data = rcdev_to_clock_data(rcdev); + u32 reg, val; + + reg = readl_relaxed(clk_data->base + REG_SUBBLK_RESET_CR); + val = reg | (1u << id); + writel_relaxed(val, clk_data->base + REG_SUBBLK_RESET_CR); + + dev_dbg(clk_data->dev, "deassert reset: %02lu\n", id); + return 0; +} + +static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct mpfs_clock_data *clk_data = rcdev_to_clock_data(rcdev); + u32 reg, val; + + reg = readl_relaxed(clk_data->base + REG_SUBBLK_RESET_CR); + val = reg & ~(1u << id); + writel_relaxed(val, clk_data->base + REG_SUBBLK_RESET_CR); + + dev_dbg(clk_data->dev, "deassert reset: %02lu\n", id); + + return 0; +} + +static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct mpfs_clock_data *clk_data = rcdev_to_clock_data(rcdev); + u32 reg; + + reg = readl_relaxed(clk_data->base + REG_SUBBLK_RESET_CR); + return (reg & (1u << id)); +} + + // .reset = mpfs_reset, +static const struct reset_control_ops mpfs_reset_ops = { + .assert = mpfs_assert, + .deassert = mpfs_deassert, + .status = mpfs_status, +}; + +//geert - does it make sense to reuse the clk_ indexes for the reset ctrlr? +// -> they run from 3 to 32 but skip one +//if yes, do i p much just subtract 3 in of_xlate & manipulate that bit? +static int mpfs_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + struct mpfs_clock_data *clk_data = rcdev_to_clock_data(rcdev); + unsigned int index = reset_spec->args[0]; + /* account for reserved fpga fabric reset */ + unsigned int num_resets = ARRAY_SIZE(mpfs_periph_clks) + 1; + + if (index < MPFS_PERIPH_OFFSET || index > (MPFS_PERIPH_OFFSET + num_resets)) { + dev_err(clk_data->dev, "Invalid reset index %u\n", reset_spec->args[0]); + return -EINVAL; + } + + return index - MPFS_PERIPH_OFFSET; +} +static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) +{ + clk_data->rcdev.ops = &mpfs_reset_ops; + clk_data->rcdev.of_node = clk_data->dev->of_node; + clk_data->rcdev.of_reset_n_cells = 1; + clk_data->rcdev.of_xlate = mpfs_reset_xlate; + /* CLK_RESERVED is not part of mpfs_periph_clks, so add 1 */ + clk_data->rcdev.nr_resets = ARRAY_SIZE(mpfs_periph_clks) + 1; + return devm_reset_controller_register(clk_data->dev, &clk_data->rcdev); +} + +#else /* !CONFIG_RESET_CONTROLLER */ +static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) +{ + return 0; +} +#endif /* !CONFIG_RESET_CONTROLLER */ + static int mpfs_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -496,6 +608,7 @@ static int mpfs_clk_probe(struct platform_device *pdev) return PTR_ERR(clk_data->msspll_base); clk_data->hw_data.num = num_clks; + clk_data->dev = dev; ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), clk_data); @@ -515,6 +628,10 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; + ret = mpfs_reset_controller_register(clk_data); + if (ret) + return ret; + return ret; }