From patchwork Sat May 28 20:46:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lev Kujawski X-Patchwork-Id: 12864094 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9431EC433EF for ; Sat, 28 May 2022 20:49:36 +0000 (UTC) Received: from localhost ([::1]:41894 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nv3NP-0005BO-HJ for qemu-devel@archiver.kernel.org; Sat, 28 May 2022 16:49:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nv3Lj-0002Wp-3V; Sat, 28 May 2022 16:47:51 -0400 Received: from mout-u-107.mailbox.org ([2001:67c:2050:101:465::107]:35138) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_CHACHA20_POLY1305:256) (Exim 4.90_1) (envelope-from ) id 1nv3La-0004x3-D7; Sat, 28 May 2022 16:47:50 -0400 Received: from smtp1.mailbox.org (smtp1.mailbox.org [10.196.197.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4L9Ydj4vzPz9sQM; Sat, 28 May 2022 22:47:37 +0200 (CEST) From: Lev Kujawski To: qemu-trival@nongnu.org Cc: Lev Kujawski , John Snow , qemu-block@nongnu.org (open list:IDE), qemu-devel@nongnu.org (open list:All patches CC here) Subject: [PATCH 1/4] hw/ide/atapi.c: Correct typos (CD-CDROM -> CD-ROM) Date: Sat, 28 May 2022 20:46:59 +0000 Message-Id: <20220528204702.167912-1-lkujaw@member.fsf.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:67c:2050:101:465::107; envelope-from=lkujaw@member.fsf.org; helo=mout-u-107.mailbox.org X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Lev Kujawski Reviewed-by: Philippe Mathieu-Daudé --- hw/ide/atapi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c index b626199e3d..88b2890faf 100644 --- a/hw/ide/atapi.c +++ b/hw/ide/atapi.c @@ -318,7 +318,7 @@ static void ide_atapi_cmd_reply(IDEState *s, int size, int max_size) } } -/* start a CD-CDROM read command */ +/* start a CD-ROM read command */ static void ide_atapi_cmd_read_pio(IDEState *s, int lba, int nb_sectors, int sector_size) { @@ -417,7 +417,7 @@ eot: ide_set_inactive(s, false); } -/* start a CD-CDROM read command with DMA */ +/* start a CD-ROM read command with DMA */ /* XXX: test if DMA is available */ static void ide_atapi_cmd_read_dma(IDEState *s, int lba, int nb_sectors, int sector_size) From patchwork Sat May 28 20:47:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lev Kujawski X-Patchwork-Id: 12864095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 642A6C433FE for ; Sat, 28 May 2022 20:49:37 +0000 (UTC) Received: from localhost ([::1]:41774 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nv3NQ-000571-AP for qemu-devel@archiver.kernel.org; Sat, 28 May 2022 16:49:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nv3Lp-0002jr-Kt; Sat, 28 May 2022 16:47:57 -0400 Received: from mout-u-107.mailbox.org ([91.198.250.252]:40906) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_CHACHA20_POLY1305:256) (Exim 4.90_1) (envelope-from ) id 1nv3Ln-0004yN-QI; Sat, 28 May 2022 16:47:57 -0400 Received: from smtp1.mailbox.org (smtp1.mailbox.org [IPv6:2001:67c:2050:b231:465::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4L9Ydz5M95z9sQM; Sat, 28 May 2022 22:47:51 +0200 (CEST) From: Lev Kujawski To: qemu-trival@nongnu.org Cc: Lev Kujawski , John Snow , qemu-block@nongnu.org (open list:IDE), qemu-devel@nongnu.org (open list:All patches CC here) Subject: [PATCH 2/4] hw/ide/core: Clear LBA and drive bits for EXECUTE DEVICE DIAGNOSTIC Date: Sat, 28 May 2022 20:47:00 +0000 Message-Id: <20220528204702.167912-2-lkujaw@member.fsf.org> In-Reply-To: <20220528204702.167912-1-lkujaw@member.fsf.org> References: <20220528204702.167912-1-lkujaw@member.fsf.org> MIME-Version: 1.0 X-Rspamd-Queue-Id: 4L9Ydz5M95z9sQM Received-SPF: pass client-ip=91.198.250.252; envelope-from=lkujaw@member.fsf.org; helo=mout-u-107.mailbox.org X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Prior to this patch, cmd_exec_dev_diagnostic relied upon ide_set_signature to clear the device register. While the preservation of the drive bit by ide_set_signature is necessary for the DEVICE RESET, IDENTIFY DEVICE, and READ SECTOR commands, ATA/ATAPI-6 specifies that "DEV shall be cleared to zero" for EXECUTE DEVICE DIAGNOSTIC. This deviation was uncovered by the ATACT Device Testing Program written by Hale Landis. Signed-off-by: Lev Kujawski --- hw/ide/core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/ide/core.c b/hw/ide/core.c index c2caa54285..5a24547e49 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -1704,8 +1704,14 @@ static bool cmd_identify_packet(IDEState *s, uint8_t cmd) return false; } +/* EXECUTE DEVICE DIAGNOSTIC */ static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd) { + /* + * Clear the device register per the ATA (v6) specification, + * because ide_set_signature does not clear LBA or drive bits. + */ + s->select = (ATA_DEV_ALWAYS_ON); ide_set_signature(s); if (s->drive_kind == IDE_CD) { From patchwork Sat May 28 20:47:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lev Kujawski X-Patchwork-Id: 12864097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72B2FC433EF for ; Sat, 28 May 2022 20:51:02 +0000 (UTC) Received: from localhost ([::1]:45000 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nv3On-0007HV-Je for qemu-devel@archiver.kernel.org; Sat, 28 May 2022 16:51:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40358) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nv3Lz-0003B9-Ga; Sat, 28 May 2022 16:48:07 -0400 Received: from mout-u-107.mailbox.org ([91.198.250.252]:40910) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_CHACHA20_POLY1305:256) (Exim 4.90_1) (envelope-from ) id 1nv3Lx-00050A-WA; Sat, 28 May 2022 16:48:07 -0400 Received: from smtp202.mailbox.org (smtp202.mailbox.org [IPv6:2001:67c:2050:b231:465::202]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4L9YfB2KPqz9sQM; Sat, 28 May 2022 22:48:02 +0200 (CEST) From: Lev Kujawski To: qemu-trival@nongnu.org Cc: Lev Kujawski , John Snow , qemu-block@nongnu.org (open list:IDE), qemu-devel@nongnu.org (open list:All patches CC here) Subject: [PATCH 3/4] piix_ide_reset: Use pci_set_* functions instead of direct access Date: Sat, 28 May 2022 20:47:01 +0000 Message-Id: <20220528204702.167912-3-lkujaw@member.fsf.org> In-Reply-To: <20220528204702.167912-1-lkujaw@member.fsf.org> References: <20220528204702.167912-1-lkujaw@member.fsf.org> MIME-Version: 1.0 X-Rspamd-Queue-Id: 4L9YfB2KPqz9sQM Received-SPF: pass client-ip=91.198.250.252; envelope-from=lkujaw@member.fsf.org; helo=mout-u-107.mailbox.org X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Eliminates the remaining TODOs in hw/ide/piix.c by: - Using pci_set_{size} functions to write the PIIX PCI configuration space instead of manipulating it directly as an array; and - Documenting default register values by reference to the controlling specification. Signed-off-by: Lev Kujawski Reviewed-by: Philippe Mathieu-Daudé --- hw/ide/piix.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/ide/piix.c b/hw/ide/piix.c index ce89fd0aa3..76ea8fd9f6 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -21,6 +21,10 @@ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. + * + * References: + * [1] 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR, + * 290550-002, Intel Corporation, April 1997. */ #include "qemu/osdep.h" @@ -114,14 +118,11 @@ static void piix_ide_reset(DeviceState *dev) ide_bus_reset(&d->bus[i]); } - /* TODO: this is the default. do not override. */ - pci_conf[PCI_COMMAND] = 0x00; - /* TODO: this is the default. do not override. */ - pci_conf[PCI_COMMAND + 1] = 0x00; - /* TODO: use pci_set_word */ - pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK; - pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8; - pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ + /* PCI command register default value (0000h) per [1, p.48]. */ + pci_set_word(pci_conf + PCI_COMMAND, 0x0000); + pci_set_word(pci_conf + PCI_STATUS, + PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK); + pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */ } static int pci_piix_init_ports(PCIIDEState *d) From patchwork Sat May 28 20:47:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lev Kujawski X-Patchwork-Id: 12864096 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09FFAC433EF for ; Sat, 28 May 2022 20:50:39 +0000 (UTC) Received: from localhost ([::1]:43842 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nv3OQ-0006Tf-0Y for qemu-devel@archiver.kernel.org; Sat, 28 May 2022 16:50:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nv3MJ-0003i4-GW; Sat, 28 May 2022 16:48:28 -0400 Received: from mout-u-107.mailbox.org ([2001:67c:2050:101:465::107]:35140) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_CHACHA20_POLY1305:256) (Exim 4.90_1) (envelope-from ) id 1nv3MH-00051a-VZ; Sat, 28 May 2022 16:48:27 -0400 Received: from smtp1.mailbox.org (smtp1.mailbox.org [10.196.197.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4L9YfZ3W8bz9sR0; Sat, 28 May 2022 22:48:22 +0200 (CEST) From: Lev Kujawski To: qemu-trival@nongnu.org Cc: Lev Kujawski , John Snow , qemu-block@nongnu.org (open list:IDE), qemu-devel@nongnu.org (open list:All patches CC here) Subject: [PATCH 4/4] hw/ide/piix: Ignore writes of hardwired PCI command register bits Date: Sat, 28 May 2022 20:47:02 +0000 Message-Id: <20220528204702.167912-4-lkujaw@member.fsf.org> In-Reply-To: <20220528204702.167912-1-lkujaw@member.fsf.org> References: <20220528204702.167912-1-lkujaw@member.fsf.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:67c:2050:101:465::107; envelope-from=lkujaw@member.fsf.org; helo=mout-u-107.mailbox.org X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" One method to enable PCI bus mastering for IDE controllers, often used by x86 firmware, is to write 0x7 to the PCI command register. Neither the PIIX3 specification nor actual hardware (a Tyan S1686D system) permit modification of the Memory Space Enable (MSE) bit, 1, and thus the command register would be left in an unspecified state without this patch. Signed-off-by: Lev Kujawski --- hw/ide/piix.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/hw/ide/piix.c b/hw/ide/piix.c index 76ea8fd9f6..f1d1168ecd 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -25,6 +25,8 @@ * References: * [1] 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR, * 290550-002, Intel Corporation, April 1997. + * [2] 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4), 290562-001, + * Intel Corporation, April 1997. */ #include "qemu/osdep.h" @@ -32,6 +34,7 @@ #include "migration/vmstate.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/range.h" #include "sysemu/block-backend.h" #include "sysemu/blockdev.h" #include "sysemu/dma.h" @@ -220,6 +223,26 @@ static void pci_piix_ide_exitfn(PCIDevice *dev) } } +static void piix_pci_config_write(PCIDevice *d, uint32_t addr, + uint32_t val, int l) +{ + /* + * Mask all IDE PCI command register bits except for Bus Master + * Function Enable (bit 2) and I/O Space Enable (bit 1), as the + * remainder are hardwired to 0 [1, p.48] [2, p.89-90]. + * + * NOTE: According to the PIIX3 datasheet [1], the Memory Space + * Enable (MSE bit) is hardwired to 1, but this is contradicted by + * actual PIIX3 hardware, the datasheet itself (viz., Default + * Value: 0000h), and the PIIX4 datasheet [2]. + */ + if (range_covers_byte(addr, l, PCI_COMMAND)) { + val &= ~(0xfffa << ((PCI_COMMAND - addr) << 3)); + } + + pci_default_write_config(d, addr, val, l); +} + /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ static void piix3_ide_class_init(ObjectClass *klass, void *data) { @@ -232,6 +255,7 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1; k->class_id = PCI_CLASS_STORAGE_IDE; + k->config_write = piix_pci_config_write; set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->hotpluggable = false; } @@ -260,6 +284,7 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371AB; k->class_id = PCI_CLASS_STORAGE_IDE; + k->config_write = piix_pci_config_write; set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->hotpluggable = false; }