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[217.237.121.196]) by smtp.gmail.com with ESMTPSA id g13-20020a5d64ed000000b002100e86319asm7341049wri.78.2022.05.29.11.40.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 May 2022 11:40:30 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum Subject: [PATCH v3 1/3] hw/i386/microvm-dt: Force explicit failure if retrieving QOM property fails Date: Sun, 29 May 2022 20:40:04 +0200 Message-Id: <20220529184006.10712-2-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220529184006.10712-1-shentey@gmail.com> References: <20220529184006.10712-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=shentey@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" New code will be added where this is best practice. So update existing code as well. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/microvm-dt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/i386/microvm-dt.c b/hw/i386/microvm-dt.c index 9c3c4995b4..fde74819f2 100644 --- a/hw/i386/microvm-dt.c +++ b/hw/i386/microvm-dt.c @@ -32,6 +32,7 @@ */ #include "qemu/osdep.h" #include "qemu/cutils.h" +#include "qapi/error.h" #include "sysemu/device_tree.h" #include "hw/char/serial.h" #include "hw/i386/fw_cfg.h" @@ -187,8 +188,8 @@ static void dt_add_ioapic(MicrovmMachineState *mms, SysBusDevice *dev) static void dt_add_isa_serial(MicrovmMachineState *mms, ISADevice *dev) { const char compat[] = "ns16550"; - uint32_t irq = object_property_get_int(OBJECT(dev), "irq", NULL); - hwaddr base = object_property_get_int(OBJECT(dev), "iobase", NULL); + uint32_t irq = object_property_get_int(OBJECT(dev), "irq", &error_fatal); + hwaddr base = object_property_get_int(OBJECT(dev), "iobase", &error_fatal); hwaddr size = 8; char *nodename; From patchwork Sun May 29 18:40:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12864233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D1BDC433F5 for ; Sun, 29 May 2022 18:41:51 +0000 (UTC) Received: from localhost ([::1]:53240 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nvNrK-0008Af-5H for qemu-devel@archiver.kernel.org; Sun, 29 May 2022 14:41:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvNq6-0006ay-Lw; Sun, 29 May 2022 14:40:35 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:46683) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nvNq5-0002G7-30; Sun, 29 May 2022 14:40:34 -0400 Received: by mail-wr1-x42e.google.com with SMTP id d26so6426823wrb.13; Sun, 29 May 2022 11:40:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Cov+lge9r84+pASXyK6paUlsnrkFtZeRPcnwvaSMtUY=; b=QC/0n0jWuNFEjA6GJfJnyBszRzWMQMTp0+cyFjhD1QMFnPUxNS7lejjy5+gxe1YAuC w+F3ys81DK3z/SvhRNVa8RgOn2yZtfkcU9Og7XbVGNKh3oLpCiYS3V0dY2vnQhbFfHBc 5JnFEqUQDHYoNwvL5+duZKnJwMRQcmKmclkU8cg2wU7wHCblLjM6axwsAIgPFiWMCMmu upUqKOyl45Xplo7u9TM8zut2Dy3TA0TdxoWt8+Pk5T1OCY458UmHQLMx6X8xWlh/pVPu ozNSTzYn9Q98Zykh/OHgwdMH3ALNshcutuakLmCWz4TMs6X5krIW4B6Lnw6AQG8EailM xmGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cov+lge9r84+pASXyK6paUlsnrkFtZeRPcnwvaSMtUY=; b=GDr8i0Fgx9ZR6tWCqEroYCkoUJrk9rrMNWXuNdn6VWMciUPZA6h9Dw/4xPk/pkY9u4 T2HXNLKsLyEyybVLIn0DiTBhvsoLRhj00t3vLgCxdhzETvucGQJeFWHlroRnSezShEHi nM4CeSIkovDGV1+tMeSPYcqS7/tgIdWjnGlxOiVc+SO+yIWiYN1wJGF6l2W6anNH6MqE aYJqavJG/hHVztyEMN0gt+k86jDdMO1ff8SY7qr+zADeBSQrcLrPeDXVXZqgXf4UtdOP Z8suARgL7dD7zbcM1qmSwvGy+eVUK/fc7dB5KNx5HkwzxleIrqfasu+pJzHE4S5ssgRz anHA== X-Gm-Message-State: AOAM5324ekXk1qCxjn1BA35W9HLlF64uPJ5cf4kjDl7wmrttur+7lcwN j3CFBjNGhiP8A2YtJGSIy6++6WxOu2iJ5SPc X-Google-Smtp-Source: ABdhPJyF+8W36m34tKnyLPNYszuTt/kp3KvReS+f4j5GE4AONrg6INOMJjSUuiQWzsdfBUtNO8lGSA== X-Received: by 2002:adf:f111:0:b0:210:313a:790b with SMTP id r17-20020adff111000000b00210313a790bmr2496148wro.367.1653849631236; Sun, 29 May 2022 11:40:31 -0700 (PDT) Received: from osoxes.fritz.box (pd9ed79c4.dip0.t-ipconnect.de. [217.237.121.196]) by smtp.gmail.com with ESMTPSA id g13-20020a5d64ed000000b002100e86319asm7341049wri.78.2022.05.29.11.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 May 2022 11:40:30 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Bernhard Beschow , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v3 2/3] hw/i386/microvm-dt: Determine mc146818rtc's IRQ number from QOM property Date: Sun, 29 May 2022 20:40:05 +0200 Message-Id: <20220529184006.10712-3-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220529184006.10712-1-shentey@gmail.com> References: <20220529184006.10712-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=shentey@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Since commit 3b004a16540aa41f2aa6a1ceb0bf306716766914 'hw/rtc/ mc146818rtc: QOM'ify IRQ number' mc146818rtc's IRQ number is configurable. Fix microvm-dt to respect its value. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/microvm-dt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/microvm-dt.c b/hw/i386/microvm-dt.c index fde74819f2..287818c641 100644 --- a/hw/i386/microvm-dt.c +++ b/hw/i386/microvm-dt.c @@ -209,7 +209,7 @@ static void dt_add_isa_serial(MicrovmMachineState *mms, ISADevice *dev) static void dt_add_isa_rtc(MicrovmMachineState *mms, ISADevice *dev) { const char compat[] = "motorola,mc146818"; - uint32_t irq = RTC_ISA_IRQ; + uint32_t irq = object_property_get_uint(OBJECT(dev), "irq", &error_fatal); hwaddr base = RTC_ISA_BASE; hwaddr size = 8; char *nodename; From patchwork Sun May 29 18:40:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12864236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBD8AC433F5 for ; Sun, 29 May 2022 18:46:40 +0000 (UTC) Received: from localhost ([::1]:59426 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nvNw0-00043D-0e for qemu-devel@archiver.kernel.org; Sun, 29 May 2022 14:46:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvNq7-0006b4-O7; Sun, 29 May 2022 14:40:35 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:44929) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nvNq6-0002GU-47; Sun, 29 May 2022 14:40:35 -0400 Received: by mail-wr1-x430.google.com with SMTP id e25so1407064wra.11; Sun, 29 May 2022 11:40:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6HztDJBzf0Fp93vOy8s8PCk7aEO7ZIXWGwPqPqGSnVI=; b=n+r5zsoMkA2VBM/JHXzix9H1JrPIjwGyaoggXxwzVDrOUt+YfqO6+WAtlEAjRH0kOf 075p0QA5Wi9Ws7OjCSD4CP3GygnOHDJrEF5uwdkRyGNgj/85PNSKV3lBG4r+rGX2eSyI 1bMiNpIXiDNzn0oS5LNidT95pNcHolL7gC3WWDkV3lJKEvG1fg09RIetiDgvdP0IK5ln b0ZLqikMlLjAClXEfNllvDzGWeb5/d08+mkyyShephru5Oq+xrlf0Fhq3O5OxGSzI0wD 5az1OgG7y0uSUwQ8kk3xvKZJaoOKhjFJMURW1LjlZTUA31AFvEpkcwQedGKmyDJVL81O bM+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6HztDJBzf0Fp93vOy8s8PCk7aEO7ZIXWGwPqPqGSnVI=; b=s/nE8/OiPOsf1p1kvWOkOqRcSLc+Mp6MSdSPOb/Z0JCM6gxvMn2rxyh//WxSOXYoMo 4/3sch+TfXr0GL1lAbSj2CHtnz9Lnl4eu0ke/wqc923LVdz/my+Xw01kFva5TPyU0d0m XMpUBT4vTZgYhUteVJP0DX4QhnXYqG+bTjwyS8oM1H04AsDrezbWAeOq+Ad9XLY6gzsq HvfN+Mc7ggCR1m8xOacd0YNrCcPKGpX4PZwRwy1SmQT/XckxSG1KRVOU32xp29lXu2Tl zgndy4Ku3DXTFQNVu076ljKB8h791/wgPHcFNs57tmgi8xkFigWUyYqUEOc3KZHhbIZy vpow== X-Gm-Message-State: AOAM533GH1oh5j5xQRIr7kD9sCzw/ykBW2FunNpjOmTdOjrfXKDYGU23 XNRrGOdrehaQBsE3GB998affk9VyA/4g4b1S X-Google-Smtp-Source: ABdhPJyRW8Xty5Fa7nezA5eIZQx/lUnuy3WP1gCaAdlOdA5Q5w/dl0d1dV3WtSJ8W7M0UXze91j6UA== X-Received: by 2002:adf:9cc2:0:b0:20f:e59a:ec41 with SMTP id h2-20020adf9cc2000000b0020fe59aec41mr26732038wre.124.1653849632255; Sun, 29 May 2022 11:40:32 -0700 (PDT) Received: from osoxes.fritz.box (pd9ed79c4.dip0.t-ipconnect.de. [217.237.121.196]) by smtp.gmail.com with ESMTPSA id g13-20020a5d64ed000000b002100e86319asm7341049wri.78.2022.05.29.11.40.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 May 2022 11:40:32 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Bernhard Beschow , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum Subject: [PATCH v3 3/3] rtc/mc146818rtc: QOM'ify io_base offset Date: Sun, 29 May 2022 20:40:06 +0200 Message-Id: <20220529184006.10712-4-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220529184006.10712-1-shentey@gmail.com> References: <20220529184006.10712-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=shentey@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Exposing the io_base offset as a QOM property not only allows it to be configurable but also to be displayed in HMP: Before: (qemu) info qtree ... dev: mc146818rtc, id "" gpio-out "" 1 base_year = 0 (0x0) irq = 8 (0x8) lost_tick_policy = "discard" After: dev: mc146818rtc, id "" gpio-out "" 1 base_year = 0 (0x0) iobase = 112 (0x70) irq = 8 (0x8) lost_tick_policy = "discard" Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/microvm-dt.c | 2 +- hw/rtc/mc146818rtc.c | 9 ++++++--- include/hw/rtc/mc146818rtc.h | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/i386/microvm-dt.c b/hw/i386/microvm-dt.c index 287818c641..b3049e4f9f 100644 --- a/hw/i386/microvm-dt.c +++ b/hw/i386/microvm-dt.c @@ -210,7 +210,7 @@ static void dt_add_isa_rtc(MicrovmMachineState *mms, ISADevice *dev) { const char compat[] = "motorola,mc146818"; uint32_t irq = object_property_get_uint(OBJECT(dev), "irq", &error_fatal); - hwaddr base = RTC_ISA_BASE; + hwaddr base = object_property_get_uint(OBJECT(dev), "iobase", &error_fatal); hwaddr size = 8; char *nodename; diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index f235c2ddbe..5f458a881e 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -74,6 +74,8 @@ #define RTC_CLOCK_RATE 32768 #define UIP_HOLD_LENGTH (8 * NANOSECONDS_PER_SECOND / 32768) +#define RTC_ISA_BASE 0x70 + static void rtc_set_time(RTCState *s); static void rtc_update_time(RTCState *s); static void rtc_set_cmos(RTCState *s, const struct tm *tm); @@ -941,7 +943,7 @@ static void rtc_realizefn(DeviceState *dev, Error **errp) qemu_register_suspend_notifier(&s->suspend_notifier); memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2); - isa_register_ioport(isadev, &s->io, RTC_ISA_BASE); + isa_register_ioport(isadev, &s->io, s->io_base); /* register rtc 0x70 port for coalesced_pio */ memory_region_set_flush_coalesced(&s->io); @@ -950,7 +952,7 @@ static void rtc_realizefn(DeviceState *dev, Error **errp) memory_region_add_subregion(&s->io, 0, &s->coalesced_io); memory_region_add_coalescing(&s->coalesced_io, 0, 1); - qdev_set_legacy_instance_id(dev, RTC_ISA_BASE, 3); + qdev_set_legacy_instance_id(dev, s->io_base, 3); object_property_add_tm(OBJECT(s), "date", rtc_get_date); @@ -983,6 +985,7 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq) static Property mc146818rtc_properties[] = { DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), + DEFINE_PROP_UINT16("iobase", RTCState, io_base, RTC_ISA_BASE), DEFINE_PROP_UINT8("irq", RTCState, isairq, RTC_ISA_IRQ), DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState, lost_tick_policy, LOST_TICK_POLICY_DISCARD), @@ -1028,7 +1031,7 @@ static void rtc_build_aml(ISADevice *isadev, Aml *scope) * does, even though qemu only responds to the first two ports. */ crs = aml_resource_template(); - aml_append(crs, aml_io(AML_DECODE16, RTC_ISA_BASE, RTC_ISA_BASE, + aml_append(crs, aml_io(AML_DECODE16, s->io_base, s->io_base, 0x01, 0x08)); aml_append(crs, aml_irq_no_flags(s->isairq)); diff --git a/include/hw/rtc/mc146818rtc.h b/include/hw/rtc/mc146818rtc.h index 33d85753c0..1db0fcee92 100644 --- a/include/hw/rtc/mc146818rtc.h +++ b/include/hw/rtc/mc146818rtc.h @@ -26,6 +26,7 @@ struct RTCState { uint8_t cmos_data[128]; uint8_t cmos_index; uint8_t isairq; + uint16_t io_base; int32_t base_year; uint64_t base_rtc; uint64_t last_update; @@ -49,7 +50,6 @@ struct RTCState { }; #define RTC_ISA_IRQ 8 -#define RTC_ISA_BASE 0x70 ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq);