From patchwork Wed Jun 1 02:22:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 12866306 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19375C433FE for ; Wed, 1 Jun 2022 02:23:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id DA402C34114; Wed, 1 Jun 2022 02:23:08 +0000 (UTC) Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id E50ADC385A9 for ; Wed, 1 Jun 2022 02:23:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org E50ADC385A9 Authentication-Results: smtp.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.kernel.org; spf=fail smtp.mailfrom=broadcom.com Received: by mail-pj1-f51.google.com with SMTP id l7-20020a17090aaa8700b001dd1a5b9965so688100pjq.2 for ; Tue, 31 May 2022 19:23:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=ngZwjq45tM7azpd6oPc/h1R+M5f0JzyBZc1rQz+1yCQ=; b=O3l8v1c0GLb7TL6+UW1AFXqEdgJt8uhYF7uK2f/XPTp24vQjSRM0tMMwFtDTYbXMoW gx6PKqR2qWPlaeZxn+1EI80IVC9RlHrZcSEthOv3BXGuzBcjjkaH+Tj9kZ+8qzE6TUmL pKZGP1IAEqd8gQIcqVbG2N37y9HLXO/rLx1mg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=ngZwjq45tM7azpd6oPc/h1R+M5f0JzyBZc1rQz+1yCQ=; b=7EkS2p9v950D2yj2jXyxv3bBoMxjs4io1IXEx1R5h+0HcYhskAndpCcbrQPJ8yHLO6 su24O+2D5sqenL7+qsaYwdY2FnMH5ur/zMbbksbH9ebnMQs+muk3tDIR5o+Mxrk3f6mn 2xcE2pVIFQP2nlxtSqQPUyfXbWcYmHNYCMjGiMi08BCjmwhUAfLpnywg7cBqMnZ9V2zI wqopb4JD7smXIYg8WCtnKYrA0rDyFHkpRaoEolVPBDjdfgk44rtpe6qDQqc127BSJuYx Ftfg5DTjavH4YICW8++8SY26IXqscOj8cRYFOnNQEvXMan1Xpad6chkTs/OOMCFocd8v UEbA== X-Gm-Message-State: AOAM530FSb6H0PNm15wT6bzJx1ciymyzQtN+JfaP6uFpPQ70sfdyQvJO eFcxVpCL+uXIcyuM8PM+L/HvKw== X-Google-Smtp-Source: ABdhPJyVQ6BqRjO2+eKFo69VmqoB1DX6OTBsxsQd9r7b+eZsy8UYi5iI7eTY0iz6DFs/x08U3RGPZg== X-Received: by 2002:a17:90a:fe8f:b0:1e3:1dcd:7f94 with SMTP id co15-20020a17090afe8f00b001e31dcd7f94mr10568867pjb.23.1654050187319; Tue, 31 May 2022 19:23:07 -0700 (PDT) Received: from T3500-3.dhcp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id v24-20020a634658000000b003fad46ceb85sm157824pgk.7.2022.05.31.19.23.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 19:23:06 -0700 (PDT) From: William Zhang To: Linux ARM List List-Id: Cc: anand.gore@broadcom.com, dan.beygelman@broadcom.com, florian.fainelli@broadcom.com, joel.peshkin@broadcom.com, tomer.yacoby@broadcom.com, kursad.oney@broadcom.com, samyon.furman@broadcom.com, philippe.reynes@softathome.com, William Zhang , Arnd Bergmann , Broadcom internal kernel review list , Krzysztof Kozlowski , Olof Johansson , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org Subject: [PATCH v3 2/3] ARM: dts: add dts files for bcmbca SoC bcm6846 Date: Tue, 31 May 2022 19:22:12 -0700 Message-Id: <20220601022215.32494-3-william.zhang@broadcom.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220601022215.32494-1-william.zhang@broadcom.com> References: <20220601022215.32494-1-william.zhang@broadcom.com> MIME-Version: 1.0 Add dts for ARMv7 based broadband SoC BCM6846. bcm6846.dtsi is the SoC description dts header and bcm96846.dts is a simple dts file for Broadcom BCM96846 Reference board that only enable the UART port. Signed-off-by: William Zhang --- Changes in v3: - Fix timer PPI interrupt cpu mask for dual core cpu - Remove unnecessary cpu_on and cpu_off properties from psci node - Add the missing gic registers and interrupts property to gic node arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/bcm6846.dtsi | 103 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm96846.dts | 30 ++++++++++ 3 files changed, 135 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/bcm6846.dtsi create mode 100644 arch/arm/boot/dts/bcm96846.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 03f5b3a15415..2f20dcf74858 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -182,7 +182,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb dtb-$(CONFIG_ARCH_BCMBCA) += \ - bcm947622.dtb + bcm947622.dtb \ + bcm96846.dtb dtb-$(CONFIG_ARCH_CLPS711X) += \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi new file mode 100644 index 000000000000..8aa47a2583b2 --- /dev/null +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm6846", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x1b>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm96846.dts b/arch/arm/boot/dts/bcm96846.dts new file mode 100644 index 000000000000..c70ebccabc19 --- /dev/null +++ b/arch/arm/boot/dts/bcm96846.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6846.dtsi" + +/ { + model = "Broadcom BCM96846 Reference Board"; + compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +};