From patchwork Wed Jun 1 03:19:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12866312 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FC75C433EF for ; Wed, 1 Jun 2022 03:19:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349285AbiFADTh (ORCPT ); Tue, 31 May 2022 23:19:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241329AbiFADTc (ORCPT ); Tue, 31 May 2022 23:19:32 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F17598B0A7; Tue, 31 May 2022 20:19:30 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id n13-20020a17090a394d00b001e30a60f82dso4826167pjf.5; Tue, 31 May 2022 20:19:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=sKgI1HXiOEQjCz4KL5/iiLkMDmHzaI43i9dEIs2R6Zw=; b=X2Hndi0YvAZG4nN2Dl8+vVDx1DqrFowIsK7MD1rwsCZpj9ZL+wKlTD8KG59KXzPM0Q h2sy8Nf/EcYbfOl/AQ+8QLx2Gxkc6b7FRjYagm3D07AYLvNcA/k2W5r9u00EVInGfk8v tcWNQCbPYEZWE/fH+IWk8DN1MluXLhPTqK+06ACEhDx34fS1soK3XU6lYeZmQ7zpjDXg cYRnAY4D18rcpsSTKz9ExFrsYYJ1172J9jBeQ15qv2RUXcE8oQZKraVMJjEf+NI1/0L+ s8cE2U38sKa6JeVC6vdhZJo8nYoTdIUkOAlNv6wQeskkLdi5J1fEfwjiIovmU9dNApW3 6lbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=sKgI1HXiOEQjCz4KL5/iiLkMDmHzaI43i9dEIs2R6Zw=; b=6m+UCjxcbkJ0Zueo7tFjO3Fwf1+3t6Tvc0rgWO5kfekuYkZpF2myiMZX6lkL7/nFSD UHJ70+Z/uoyeYM1ouJBQLNbxem8LWVvdTwxNEl07M21FpgUQq5Gsleuk4z1thFZhWc5D Rs4TSPRLI/KurXEbJ9NCBloGQSx3vm/EGLesflQIeWeCFcdTvGG+K8PO3plIen1UDhoO hLqdlt2XCO+BNjo3Fh97XR+x4JQWw+6R10MjNkV9VxUGOeyIfYgAvOq+d1Zliz2t9D5y ZfGJ+xIa35R6jwIyEWEXW7H/QdegGGuWBeM1zhfFas5DLS45vaGn2OyWZpY3OKR5RO7w W+9g== X-Gm-Message-State: AOAM531jPQPpsoaFNcdQIFRRRBy2uXnbTXUZLcCHPlpa3uqs5B3cI5IY t1nbD1z9x6+Bu4c7yzMZYQI= X-Google-Smtp-Source: ABdhPJzldhxLu11cxwB2qP3x3UP18xW+MjJxmw4zBf2NdyVYkmoE12xWq8wIQGbpJ50NYA0DOT/uDA== X-Received: by 2002:a17:902:d58a:b0:164:f5d1:82e9 with SMTP id k10-20020a170902d58a00b00164f5d182e9mr2027183plh.3.1654053570422; Tue, 31 May 2022 20:19:30 -0700 (PDT) Received: from localhost.localdomain ([203.205.141.23]) by smtp.gmail.com with ESMTPSA id i13-20020a056a00004d00b0050dc76281d3sm184691pfk.173.2022.05.31.20.19.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 20:19:29 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Sean Christopherson , Wanpeng Li Cc: Vitaly Kuznetsov , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] KVM: x86/pmu: Accept 0 for absent PMU MSRs when host-initiated if !enable_pmu Date: Wed, 1 Jun 2022 11:19:23 +0800 Message-Id: <20220601031925.59693-1-likexu@tencent.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Whenever an MSR is part of KVM_GET_MSR_INDEX_LIST, as is the case for MSR_K7_EVNTSEL0 or MSR_F15H_PERF_CTL0, it has to be always retrievable and settable with KVM_GET_MSR and KVM_SET_MSR. Accept a zero value for these MSRs to obey the contract. Signed-off-by: Like Xu --- Note, if !enable_pmu, it is easy to reproduce and verify it with selftest. arch/x86/kvm/pmu.c | 8 ++++++++ arch/x86/kvm/svm/pmu.c | 11 ++++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 7a74691de223..3575a3746bf9 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -439,11 +439,19 @@ static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr) int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { + if (msr_info->host_initiated && !vcpu->kvm->arch.enable_pmu) { + msr_info->data = 0; + return 0; + } + return static_call(kvm_x86_pmu_get_msr)(vcpu, msr_info); } int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { + if (msr_info->host_initiated && !vcpu->kvm->arch.enable_pmu) + return !!msr_info->data; + kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index); return static_call(kvm_x86_pmu_set_msr)(vcpu, msr_info); } diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 256244b8f89c..fe520b2649b5 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -182,7 +182,16 @@ static struct kvm_pmc *amd_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu, static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr, bool host_initiated) { /* All MSRs refer to exactly one PMC, so msr_idx_to_pmc is enough. */ - return false; + if (!host_initiated) + return false; + + switch (msr) { + case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: + case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: + return true; + default: + return false; + } } static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) From patchwork Wed Jun 1 03:19:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12866313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C25DCC433EF for ; Wed, 1 Jun 2022 03:19:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349295AbiFADTl (ORCPT ); Tue, 31 May 2022 23:19:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344235AbiFADTf (ORCPT ); Tue, 31 May 2022 23:19:35 -0400 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 512AF8B0AE; Tue, 31 May 2022 20:19:33 -0700 (PDT) Received: by mail-pj1-x1031.google.com with SMTP id a10so739049pju.3; Tue, 31 May 2022 20:19:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HWM4zuHZMlVlloTmo8iISWSBoICOOIq97NK5vJSN5mU=; b=NI1X0gOWwMWhW7vHycpTM6ByU5mtiMkajNw3q2SJYFHNF6y65N8SWmkniRbbkGu3H/ hfTCZ5ZkUsE3ODXpdVatdw560hPGd/oxrmA31aXa3caEhHrYlnZy7f+GWd89AAfQVMnN d8KOOAU/UpcJXc0lG3nAeGmiuqDNHR/Mpt8ktZFUzJ8HxcZ8Z0sMktICIbdcEFv6miYa PTG5IZDEV4ME1k0xKNnvP6+U356r8PbWyCKRfdE4JFP5ktSP1A/nPH186zlzodDEkYp8 Y3vnS6hCpn9bpugd2+oRUdKcQdqKyxWKeefZMUdH+BMUMvgxHr2iZqJQKA7AoFMLo+Bj UDRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HWM4zuHZMlVlloTmo8iISWSBoICOOIq97NK5vJSN5mU=; b=5lUeRqbVwYojgLb+OFOt2yZm84V4nVqnXLslkxX1NycvCgqqdg1x1XM5PIVeVONqKe 6wL0ZiWBWE966BugeDXHGAHKGCRv+FzsioN/OIhbgPQedKiZC8JqK1ARcDVNAJ1CWAII bXUv30Cil8J3zNIQ2eekGBwPRg8a9rSEqAv4E9+Cpwgw9tdDKReNlrsMOj0lx12i6nqK S3FbNE+ANB30fTwQp8DAOjlZVWBr5Ix/o+Q4QK4g7LzPl6diBljxcs8oCY6Tl5s097CY +IUIX8ypf+1mXNdBbvWNA1cLxcN5gE97OJ5e8hikjo7xvNRU1Ak+dWHPA8m0F0Y7Wzft qjZA== X-Gm-Message-State: AOAM5313waeHWlVLQyM5r/kqPnr/VHghE2u0/ahPVMrWFuULr/YhdGUc cVTNMr5GYR25JyPW4fbXRKg= X-Google-Smtp-Source: ABdhPJz0WwOvL8UTIuOTGR6LbqDQqUFkm9wE6C1Rul96QUPJcAJbwlxjfPU7pYEEklC7CSnXmU+HVA== X-Received: by 2002:a17:90b:1bca:b0:1e2:c0a2:80f7 with SMTP id oa10-20020a17090b1bca00b001e2c0a280f7mr19642798pjb.162.1654053572814; Tue, 31 May 2022 20:19:32 -0700 (PDT) Received: from localhost.localdomain ([203.205.141.23]) by smtp.gmail.com with ESMTPSA id i13-20020a056a00004d00b0050dc76281d3sm184691pfk.173.2022.05.31.20.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 20:19:32 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Sean Christopherson , Wanpeng Li Cc: Vitaly Kuznetsov , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] KVM: x86/pmu: Restrict advanced features based on module enable_pmu Date: Wed, 1 Jun 2022 11:19:24 +0800 Message-Id: <20220601031925.59693-2-likexu@tencent.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220601031925.59693-1-likexu@tencent.com> References: <20220601031925.59693-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Once vPMU is disabled, the KVM would not expose features like: PEBS (via clear kvm_pmu_cap.pebs_ept), legacy LBR and ARCH_LBR, CPUID 0xA leaf, PDCM bit and MSR_IA32_PERF_CAPABILITIES, plus PT_MODE_HOST_GUEST mode. What these associative features have in common is that their use relies on the underlying PMU counter and the host perf_event as a back-end resource requester or sharing part of the irq delivery path. Signed-off-by: Like Xu --- Follow up: a pmu_disable kvm-unit-test will be proposed later. arch/x86/kvm/pmu.h | 6 ++++-- arch/x86/kvm/vmx/capabilities.h | 6 +++++- arch/x86/kvm/vmx/vmx.c | 7 +++++-- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index d59e1cb3b5dc..8fbce2bc06d9 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -167,9 +167,11 @@ static inline void kvm_init_pmu_capability(void) * For Intel, only support guest architectural pmu * on a host with architectural pmu. */ - if ((is_intel && !kvm_pmu_cap.version) || !kvm_pmu_cap.num_counters_gp) { - memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap)); + if ((is_intel && !kvm_pmu_cap.version) || !kvm_pmu_cap.num_counters_gp) enable_pmu = false; + + if (!enable_pmu) { + memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap)); return; } diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h index dc2cb8a16e76..96d025483b7b 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -7,6 +7,7 @@ #include "lapic.h" #include "x86.h" #include "pmu.h" +#include "cpuid.h" extern bool __read_mostly enable_vpid; extern bool __read_mostly flexpriority_enabled; @@ -415,6 +416,9 @@ static inline u64 vmx_get_perf_capabilities(void) u64 perf_cap = PMU_CAP_FW_WRITES; u64 host_perf_cap = 0; + if (!enable_pmu) + return 0; + if (boot_cpu_has(X86_FEATURE_PDCM)) rdmsrl(MSR_IA32_PERF_CAPABILITIES, host_perf_cap); @@ -426,7 +430,7 @@ static inline u64 vmx_get_perf_capabilities(void) perf_cap &= ~PERF_CAP_PEBS_BASELINE; } - if (boot_cpu_has(X86_FEATURE_ARCH_LBR) && !cpu_has_vmx_arch_lbr()) + if (kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR) && !cpu_has_vmx_arch_lbr()) perf_cap &= ~PMU_CAP_LBR_FMT; return perf_cap; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 6927f6e8ec31..11bad594fedd 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7575,11 +7575,14 @@ static __init void vmx_set_cpu_caps(void) kvm_cpu_cap_check_and_set(X86_FEATURE_DS); kvm_cpu_cap_check_and_set(X86_FEATURE_DTES64); } - if (!cpu_has_vmx_arch_lbr()) { + if (!enable_pmu || !cpu_has_vmx_arch_lbr()) { kvm_cpu_cap_clear(X86_FEATURE_ARCH_LBR); supported_xss &= ~XFEATURE_MASK_LBR; } + if (!enable_pmu) + kvm_cpu_cap_clear(X86_FEATURE_PDCM); + if (!enable_sgx) { kvm_cpu_cap_clear(X86_FEATURE_SGX); kvm_cpu_cap_clear(X86_FEATURE_SGX_LC); @@ -8269,7 +8272,7 @@ static __init int hardware_setup(void) if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) return -EINVAL; - if (!enable_ept || !cpu_has_vmx_intel_pt()) + if (!enable_ept || !enable_pmu || !cpu_has_vmx_intel_pt()) pt_mode = PT_MODE_SYSTEM; if (pt_mode == PT_MODE_HOST_GUEST) vmx_init_ops.handle_intel_pt_intr = vmx_handle_intel_pt_intr; From patchwork Wed Jun 1 03:19:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12866314 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF64BC433FE for ; Wed, 1 Jun 2022 03:19:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349293AbiFADTq (ORCPT ); Tue, 31 May 2022 23:19:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349284AbiFADTh (ORCPT ); Tue, 31 May 2022 23:19:37 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AA558B0A7; Tue, 31 May 2022 20:19:35 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id h1so523841plf.11; Tue, 31 May 2022 20:19:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7+1EA6A/6RNV2QBUrRVFqjIksxe9LFHPVmVbTjKWy98=; b=RAxMiTTID2eCzjoSn3227yQkq6kWGgPAz4Vxzhpno5au8ao8ekcvbvoBIQVJ47cmXS Bwb4SUEsFHx0lu0Mm5+js0xv1voJcY1tTDDv2crsqbY/Nwi0k9ThysQ5uykPyz4ACBFX y8rgvpMSbM5T35Soge+8MxNZjsHByeQRpYLpYTHJ2FW0iK0GY/1FTIICfZJ9M31m2dBU zVGMjhI/+eBCjo95970rvpp+/oqLZnNCerIWUcFw/xHTPmPsRjuGczkVnYvoB+wDZ2cx /bn+3PhKH0t1TZ6Z21yAvDdZ8L35rhmeMsau0ZLiz9YYseJrZQhTlfJMB3mAEpnM8knY +EYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7+1EA6A/6RNV2QBUrRVFqjIksxe9LFHPVmVbTjKWy98=; b=nLeh00RSb6ZdGnYL2dZ1mlh9ygQ7kk7FA6FI639EGcRqhs+J3ss1QiMEraStiTPEu9 uM2whf3ut66gvvmYt7y3s3HzDzFt5AVaT1W+uPlyq+XMRRWz080t6i+X3czyiFDxUBXL cJeJMcp7sC52DyL6bwnS3Q50lKNcBG+qHcsUrAW9LWlc34i4nNlSbNEuy28hVKED0SFQ ioUMF+sHIsYgXNyWCvaDLKoxZPqojSCpHI4FZc7/Tbb4BXo3KPdgxLDkw3hnV04TvB5a Kg8mZOughDmXiak0TS9jQYCxAYwPULfSrHkw+qXZVtpLmpNh5rn8YlM1wSQ+98mz7e8D 5n4w== X-Gm-Message-State: AOAM5311UQ2d1udgSHekyuFiFEHwQWW9eQuBEHDWUTa8VQ584C1TiE+7 wf2e1Wswj+BbKzCa0sE8KXg= X-Google-Smtp-Source: ABdhPJwx/TQ1fyWBUhEBxzMKoDjXWgi81xMb6vE02IzLHAAtZ0sg03nyELtVs+yiIX/y1qsOzS3FUw== X-Received: by 2002:a17:90b:4f47:b0:1e3:38c7:70b5 with SMTP id pj7-20020a17090b4f4700b001e338c770b5mr7215818pjb.32.1654053575187; Tue, 31 May 2022 20:19:35 -0700 (PDT) Received: from localhost.localdomain ([203.205.141.23]) by smtp.gmail.com with ESMTPSA id i13-20020a056a00004d00b0050dc76281d3sm184691pfk.173.2022.05.31.20.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 20:19:34 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Sean Christopherson , Wanpeng Li Cc: Vitaly Kuznetsov , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] KVM: x86/pmu: Avoid exposing Intel BTS feature Date: Wed, 1 Jun 2022 11:19:25 +0800 Message-Id: <20220601031925.59693-3-likexu@tencent.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220601031925.59693-1-likexu@tencent.com> References: <20220601031925.59693-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu The BTS feature (including the ability to set the BTS and BTINT bits in the DEBUGCTL MSR) is currently unsupported on KVM. But we may try using the BTS facility on a PEBS enabled guest like this: perf record -e branches:u -c 1 -d ls and then we would encounter the following call trace: [] unchecked MSR access error: WRMSR to 0x1d9 (tried to write 0x00000000000003c0) at rIP: 0xffffffff810745e4 (native_write_msr+0x4/0x20) [] Call Trace: [] intel_pmu_enable_bts+0x5d/0x70 [] bts_event_add+0x54/0x70 [] event_sched_in+0xee/0x290 As it lacks any CPUID indicator or perf_capabilities valid bit fields to prompt for this information, the platform would hint the Intel BTS feature unavailable to guest by setting the BTS_UNAVAIL bit in the IA32_MISC_ENABLE. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.h | 3 +++ arch/x86/kvm/vmx/pmu_intel.c | 4 +++- arch/x86/kvm/x86.c | 6 +++--- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 8fbce2bc06d9..c1b61671ba1e 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -8,6 +8,9 @@ #define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu)) #define pmc_to_pmu(pmc) (&(pmc)->vcpu->arch.pmu) +#define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | \ + MSR_IA32_MISC_ENABLE_BTS_UNAVAIL) + /* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */ #define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index ddf837130d1f..967fd2e15815 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -634,6 +634,9 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->pebs_enable_mask = ~0ull; pmu->pebs_data_cfg_mask = ~0ull; + vcpu->arch.ia32_misc_enable_msr |= (MSR_IA32_MISC_ENABLE_BTS_UNAVAIL | + MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL); + entry = kvm_find_cpuid_entry(vcpu, 0xa, 0); if (!entry || !vcpu->kvm->arch.enable_pmu) return; @@ -725,7 +728,6 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) ~((1ull << pmu->nr_arch_gp_counters) - 1); } } else { - vcpu->arch.ia32_misc_enable_msr |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; vcpu->arch.perf_capabilities &= ~PERF_CAP_PEBS_MASK; } diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 7460b9a77d9a..22c3c576fbc2 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -3565,12 +3565,12 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) break; case MSR_IA32_MISC_ENABLE: { u64 old_val = vcpu->arch.ia32_misc_enable_msr; - u64 pmu_mask = MSR_IA32_MISC_ENABLE_EMON | - MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; + u64 pmu_mask = MSR_IA32_MISC_ENABLE_PMU_RO_MASK | + MSR_IA32_MISC_ENABLE_EMON; /* RO bits */ if (!msr_info->host_initiated && - ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) + ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)) return 1; /*