From patchwork Wed Jun 1 04:15:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Potin Lai X-Patchwork-Id: 12866341 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43575C433F5 for ; Wed, 1 Jun 2022 04:19:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8RKz2GFRxVBq/W3nk1AwVJCARyEsz5M52gL6Xv0b6qU=; b=yTVyAnl+OS1ImU LIjVV+bOoHsRWTVbKwCV7NnExvyqwbhawSnyasn3RVZo8sk5OJUYJcUdANn72Ty+lGaWMy4WDT4PI M4jvvfWGj0Oi8GL6RtZ8dNO345toHWqleYaUmOnMWKnLFRztU6SKQn5/p+DGY0ejLCer1q2Ws3cfR F17Tmj2SRsrjwJ3vRD3bmz4fCffoQhwj93lFcXZ5c/jLl4S3CdTcTg6xJC7yg14+caiy24sTJK3Kj iZu1XpqF6eHpn9KFGIXM1YAW3wTUL6BS+DK9ZxDVQzjZPzvSyuKtSQdJbjmFSPQw32tZn+BlHguR7 2LrzXKsu1hxSHpIUC7ow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nwFny-00DmZJ-R5; Wed, 01 Jun 2022 04:17:58 +0000 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nwFnn-00DmVW-37 for linux-arm-kernel@lists.infradead.org; Wed, 01 Jun 2022 04:17:48 +0000 Received: by mail-pj1-x1032.google.com with SMTP id q12-20020a17090a304c00b001e2d4fb0eb4so4934325pjl.4 for ; Tue, 31 May 2022 21:17:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=p/+ntGXUelw5ZDKTegotppZpOKb88sw5s3W1VT60Y9Y=; b=BU4zuxcHxh+X+A8rj2aKOosynv9Ke9MJ76UXkz7klHU11GJSFLHzRfLrO6Hf/BrqPF 3zXbiI0QmoKyPoP+cZ8T/Rvmm+nISUxm6buoXmGvhyR0K3NH++WHSyEQG22ZdCPuw6Tg 1SQQz+84Xu5ZPs4A62/st5YNzXkEN1K3O8FYxm8CbL9boCVhfeeYOeXROdwzitvUBqrA DFH+Ham35Nc3eWm4XF4cOkgyClE2QcUKQOxadEUL7Z+hdzSJtLQzFhQliJrPVx2RsAk4 77MLz5V0xpX8sbC6i4P2FnftnE4COW4hGeECaHQtafPBsG0frihMYwzq6rYL58kZ/+F+ dtOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p/+ntGXUelw5ZDKTegotppZpOKb88sw5s3W1VT60Y9Y=; b=cDe0CFiKQjnKpvg1EaQFKnxK9z5ijKKg6SN8c1lnfYln0myTIzQ2ZBzpqvhEoRyKCw z4PWf1ZSxI8Gc6YKr+Om+oZcj+eLA0CBw4PeMLJ53kJmZ9S7s6ibFQEeITFlVxRZ9dsq aH/HQ/VUgtsDvWrr9lHIedZNwLBHfkbz6pz57U2ta2c6w4WcvMbykmf0RL0LDyg+Xhv6 dXSlfBtmmUL9kewSKRzCarh27a0Pkk58uS9L4W0xICCcNcZUQLemfK44zZxcibXA9IkO y0lRAsq7yl+aro7tN3hATcJAEYG307mjiz+oFY0mxIRS2yEK3eu7rWp4s2Lad1ttn7Id 0G1w== X-Gm-Message-State: AOAM532gvQFoxeSdam2NXrBg4MW+4Qo0I5Wrl2iI5afriZfoBcNGmACY 5EgjhgcfallYcpcN5NvG5MM= X-Google-Smtp-Source: ABdhPJx+oMC5YHO/HcdO/PczBVYNasPXpb2NZykBAGhnAUC/SLEgp2vTpff2UMHbUmeZMm0e2M4m7A== X-Received: by 2002:a17:90a:bb17:b0:1e0:ab18:4491 with SMTP id u23-20020a17090abb1700b001e0ab184491mr31807267pjr.120.1654057065640; Tue, 31 May 2022 21:17:45 -0700 (PDT) Received: from potin-quanta.dhcpserver.local (125-228-123-29.hinet-ip.hinet.net. [125.228.123.29]) by smtp.gmail.com with ESMTPSA id u11-20020a63d34b000000b003c14af505f6sm290749pgi.14.2022.05.31.21.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 21:17:45 -0700 (PDT) From: Potin Lai To: Brendan Higgins , Benjamin Herrenschmidt , Joel Stanley , Andrew Jeffery , Rob Herring , Rayn Chen Cc: Patrick Williams , Potin Lai , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Potin Lai Subject: [PATCH v2 1/2] aspeed: i2c: add manual clock setting feature Date: Wed, 1 Jun 2022 12:15:11 +0800 Message-Id: <20220601041512.21484-2-potin.lai.pt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220601041512.21484-1-potin.lai.pt@gmail.com> References: <20220601041512.21484-1-potin.lai.pt@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220531_211747_194754_A2837338 X-CRM114-Status: GOOD ( 16.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add manual tuning i2c clock timing register support by reading following properties. * aspeed,i2c-manual-clk: Enable aspeed i2c clock manual setting * aspeed,i2c-base-clk-div: Base Clock divisor (tBaseClk) * aspeed,i2c-clk-high-cycle: Cycles of clock-high pulse (tClkHigh) * aspeed,i2c-clk-low-cycle: Cycles of clock-low pulse (tClkLow) Signed-off-by: Potin Lai --- drivers/i2c/busses/i2c-aspeed.c | 57 ++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c index 67e8b97c0c95..64424f377f27 100644 --- a/drivers/i2c/busses/i2c-aspeed.c +++ b/drivers/i2c/busses/i2c-aspeed.c @@ -60,6 +60,7 @@ #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12) #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0) #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0) +#define ASPEED_I2CD_TIME_BASE_DIVISOR_MAX 32768 /* 0x08 : I2CD Clock and AC Timing Control Register #2 */ #define ASPEED_NO_TIMEOUT_CTRL 0 @@ -898,6 +899,57 @@ static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus) return 0; } +/* precondition: bus.lock has been acquired. */ +static int aspeed_i2c_manual_clk_setup(struct aspeed_i2c_bus *bus) +{ + u32 divisor, clk_high, clk_low, clk_reg_val; + + if (device_property_read_u32(bus->dev, "aspeed,i2c-base-clk-div", + &divisor) != 0) { + dev_err(bus->dev, "Could not read aspeed,i2c-base-clk-div\n"); + return -EINVAL; + } else if (!divisor || divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MAX || + BIT(__fls(divisor)) != divisor) { + dev_err(bus->dev, "Invalid aspeed,i2c-base-clk-div: %u\n", + divisor); + return -EINVAL; + } + + if (device_property_read_u32(bus->dev, "aspeed,i2c-clk-high-cycle", + &clk_high) != 0) { + dev_err(bus->dev, "Could not read aspeed,i2c-clk-high-cycle\n"); + return -EINVAL; + } else if ((clk_high-1) > ASPEED_I2CD_TIME_SCL_REG_MAX) { + dev_err(bus->dev, "Invalid aspeed,i2c-clk-high-cycle: %u\n", + clk_high); + return -EINVAL; + } + + if (device_property_read_u32(bus->dev, "aspeed,i2c-clk-low-cycle", + &clk_low) != 0) { + dev_err(bus->dev, "Could not read aspeed,i2c-clk-low-cycle\n"); + return -EINVAL; + } else if ((clk_low-1) > ASPEED_I2CD_TIME_SCL_REG_MAX) { + dev_err(bus->dev, "Invalid aspeed,i2c-clk-low-cycle: %u\n", + clk_low); + return -EINVAL; + } + + clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1); + clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK | + ASPEED_I2CD_TIME_THDSTA_MASK | + ASPEED_I2CD_TIME_TACST_MASK); + clk_reg_val |= (ilog2(divisor) & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) + | (((clk_high-1) << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT) + & ASPEED_I2CD_TIME_SCL_HIGH_MASK) + | (((clk_low-1) << ASPEED_I2CD_TIME_SCL_LOW_SHIFT) + & ASPEED_I2CD_TIME_SCL_LOW_MASK); + writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1); + writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2); + + return 0; +} + /* precondition: bus.lock has been acquired. */ static int aspeed_i2c_init(struct aspeed_i2c_bus *bus, struct platform_device *pdev) @@ -908,7 +960,10 @@ static int aspeed_i2c_init(struct aspeed_i2c_bus *bus, /* Disable everything. */ writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); - ret = aspeed_i2c_init_clk(bus); + if (of_property_read_bool(pdev->dev.of_node, "aspeed,i2c-manual-clk")) + ret = aspeed_i2c_manual_clk_setup(bus); + else + ret = aspeed_i2c_init_clk(bus); if (ret < 0) return ret; From patchwork Wed Jun 1 04:15:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Potin Lai X-Patchwork-Id: 12866342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D64F4C433F5 for ; Wed, 1 Jun 2022 04:19:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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[125.228.123.29]) by smtp.gmail.com with ESMTPSA id u11-20020a63d34b000000b003c14af505f6sm290749pgi.14.2022.05.31.21.17.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 21:17:47 -0700 (PDT) From: Potin Lai To: Brendan Higgins , Benjamin Herrenschmidt , Joel Stanley , Andrew Jeffery , Rob Herring , Rayn Chen Cc: Patrick Williams , Potin Lai , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Potin Lai Subject: [PATCH v2 2/2] dt-bindings: aspeed-i2c: add properties for manual clock setting Date: Wed, 1 Jun 2022 12:15:12 +0800 Message-Id: <20220601041512.21484-3-potin.lai.pt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220601041512.21484-1-potin.lai.pt@gmail.com> References: <20220601041512.21484-1-potin.lai.pt@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220531_211749_716391_7436C7CD X-CRM114-Status: GOOD ( 10.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add following properties for manual tuning clock divisor and cycle of hign/low pulse witdh. * aspeed,i2c-manual-clk: Enable aspeed i2c clock manual setting * aspeed,i2c-base-clk-div: Base Clock divisor (tBaseClk) * aspeed,i2c-clk-high-cycle: Cycles of clock-high pulse (tClkHigh) * aspeed,i2c-clk-low-cycle: Cycles of clock-low pulse (tClkLow) Signed-off-by: Potin Lai --- .../devicetree/bindings/i2c/aspeed,i2c.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml index ea643e6c3ef5..e2f67fe2aa0c 100644 --- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml @@ -12,6 +12,28 @@ maintainers: allOf: - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + const: st,stm32-uart + + then: + properties: + aspeed,i2c-clk-high-cycle: + maximum: 8 + aspeed,i2c-clk-low-cycle: + maximum: 8 + + - if: + required: + - aspeed,i2c-manual-clk + + then: + required: + - aspeed,i2c-base-clk-div + - aspeed,i2c-clk-high-cycle + - aspeed,i2c-clk-low-cycle + properties: compatible: enum: @@ -49,6 +71,28 @@ properties: description: states that there is another master active on this bus + aspeed,i2c-manual-clk: + type: boolean + description: enable manual clock setting + + aspeed,i2c-base-clk-div: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, + 16384, 32768] + description: base clock divisor + + aspeed,i2c-clk-high-cycle: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 16 + description: cycles of master clock-high pulse width + + aspeed,i2c-clk-low-cycle: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 16 + description: cycles of master clock-low pulse width + required: - reg - compatible