From patchwork Wed Jun 1 15:46:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Anikiel?= X-Patchwork-Id: 12867010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EB8DC433EF for ; Wed, 1 Jun 2022 15:47:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 71F73C341C4; Wed, 1 Jun 2022 15:47:44 +0000 (UTC) Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 8B872C3411A for ; Wed, 1 Jun 2022 15:47:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 8B872C3411A Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=semihalf.com Authentication-Results: smtp.kernel.org; spf=none smtp.mailfrom=semihalf.com Received: by mail-lf1-f49.google.com with SMTP id j10so3408744lfe.12 for ; Wed, 01 Jun 2022 08:47:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UfwBRuu4ZM72mhs6ACHC3c3G4LBBG//hhQB7GRYTpTo=; b=gsAcBGGYZlDrxc1w8U/I0RGQZyGtBlacpi0yu1+HVT6FE10pI8btlK+E36lu517qr3 ITWdbD7iEdtqqg1BahkjmwOBh+QDu8nK1htTgWX9S8X18IyY+Yt/sGtPk1TW8s9W9frF ybKCcZerXQKJdbcF8MshulmkBkzafVgiwxqjV6ob54TUkmet+CgA74pxTRc45bkFr+rB VvAiIoKLhwtD7oyUHoFWiqOWwBhAMkgA8sLZW17qHqhWrZ3xIaEcBc/Xqwk60N2qHwk6 PL9gcvmMho+PKv/haR/HSSBbDYbPuZ/1e1+G2sFjxQ9833/zw2j0p0zyIZb7exRn/fTu E4eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UfwBRuu4ZM72mhs6ACHC3c3G4LBBG//hhQB7GRYTpTo=; b=0r7gK4K1uP5F/obeeKm6q686gATbqYVNfvvjYm4cWN5O2yx0orpGrzoH0YD0LFfjBP 1IOKQaHlLmsESZwHNz+jh71sA56K1SmBqV+vl48Zo+4Yh8J5sr1dUqHAVzPqMWurrsu0 e11siFXcL2mJZ4ztJxapqd+B1JW1n24He9F5KNUn/N8XVyARHuyx4PWth6BRDgnQzTj4 +Z3fVsvPlMLaObUI3O8kq34sAMiCuiKg/uFzBpqoT1ca0nseex9R1HPX2aCZEd2euPBB hTVrpcochCz5jEA/W1ct4NRwujy1ZqdNVedtsHGXE6t9h8gAlvfsHY5QP58Lo3cZHYUh zDhQ== X-Gm-Message-State: AOAM533XnnfDeFn6G8ueRYN7tQxM56cGL9g/jcgTss9Q/6ar/EOZ4Drl 4r6AuwQQ50G+RnSlHdEF47UKCfS9VXY0QA== X-Google-Smtp-Source: ABdhPJw2YqAERwhfHBUEzSKgK8Qry/TcdNJe+5LBYjVk0PezmPnVZkD0WfINjfthvl3P4PpyLWKaag== X-Received: by 2002:a05:6512:3f05:b0:477:8ecb:4fbe with SMTP id y5-20020a0565123f0500b004778ecb4fbemr49162017lfa.193.1654098461732; Wed, 01 Jun 2022 08:47:41 -0700 (PDT) Received: from panikiel.wifi.semihalf.net ([83.142.187.86]) by smtp.gmail.com with ESMTPSA id f10-20020a19380a000000b00478ad871b25sm431219lfa.145.2022.06.01.08.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 08:47:41 -0700 (PDT) From: =?utf-8?q?Pawe=C5=82_Anikiel?= List-Id: To: soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, olof@lixom.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dinguyen@kernel.org, amstan@chromium.org, upstream@semihalf.com, =?utf-8?q?Pawe=C5=82_Anikiel?= Subject: [PATCH v2 1/5] ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi Date: Wed, 1 Jun 2022 17:46:43 +0200 Message-Id: <20220601154647.80071-2-pan@semihalf.com> X-Mailer: git-send-email 2.36.1.255.ge46751e96f-goog In-Reply-To: <20220601154647.80071-1-pan@semihalf.com> References: <20220601154647.80071-1-pan@semihalf.com> MIME-Version: 1.0 The Mercury+ AA1 is not a standalone board, rather it's a module with an Arria 10 SoC. Remove status = "okay" and i2c aliases, as they are routed to the base board and should be enabled from there. Signed-off-by: Paweł Anikiel Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/Makefile | 1 - ...1.dts => socfpga_arria10_mercury_aa1.dtsi} | 28 ------------------- 2 files changed, 29 deletions(-) rename arch/arm/boot/dts/{socfpga_arria10_mercury_aa1.dts => socfpga_arria10_mercury_aa1.dtsi} (84%) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index edfbedaa6168..023c8b4ba45c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1146,7 +1146,6 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-torbreck.dtb dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ - socfpga_arria10_mercury_aa1.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi similarity index 84% rename from arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts rename to arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi index a75c059b6727..4b21351f2694 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0 -/dts-v1/; #include "socfpga_arria10.dtsi" @@ -11,8 +10,6 @@ / { aliases { ethernet0 = &gmac0; serial1 = &uart1; - i2c0 = &i2c0; - i2c1 = &i2c1; }; memory@0 { @@ -43,7 +40,6 @@ &gmac0 { phy-addr = <0xffffffff>; /* probe for phy addr */ max-frame-size = <3800>; - status = "okay"; phy-handle = <&phy3>; @@ -69,22 +65,8 @@ phy3: ethernet-phy@3 { }; }; -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - &i2c1 { - status = "okay"; isl12022: isl12022@6f { - status = "okay"; compatible = "isil,isl12022"; reg = <0x6f>; }; @@ -92,7 +74,6 @@ isl12022: isl12022@6f { /* Following mappings are taken from arria10 socdk dts */ &mmc { - status = "okay"; cap-sd-highspeed; broken-cd; bus-width = <4>; @@ -101,12 +82,3 @@ &mmc { &osc1 { clock-frequency = <33330000>; }; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; From patchwork Wed Jun 1 15:46:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Anikiel?= X-Patchwork-Id: 12867011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4CB17CCA477 for ; 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Wed, 01 Jun 2022 08:47:42 -0700 (PDT) Received: from panikiel.wifi.semihalf.net ([83.142.187.86]) by smtp.gmail.com with ESMTPSA id f10-20020a19380a000000b00478ad871b25sm431219lfa.145.2022.06.01.08.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 08:47:42 -0700 (PDT) From: =?utf-8?q?Pawe=C5=82_Anikiel?= List-Id: To: soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, olof@lixom.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dinguyen@kernel.org, amstan@chromium.org, upstream@semihalf.com, =?utf-8?q?Pawe=C5=82_Anikiel?= Subject: [PATCH v2 2/5] ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts Date: Wed, 1 Jun 2022 17:46:44 +0200 Message-Id: <20220601154647.80071-3-pan@semihalf.com> X-Mailer: git-send-email 2.36.1.255.ge46751e96f-goog In-Reply-To: <20220601154647.80071-1-pan@semihalf.com> References: <20220601154647.80071-1-pan@semihalf.com> MIME-Version: 1.0 The ecc manager is a part of the Arria 10 SoC, move it to the correct dts. Signed-off-by: Paweł Anikiel Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/socfpga_arria10.dtsi | 10 ++++++++++ arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 12 ------------ 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 26bda2557fe8..4370e3cbbb4b 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -736,6 +736,16 @@ emac0-tx-ecc@ff8c0c00 { <37 IRQ_TYPE_LEVEL_HIGH>; }; + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; + dma-ecc@ff8c8000 { compatible = "altr,socfpga-dma-ecc"; reg = <0xff8c8000 0x400>; diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi index 4b21351f2694..b0d20101cd00 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi @@ -23,18 +23,6 @@ chosen { }; }; -&eccmgr { - sdmmca-ecc@ff8c2c00 { - compatible = "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c2c00 0x400>; - altr,ecc-parent = <&mmc>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - &gmac0 { phy-mode = "rgmii"; phy-addr = <0xffffffff>; /* probe for phy addr */ From patchwork Wed Jun 1 15:46:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Anikiel?= X-Patchwork-Id: 12867012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C46DCCA478 for ; Wed, 1 Jun 2022 15:47:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 4E315C3411C; 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Wed, 01 Jun 2022 08:47:43 -0700 (PDT) From: =?utf-8?q?Pawe=C5=82_Anikiel?= List-Id: To: soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, olof@lixom.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dinguyen@kernel.org, amstan@chromium.org, upstream@semihalf.com, =?utf-8?q?Pawe=C5=82_Anikiel?= Subject: [PATCH v2 3/5] ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts Date: Wed, 1 Jun 2022 17:46:45 +0200 Message-Id: <20220601154647.80071-4-pan@semihalf.com> X-Mailer: git-send-email 2.36.1.255.ge46751e96f-goog In-Reply-To: <20220601154647.80071-1-pan@semihalf.com> References: <20220601154647.80071-1-pan@semihalf.com> MIME-Version: 1.0 Add atsha204a node to Mercury+ AA1 dts Signed-off-by: Paweł Anikiel Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi index b0d20101cd00..dd1bfa7e1a78 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 - +/* + * Copyright 2022 Google LLC + */ #include "socfpga_arria10.dtsi" / { @@ -54,6 +56,11 @@ phy3: ethernet-phy@3 { }; &i2c1 { + atsha204a: crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; + isl12022: isl12022@6f { compatible = "isil,isl12022"; reg = <0x6f>; From patchwork Wed Jun 1 15:46:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Anikiel?= X-Patchwork-Id: 12867013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30D71CCA47A for ; Wed, 1 Jun 2022 15:47:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 187FEC3411A; Wed, 1 Jun 2022 15:47:47 +0000 (UTC) Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 99013C385A5 for ; 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Wed, 01 Jun 2022 08:47:44 -0700 (PDT) From: =?utf-8?q?Pawe=C5=82_Anikiel?= List-Id: To: soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, olof@lixom.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dinguyen@kernel.org, amstan@chromium.org, upstream@semihalf.com, =?utf-8?q?Pawe=C5=82_Anikiel?= Subject: [PATCH v2 4/5] ARM: dts: socfpga: Add Google Chameleon v3 devicetree Date: Wed, 1 Jun 2022 17:46:46 +0200 Message-Id: <20220601154647.80071-5-pan@semihalf.com> X-Mailer: git-send-email 2.36.1.255.ge46751e96f-goog In-Reply-To: <20220601154647.80071-1-pan@semihalf.com> References: <20220601154647.80071-1-pan@semihalf.com> MIME-Version: 1.0 Add devicetree for the Google Chameleon v3 board. Signed-off-by: Paweł Anikiel Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/socfpga_arria10_chameleonv3.dts | 90 +++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 023c8b4ba45c..9417106d3289 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1146,6 +1146,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-torbreck.dtb dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ + socfpga_arria10_chameleonv3.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts new file mode 100644 index 000000000000..422d00cd4c74 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +/dts-v1/; +#include "socfpga_arria10_mercury_aa1.dtsi" + +/ { + model = "Google Chameleon V3"; + compatible = "google,chameleon-v3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + serial0 = &uart0; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; +}; + +&gmac0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + ssm2603: audio-codec@1a { + compatible = "adi,ssm2603"; + reg = <0x1a>; + }; +}; + +&i2c1 { + status = "okay"; + + u80: gpio@21 { + compatible = "nxp,pca9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SOM_AUD_MUTE", + "DP1_OUT_CEC_EN", + "DP2_OUT_CEC_EN", + "DP1_SOM_PS8469_CAD", + "DPD_SOM_PS8469_CAD", + "DP_OUT_PWR_EN", + "STM32_RST_L", + "STM32_BOOT0", + + "FPGA_PROT", + "STM32_FPGA_COMM0", + "TP119", + "TP120", + "TP121", + "TP122", + "TP123", + "TP124"; + }; +}; + +&mmc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; From patchwork Wed Jun 1 15:46:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Anikiel?= X-Patchwork-Id: 12867014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DB89CCA479 for ; Wed, 1 Jun 2022 15:47:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 279AEC3411F; Wed, 1 Jun 2022 15:47:48 +0000 (UTC) Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id B9C1AC3411C for ; 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Wed, 01 Jun 2022 08:47:45 -0700 (PDT) From: =?utf-8?q?Pawe=C5=82_Anikiel?= List-Id: To: soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, olof@lixom.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dinguyen@kernel.org, amstan@chromium.org, upstream@semihalf.com, =?utf-8?q?Pawe=C5=82_Anikiel?= Subject: [PATCH v2 5/5] dt-bindings: altera: Add Chameleon v3 board Date: Wed, 1 Jun 2022 17:46:47 +0200 Message-Id: <20220601154647.80071-6-pan@semihalf.com> X-Mailer: git-send-email 2.36.1.255.ge46751e96f-goog In-Reply-To: <20220601154647.80071-1-pan@semihalf.com> References: <20220601154647.80071-1-pan@semihalf.com> MIME-Version: 1.0 Add Chameleon v3 to Arria 10 boards. Signed-off-by: Paweł Anikiel --- Documentation/devicetree/bindings/arm/altera.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 5e2017c0a051..400543fbe78d 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -26,6 +26,7 @@ properties: - enum: - altr,socfpga-arria10-socdk - enclustra,mercury-aa1 + - google,chameleon-v3 - const: altr,socfpga-arria10 - const: altr,socfpga