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mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com; Message-ID: <46c6bf61-5669-0de2-163d-64b9a3ce07a7@suse.com> Date: Thu, 2 Jun 2022 12:26:44 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: [PATCH v2 1/2] x86/mwait-idle: add 'preferred-cstates' command line option Content-Language: en-US From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?utf-8?q?Roger_Pau_Monn=C3=A9?= References: In-Reply-To: X-ClientProxiedBy: AS9P251CA0002.EURP251.PROD.OUTLOOK.COM (2603:10a6:20b:50f::10) To VE1PR04MB6560.eurprd04.prod.outlook.com (2603:10a6:803:122::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 85e09c86-bff9-4760-e046-08da44826519 X-MS-TrafficTypeDiagnostic: HE1PR0401MB2521:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?UwQG4QIR+cTrMz59WmNSlZ2tVGoD?= =?utf-8?q?O92jtA/2R8xsczmx6VYQ+JsimAk5sXTVQnNFHC7RrxO1FBbkfPyfEJTSsi3fzErj5?= =?utf-8?q?K7ZMLAMJOR0q6HovINbqVbP+WE8LvDyBbVGwIn1SeXQa7Ai+0AMN7BK7ZE5Ba+hFy?= =?utf-8?q?LBNbYMmR9JEywF9t1Il/rV6v+PZNeIAVUJ7EVucJBRL+uzTd7sYyzNtM4eS5BOFJU?= =?utf-8?q?UIskcG601YW0aYRP+QEkgKOm++EMtfdL+f8CLdO1pWpcxzZGq4q5R00UjvQBA3vfw?= =?utf-8?q?bLOLNBK1nL4ewR7iwSdgQ+UfbfTAL858rCrAH5oQg6D2J/XgOPN0ymb2uvpEwM0l9?= =?utf-8?q?MXEhq3o4RGAndkO+EOnAoh+MYj21HVlqAfKVWWVoTmoRknP1aN4N7oOGPaRAicy8v?= =?utf-8?q?hfckDpfZgenDR5rNDL8A1NKcjxenL/uf0ZcCeZpGUCShbwgAgxwnDXsHAr9dih/0H?= =?utf-8?q?va6YUHCjogZag8/QI8CwA5Lz6myh83EExabS4AkJISWFOPG6SrEZq2lhFg8B3RCw8?= =?utf-8?q?3W18ZICkBRHnupS2wS6pxNa5O3eXW9xDoq+50jmiQz+IFZDpsGGfxf3p51FmlSqs/?= =?utf-8?q?1tx80/4I2wVCM6NQlVlEwMI6qfP2PFFdM2TvaSR3grULLnR0s9AwDRPfrKV/NZDuH?= =?utf-8?q?W9nKmKc29Qn/wFdHR3pze8LGuZgabHYP25NWZAarXUsNTmpPhuUfyEx2opPimbEpa?= =?utf-8?q?pITKpyCkL5nKIhLi6H4wW1OWPgPK0lUw4087N6SaAZhfyrcOkjKvNL1KsYRhOTokD?= =?utf-8?q?t6RqayN94QwZa/5UArRmLeB9myz0SGKFRm2wbfOr1TNgh1Kee2U0EiJ4Nww9lThs0?= =?utf-8?q?lN5kwsGSV3OR2s6t+/dDN7ypPQswxZS8DOoFv854zAeVdFm4wNB4AoITt6zPk8AP5?= =?utf-8?q?y2Gax56OHmI1bzqLvupWBRRbPu4d6B32e+4/a3vBTQOfG8+2jstVdF5WxF8fa10MM?= =?utf-8?q?lGZFrnrRvyBlsedcbFOhCA4t8VU2Rt/HxcWvz7PPzk9EFdq7V/Fe0r85pqDjz+FCz?= =?utf-8?q?21QvnBnmI4LONO9WKeyeFPqv3KvGf/mf119s6GE0T8y89Kp+4b5QoIdiTFSNh6ZhB?= =?utf-8?q?EE4tQtXbup1WCQ/YPqbAR2aw32rBnT0f4qGfqX40fZrJMNL9vvgtCB40WSARUcgWb?= =?utf-8?q?SKKTCRtJ27HywlF1iQplb8z4EpJewQ64hgmYrTK5aZ3fqcNMIU4nRk3Mb5ykoxFua?= =?utf-8?q?ijwOp22e53cX8DQgqwOOAbPyFblrWjmixr2F3pDqWx9TTUbDLGAjlbpJp/2ugfTjo?= =?utf-8?q?djYrwzZgOYU8evuUuKMTUt87wZ7OV5lBXtGeFyTJMUQahqlAnoJIq9dpXvSvrgGO8?= =?utf-8?q?IUjTSohBmVOlWtphafHbTIBK1hMzyaukR+/faOu+gb3kmhxZG1f6Fgk6kl/0kGgU2?= =?utf-8?q?HOgHr809EFX7Fzpqxg20ep4beHnklsaGfYa46g5YdXcck7w1p+fTEP0hAFtDRRVa/?= =?utf-8?q?TW+WfPr+oi5WG3co6iawUbGaZuoI/Lif/mC41AKroBRJmDQ0RG4IxcMYwTDr6vdMa?= =?utf-8?q?4/Zb/ETP/F0HExYqzJC1QcIwWUkkGMoHrZf9iK4AAN107hE0UqhT3FoB73Xa3+6QM?= =?utf-8?q?gT0bwZCzdNdmFz3LxwRQJicvBRnep9Jgmmpfzg4rbkhGaHX6Cbmg+qiVxFruWulzQ?= =?utf-8?q?L0MpW4FLouvQklcQufC3x1K9O4JDAUpA=3D=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 85e09c86-bff9-4760-e046-08da44826519 X-MS-Exchange-CrossTenant-AuthSource: VE1PR04MB6560.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2022 10:26:46.0228 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: juT4yKrR9yjI73flIbiuQsfgVnCd6srd2I/uv2frnq6PZJmsxcJjgA++jka6Ok4mb96F51QLOfvNgwabZtgY6Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0401MB2521 From: Artem Bityutskiy On Sapphire Rapids Xeon (SPR) the C1 and C1E states are basically mutually exclusive - only one of them can be enabled. By default, 'intel_idle' driver enables C1 and disables C1E. However, some users prefer to use C1E instead of C1, because it saves more energy. This patch adds a new module parameter ('preferred_cstates') for enabling C1E and disabling C1. Here is the idea behind it. 1. This option has effect only for "mutually exclusive" C-states like C1 and C1E on SPR. 2. It does not have any effect on independent C-states, which do not require other C-states to be disabled (most states on most platforms as of today). 3. For mutually exclusive C-states, the 'intel_idle' driver always has a reasonable default, such as enabling C1 on SPR by default. On other platforms, the default may be different. 4. Users can override the default using the 'preferred_cstates' parameter. 5. The parameter accepts the preferred C-states bit-mask, similarly to the existing 'states_off' parameter. 6. This parameter is not limited to C1/C1E, and leaves room for supporting other mutually exclusive C-states, if they come in the future. Today 'intel_idle' can only be compiled-in, which means that on SPR, in order to disable C1 and enable C1E, users should boot with the following kernel argument: intel_idle.preferred_cstates=4 Signed-off-by: Artem Bityutskiy Signed-off-by: Rafael J. Wysocki Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git da0e58c038e6 Enable C1E (if requested) not only on the BSP's socket / package. Alter command line option to fit our model, and extend it to also accept string form arguments. Signed-off-by: Jan Beulich --- v2: Also accept string form arguments for command line option. Restore C1E-control related enum from Linux, despite our somewhat different use (and bigger code churn). --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -1885,6 +1885,12 @@ paging controls access to usermode addre ### ple_window (Intel) > `= ` +### preferred-cstates (x86) +> `= ( | List of ( C1 | C1E | C2 | ... )` + +This is a mask of C-states which are to be used preferably. This option is +applicable only on hardware were certain C-states are exclusive of one another. + ### psr (Intel) > `= List of ( cmt: | rmid_max: | cat: | cos_max: | cdp: )` --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -82,10 +82,29 @@ boolean_param("mwait-idle", opt_mwait_id static unsigned int mwait_substates; +/* + * Some platforms come with mutually exclusive C-states, so that if one is + * enabled, the other C-states must not be used. Example: C1 and C1E on + * Sapphire Rapids platform. This parameter allows for selecting the + * preferred C-states among the groups of mutually exclusive C-states - the + * selected C-states will be registered, the other C-states from the mutually + * exclusive group won't be registered. If the platform has no mutually + * exclusive C-states, this parameter has no effect. + */ +static unsigned int __ro_after_init preferred_states_mask; +static char __initdata preferred_states[64]; +string_param("preferred-cstates", preferred_states); + #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF /* Reliable LAPIC Timer States, bit 1 for C1 etc. Default to only C1. */ static unsigned int lapic_timer_reliable_states = (1 << 1); +enum c1e_promotion { + C1E_PROMOTION_PRESERVE, + C1E_PROMOTION_ENABLE, + C1E_PROMOTION_DISABLE +}; + struct idle_cpu { const struct cpuidle_state *state_table; @@ -95,7 +114,7 @@ struct idle_cpu { */ unsigned long auto_demotion_disable_flags; bool byt_auto_demotion_disable_flag; - bool disable_promotion_to_c1e; + enum c1e_promotion c1e_promotion; }; static const struct idle_cpu *icpu; @@ -924,6 +943,15 @@ static void cf_check byt_auto_demotion_d wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); } +static void cf_check c1e_promotion_enable(void *dummy) +{ + uint64_t msr_bits; + + rdmsrl(MSR_IA32_POWER_CTL, msr_bits); + msr_bits |= 0x2; + wrmsrl(MSR_IA32_POWER_CTL, msr_bits); +} + static void cf_check c1e_promotion_disable(void *dummy) { u64 msr_bits; @@ -936,7 +964,7 @@ static void cf_check c1e_promotion_disab static const struct idle_cpu idle_cpu_nehalem = { .state_table = nehalem_cstates, .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static const struct idle_cpu idle_cpu_atom = { @@ -954,64 +982,64 @@ static const struct idle_cpu idle_cpu_li static const struct idle_cpu idle_cpu_snb = { .state_table = snb_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static const struct idle_cpu idle_cpu_byt = { .state_table = byt_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, .byt_auto_demotion_disable_flag = true, }; static const struct idle_cpu idle_cpu_cht = { .state_table = cht_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, .byt_auto_demotion_disable_flag = true, }; static const struct idle_cpu idle_cpu_ivb = { .state_table = ivb_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static const struct idle_cpu idle_cpu_ivt = { .state_table = ivt_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static const struct idle_cpu idle_cpu_hsw = { .state_table = hsw_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static const struct idle_cpu idle_cpu_bdw = { .state_table = bdw_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static const struct idle_cpu idle_cpu_skl = { .state_table = skl_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static const struct idle_cpu idle_cpu_skx = { .state_table = skx_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static const struct idle_cpu idle_cpu_icx = { .state_table = icx_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static struct idle_cpu __read_mostly idle_cpu_spr = { .state_table = spr_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static const struct idle_cpu idle_cpu_avn = { .state_table = avn_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static const struct idle_cpu idle_cpu_knl = { @@ -1020,17 +1048,17 @@ static const struct idle_cpu idle_cpu_kn static const struct idle_cpu idle_cpu_bxt = { .state_table = bxt_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static const struct idle_cpu idle_cpu_dnv = { .state_table = dnv_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; static const struct idle_cpu idle_cpu_snr = { .state_table = snr_cstates, - .disable_promotion_to_c1e = true, + .c1e_promotion = C1E_PROMOTION_DISABLE, }; #define ICPU(model, cpu) \ @@ -1241,6 +1269,25 @@ static void __init skx_idle_state_table_ } /* + * spr_idle_state_table_update - Adjust Sapphire Rapids idle states table. + */ +static void __init spr_idle_state_table_update(void) +{ + /* Check if user prefers C1E over C1. */ + if (preferred_states_mask & BIT(2, U)) { + if (preferred_states_mask & BIT(1, U)) + /* Both can't be enabled, stick to the defaults. */ + return; + + spr_cstates[0].flags |= CPUIDLE_FLAG_DISABLED; + spr_cstates[1].flags &= ~CPUIDLE_FLAG_DISABLED; + + /* Request enabling C1E using the "C1E promotion" bit. */ + idle_cpu_spr.c1e_promotion = C1E_PROMOTION_ENABLE; + } +} + +/* * mwait_idle_state_table_update() * * Update the default state_table for this CPU-id @@ -1261,6 +1308,9 @@ static void __init mwait_idle_state_tabl case INTEL_FAM6_SKYLAKE_X: skx_idle_state_table_update(); break; + case INTEL_FAM6_SAPPHIRERAPIDS_X: + spr_idle_state_table_update(); + break; } } @@ -1268,6 +1318,7 @@ static int __init mwait_idle_probe(void) { unsigned int eax, ebx, ecx; const struct x86_cpu_id *id = x86_match_cpu(intel_idle_ids); + const char *str; if (!id) { pr_debug(PREFIX "does not run on family %d model %d\n", @@ -1309,6 +1360,39 @@ static int __init mwait_idle_probe(void) pr_debug(PREFIX "lapic_timer_reliable_states %#x\n", lapic_timer_reliable_states); + str = preferred_states; + if (isdigit(str[0])) + preferred_states_mask = simple_strtoul(str, &str, 0); + else if (str[0]) + { + const char *ss; + + do { + const struct cpuidle_state *state = icpu->state_table; + unsigned int bit = 1; + + ss = strchr(str, ','); + if (!ss) + ss = strchr(str, '\0'); + + for (; state->name[0]; ++state) { + bit <<= 1; + if (!cmdline_strcmp(str, state->name)) { + preferred_states_mask |= bit; + break; + } + } + if (!state->name[0]) + break; + + str = ss + 1; + } while (*ss); + + str -= str == ss + 1; + } + if (str[0]) + printk("unrecognized \"preferred-cstates=%s\"\n", str); + mwait_idle_state_table_update(); return 0; @@ -1400,8 +1484,18 @@ static int cf_check mwait_idle_cpu_init( if (icpu->byt_auto_demotion_disable_flag) on_selected_cpus(cpumask_of(cpu), byt_auto_demotion_disable, NULL, 1); - if (icpu->disable_promotion_to_c1e) + switch (icpu->c1e_promotion) { + case C1E_PROMOTION_DISABLE: on_selected_cpus(cpumask_of(cpu), c1e_promotion_disable, NULL, 1); + break; + + case C1E_PROMOTION_ENABLE: + on_selected_cpus(cpumask_of(cpu), c1e_promotion_enable, NULL, 1); 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Signed-off-by: Artem Bityutskiy Signed-off-by: Rafael J. Wysocki Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 3a9cf77b60dc Make sure a contradictory "preferred-cstates" wouldn't cause bypassing of the added logic. Signed-off-by: Jan Beulich Acked-by: Roger Pau Monné --- v2: Sync with the Linux side fix to the noticed issue. Re-base over change to earlier patch. --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1273,18 +1273,31 @@ static void __init skx_idle_state_table_ */ static void __init spr_idle_state_table_update(void) { - /* Check if user prefers C1E over C1. */ - if (preferred_states_mask & BIT(2, U)) { - if (preferred_states_mask & BIT(1, U)) - /* Both can't be enabled, stick to the defaults. */ - return; + uint64_t msr; + /* Check if user prefers C1E over C1. */ + if (preferred_states_mask & BIT(2, U) && + !(preferred_states_mask & BIT(1, U))) { + /* Disable C1 and enable C1E. */ spr_cstates[0].flags |= CPUIDLE_FLAG_DISABLED; spr_cstates[1].flags &= ~CPUIDLE_FLAG_DISABLED; /* Request enabling C1E using the "C1E promotion" bit. */ idle_cpu_spr.c1e_promotion = C1E_PROMOTION_ENABLE; } + + /* + * By default, the C6 state assumes the worst-case scenario of package + * C6. However, if PC6 is disabled, we update the numbers to match + * core C6. + */ + rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr); + + /* Limit value 2 and above allow for PC6. */ + if ((msr & 0x7) < 2) { + spr_cstates[2].exit_latency = 190; + spr_cstates[2].target_residency = 600; + } } /*