From patchwork Thu Jun 2 14:11:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: wen.ping.teh@intel.com X-Patchwork-Id: 12867913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 741AFC433EF for ; Thu, 2 Jun 2022 14:13:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=x6G1NPXs3KSfAHMLR9VecJkTd1JbQVEnGjJIrIvqpS0=; b=MqVXWQKqsyoZbD Ekd8GuQ7h3rebtkiYo2UcK+JFLgzSCZuFmukCSh7CNLxjMmnw85xxQbRjQ3zx2hFFvjyr8fQH6EVh T/NGgFuMyrNsrtPSkrlwPx3U9PZLBmRe9chBzCLhVZGp9CkitYRg+XzV8IIgvbpoY72R6Ywttkhi0 ghx49LEzVUoo1zIDkxN+UAq6fHJ4Wlw8Lw5KaRHgL8OjViA6X65A2UASHkqZbfh+caXvlhOjEinGN B64v2JzlqI16wnIAtH3v+6FpOC9e8hVqZbL0nDRhmUGQtbKT7dtyfSf71hxSCM3//7uiBGFlRZ3NL yjtAwfn2rqC8gBPe/TiA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nwlYv-003WaB-9O; Thu, 02 Jun 2022 14:12:33 +0000 Received: from mga07.intel.com ([134.134.136.100]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nwlYr-003WZ9-IG for linux-arm-kernel@lists.infradead.org; Thu, 02 Jun 2022 14:12:31 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654179149; x=1685715149; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=KbrPrIvCS+mi/COhLEjYkOuQ96crZbeQdqbKiwSPa2c=; b=TH/93NfkG/virwtkoQ3Nb67P4WjcAiRzLFf5Vl93xGI9yWpABcbNAcPa ctfqEmZ/icFKR4SpWVyVdGy/5VSzWRZC5dkF/+L/10UVQa5gD/bMvdN1r c2o6+m6D/pwpfbIPuHxK8XRWACH24v96BTuj1MK6kCJDYbM3yqeU5Nczn pH6dgkBTK1UV/Mi1jOC5TT78l6ZaeJGD5o4GvANoIScpNnXkngwoX9Beu AC48ZHhC9BkzSam8rdsYJ+iZNMij2O4Aol4Gzh1XoKgp/rNjiCOeX3dKO EDeMIQmK/TnfwPNQm8N9E6sRCHfLkkphAI7avSVjfKD3hkDW7GvvSFJ6x g==; X-IronPort-AV: E=McAfee;i="6400,9594,10365"; a="339005003" X-IronPort-AV: E=Sophos;i="5.91,271,1647327600"; d="scan'208";a="339005003" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2022 07:12:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,271,1647327600"; d="scan'208";a="707580844" Received: from unknown (HELO localhost.localdomain) ([10.226.216.116]) by orsmga004.jf.intel.com with ESMTP; 02 Jun 2022 07:12:23 -0700 From: wen.ping.teh@intel.com To: Catalin Marinas , Will Deacon , Dinh Nguyen , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Teh Wen Ping Subject: [PATCH v2] arm64: dts: Add support for Stratix 10 Software Virtual Platform Date: Thu, 2 Jun 2022 22:11:51 +0800 Message-Id: <20220602141151.3431212-1-wen.ping.teh@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220602_071229_725559_62299A7E X-CRM114-Status: GOOD ( 14.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Teh Wen Ping Add Stratix 10 Software Virtual Platform device tree Signed-off-by: Teh Wen Ping --- changes in v2: -remove indentation before GPL -change root compatible to "altr,socfpga-stratix10" -remove bootargs -move clock-frequency to label -remove l2-cache -remove no longer exist authors from commit message arch/arm64/Kconfig.platforms | 3 +- arch/arm64/boot/dts/altera/Makefile | 3 +- .../dts/altera/socfpga_stratix10_swvp.dts | 117 ++++++++++++++++++ 3 files changed, 121 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index de9a18d3026f..48abe5dafaae 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -249,7 +249,8 @@ config ARCH_INTEL_SOCFPGA bool "Intel's SoCFPGA ARMv8 Families" help This enables support for Intel's SoCFPGA ARMv8 families: - Stratix 10 (ex. Altera), Agilex and eASIC N5X. + Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform, + Agilex and eASIC N5X. config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile index 4db83fbeb115..1bf0c472f6b4 100644 --- a/arch/arm64/boot/dts/altera/Makefile +++ b/arch/arm64/boot/dts/altera/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \ - socfpga_stratix10_socdk_nand.dtb + socfpga_stratix10_socdk_nand.dtb \ + socfpga_stratix10_swvp.dtb diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts new file mode 100644 index 000000000000..93fa5091a6c3 --- /dev/null +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022, Intel Corporation + */ + +#include "socfpga_stratix10.dtsi" + +/ { + model = "SOCFPGA Stratix 10 SWVP"; + compatible = "altr,socfpga-stratix10"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial1:115200n8"; + linux,initrd-start = <0x10000000>; + linux,initrd-end = <0x125c8324>; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&cpu0 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu1 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu2 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu3 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; + snps,max-mtu = <0x0>; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; +}; + +&mmc { + status = "okay"; + altr,dw-mshc-ciu-div = <0x3>; + altr,dw-mshc-sdr-timing = <0x0 0x3>; + cap-sd-highspeed; + cap-mmc-highspeed; + broken-cd; + bus-width = <4>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + clocks = <&clkmgr STRATIX10_L4_MP_CLK>; + status = "okay"; +}; + +&usb1 { + clocks = <&clkmgr STRATIX10_L4_MP_CLK>; + status = "okay"; +}; + +&rst { + altr,modrst-offset = <0x20>; +}; + +&sysmgr { + reg = <0xffd12000 0x1000>; + interrupts = <0x0 0x10 0x4>; + cpu1-start-addr = <0xffd06230>; +};