From patchwork Fri Jun 3 12:18:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 12869031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCAFEC433EF for ; Fri, 3 Jun 2022 12:20:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IpR0eEheLSWbk4c2LE1GSyMXsx4YWXtSoT3gP1xuoa0=; b=3wG8GlRknTWIsW bqy3lFthD75LVBofEqSOis8wPKpZGXqDrdTAB6abJ2wDuOiuiZOt7pHvbPVurJlYnV0VpCoLMx84W A0+1EsntpTkz4QQ3zhtYT9+CkHAxa/zSA9nSvWXZNafMMMuFMHic1YOiCigGmZRkFQDJrF45JsrES GWh5fXBfhrIZzFgX3QbRsdwU7Sg1fIZYO2lg2kzgCOU6WtH1Qjk224F0+t+5lhqjLEeKDPcDaihFe AlhKtRVS8WyVlBtePFgGaxsVzL4OpwV2RN5e/ork9YgNpSndv37gIeXq4VIVBwLuXzbbAZJ0NC+OR dzEvnCLOTXhqE7yjj2Bg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nx6H6-007NSb-RV; Fri, 03 Jun 2022 12:19:32 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nx6Gm-007NJ2-Sa for linux-arm-kernel@lists.infradead.org; Fri, 03 Jun 2022 12:19:15 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1654258752; x=1685794752; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=PaFP5mS7LABI5rntg90MTdxCG7GQMNKGnnTXLwJ4g3Q=; b=T5K1F/2fgGD2SZCqsNanfAsiJ1dZf+OtvT1n02W+FlFGn3sJvCCPttL0 T2/UNXhOjDmWQD91uDpRz2oonFzzmvVHLcm/wuBQPuFKq2tP+z/hOXUC4 10jAJJSRNOppL1TjgWxGxXyDoX1BS74h8jUS8b81FQbW5YH904J43m3Ls 3L7TNA2oTWZyjyfy3LU0zrWHOXQ5zbgJ3B8l/XHHxcRgKdIKmoArwZcFv N+skhy68HXz/bpEKO0svqGF5jhqwM6z/RLsYOnY+XKL/WBGtiS1H8YObA fGnjQNTLQmJHg8xgv/Xy42NTVZRyChopdLS4HdJY1a2p9H8OjMtJxY3IH w==; X-IronPort-AV: E=Sophos;i="5.91,274,1647327600"; d="scan'208";a="176409992" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2022 05:19:09 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 3 Jun 2022 05:19:09 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 3 Jun 2022 05:19:05 -0700 From: Kavyasree Kotagiri To: , , , , , CC: , , , Subject: [PATCH 1/3] dt-bindings: mfd: atmel,flexcom: Convert to json-schema Date: Fri, 3 Jun 2022 17:48:00 +0530 Message-ID: <20220603121802.30320-2-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220603121802.30320-1-kavyasree.kotagiri@microchip.com> References: <20220603121802.30320-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220603_051913_023605_FAA3C93C X-CRM114-Status: GOOD ( 17.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert the Atmel flexcom device tree bindings to json schema. Signed-off-by: Kavyasree Kotagiri --- .../bindings/mfd/atmel,flexcom.yaml | 97 +++++++++++++++++++ .../devicetree/bindings/mfd/atmel-flexcom.txt | 63 ------------ 2 files changed, 97 insertions(+), 63 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-flexcom.txt diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml new file mode 100644 index 000000000000..221bd840b49e --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,flexcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit) + +maintainers: + - Kavyasree Kotagiri + +description: + The Atmel Flexcom is just a wrapper which embeds a SPI controller, + an I2C controller and an USART. Only one function can be used at a + time and is chosen at boot time according to the device tree. + +properties: + compatible: + const: atmel,sama5d2-flexcom + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + description: + One range for the full I/O register region. (including USART, + TWI and SPI registers). + items: + maxItems: 3 + + atmel,flexcom-mode: + description: | + Specifies the flexcom mode as follows: + 1: USART + 2: SPI + 3: I2C. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + +patternProperties: + "^serial@[0-9a-f]+$": + description: See atmel-usart.txt for details of USART bindings. + type: object + + "^spi@[0-9a-f]+$": + description: See ../spi/spi_atmel.txt for details of SPI bindings. + type: object + + "^i2c@[0-9a-f]+$": + description: See ../i2c/i2c-at91.txt for details of I2C bindings. + type: object + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + - ranges + - atmel,flexcom-mode + +additionalProperties: false + +examples: + - | + flx0: flexcom@f8034000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8034000 0x200>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8034000 0x800>; + atmel,flexcom-mode = <2>; + + spi0: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <19 4 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx0_default>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&flx0_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt deleted file mode 100644 index 9d837535637b..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ /dev/null @@ -1,63 +0,0 @@ -* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit) - -The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C -controller and an USART. Only one function can be used at a time and is chosen -at boot time according to the device tree. - -Required properties: -- compatible: Should be "atmel,sama5d2-flexcom" -- reg: Should be the offset/length value for Flexcom dedicated - I/O registers (without USART, TWI or SPI registers). -- clocks: Should be the Flexcom peripheral clock from PMC. -- #address-cells: Should be <1> -- #size-cells: Should be <1> -- ranges: Should be one range for the full I/O register region - (including USART, TWI and SPI registers). -- atmel,flexcom-mode: Should be one of the following values: - - <1> for USART - - <2> for SPI - - <3> for I2C - -Required child: -A single available child device of type matching the "atmel,flexcom-mode" -property. - -The phandle provided by the clocks property of the child is the same as one for -the Flexcom parent. - -For other properties, please refer to the documentations of the respective -device: -- ../serial/atmel-usart.txt -- ../spi/spi_atmel.txt -- ../i2c/i2c-at91.txt - -Example: - -flexcom@f8034000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8034000 0x200>; - clocks = <&flx0_clk>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8034000 0x800>; - atmel,flexcom-mode = <2>; - - spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&flx0_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <32>; - - flash@0 { - compatible = "atmel,at25f512b"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; -}; From patchwork Fri Jun 3 12:18:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 12869032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A730C43334 for ; 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03 Jun 2022 05:19:15 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 3 Jun 2022 05:19:14 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 3 Jun 2022 05:19:11 -0700 From: Kavyasree Kotagiri To: , , , , , CC: , , , Subject: [PATCH 2/3] dt-bindings: mfd: atmel,flexcom: Add new compatible string for lan966x Date: Fri, 3 Jun 2022 17:48:01 +0530 Message-ID: <20220603121802.30320-3-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220603121802.30320-1-kavyasree.kotagiri@microchip.com> References: <20220603121802.30320-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220603_051915_802350_99AADF7E X-CRM114-Status: UNSURE ( 9.74 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on functions being configured. Signed-off-by: Kavyasree Kotagiri --- .../bindings/mfd/atmel,flexcom.yaml | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml index 221bd840b49e..6050482ad8ef 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml @@ -16,7 +16,9 @@ description: properties: compatible: - const: atmel,sama5d2-flexcom + enum: + - atmel,sama5d2-flexcom + - microchip,lan966x-flexcom reg: maxItems: 1 @@ -46,6 +48,21 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 3] + microchip,flx-shrd-pins: + description: Specify the Flexcom shared pins to be used for flexcom + chip-selects. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 20 + + microchip,flx-cs-names: + description: Chip select names. "cts", "rts" for flexcom USART "CTS" and + "RTS" lines. "cs0", "cs1" for flexcom SPI chip-select lines. + items: + enum: [ cs0, cs1, cts, rts ] + minItems: 1 + maxItems: 2 + patternProperties: "^serial@[0-9a-f]+$": description: See atmel-usart.txt for details of USART bindings. @@ -80,6 +97,8 @@ examples: #size-cells = <1>; ranges = <0x0 0xf8034000 0x800>; atmel,flexcom-mode = <2>; + microchip,flx-shrd-pins = <9>; + microchip,flx-cs-names = "cs0"; spi0: spi@400 { compatible = "atmel,at91rm9200-spi"; From patchwork Fri Jun 3 12:18:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 12869033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 128D2C43334 for ; Fri, 3 Jun 2022 12:21:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OsmuUIkeFunu3A6bKZvclAqdZiO8qBfSyjQGAc+t3AU=; b=rHy1VxWJ7PgAfK ocAjppHNiQTz1SrA1/LSqonLsqHBZ3Cy0LwDkD7XbXzUi//R9mWsDCBLE9xMfeuN70Ob0f5IPJbH+ 5nOYhDDTLbwflZ1uMy6X0TzNR2fPwAdztVtWDPJEG5JV7MAYJtmkw+XHowuYwOyEXCBZnj80FD8KL ZRs7nV83hUGDJJM/k0ahp/Q/z8KntdB0THxXIpZt1YgIVN5CBlv48zKhXp267HJEgj2gluY+9pIRs pmHc08ymOB+Piu3nToZgC189jqx//C6ajfSkj9PR1KV55tkpz72HEL+CrWDYRX9tInXAlVekgeQwW A9LAJPpZcu67IOuh3Reg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nx6I2-007NpP-2I; Fri, 03 Jun 2022 12:20:30 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nx6Gw-007NNu-FL for linux-arm-kernel@lists.infradead.org; Fri, 03 Jun 2022 12:19:24 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1654258762; x=1685794762; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=vPjtyYVg+EEiabNmG8qMLL1Ibfw++Ug4T0dSA+weyig=; b=o/Zk34jyEz5qD4lBhMMOtEohzzCGzUGZwiNFw7D2UkXM6qk08tvKZXWK LXmecfep361we/6jpBXAy0RlU1krKatcwXNMn7XdKH2DOf0BL2gcmOa5s lc6L26okWGs+75alc2EcE5d3b37U/92cxLIUC7cW6iHWOGVC4qTl93TUh G/hDNUriiwvDtEIzNmqUVd7oWozP38OFV4RJ1JzAfTl8FCy1NEJ3YCGJ6 zEFoKKv4I78F6pcL7IJxRTVnh/JDOTyvz+j8z2scSbf793vCWt+nySxA+ skBwZXZQ28Id9FKwOZCACHSibAe3TKyOJGc2YCiFP5JNBl0O3MwmhZPkU g==; X-IronPort-AV: E=Sophos;i="5.91,274,1647327600"; d="scan'208";a="98453581" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2022 05:19:21 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 3 Jun 2022 05:19:21 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 3 Jun 2022 05:19:17 -0700 From: Kavyasree Kotagiri To: , , , , , CC: , , , Subject: [PATCH 3/3] mfd: atmel-flexcom: Add support for lan966x flexcom chip-select configuration Date: Fri, 3 Jun 2022 17:48:02 +0530 Message-ID: <20220603121802.30320-4-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220603121802.30320-1-kavyasree.kotagiri@microchip.com> References: <20220603121802.30320-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220603_051922_677622_540F4CB8 X-CRM114-Status: GOOD ( 18.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org LAN966x SoC have 5 flexcoms. Each flexcom has 2 chip-selects. For each chip select of each flexcom there is a configuration register FLEXCOM_SHARED[0-4]:SS_MASK[0-1]. The width of configuration register is 21 because there are 21 shared pins on each of which the chip select can be mapped. Each bit of the register represents a different FLEXCOM_SHARED pin. Signed-off-by: Kavyasree Kotagiri --- drivers/mfd/atmel-flexcom.c | 86 ++++++++++++++++++++++++++++++++++++- 1 file changed, 84 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c index 33caa4fba6af..f87ee3606eb0 100644 --- a/drivers/mfd/atmel-flexcom.c +++ b/drivers/mfd/atmel-flexcom.c @@ -28,15 +28,64 @@ #define FLEX_MR_OPMODE(opmode) (((opmode) << FLEX_MR_OPMODE_OFFSET) & \ FLEX_MR_OPMODE_MASK) +/* LAN966x flexcom shared register offsets */ +#define FLEX_SHRD_SS_MASK_0 0x0 +#define FLEX_SHRD_SS_MASK_1 0x4 +#define FLEX_SHRD_MASK 0x1FFFFF + +struct atmel_flex_caps { + bool has_flx_cs; +}; + struct atmel_flexcom { - void __iomem *base; + void __iomem *base, *flexcom_shared_base; u32 opmode; struct clk *clk; }; +static int atmel_flexcom_lan966x_cs_config(struct platform_device *pdev) +{ + struct atmel_flexcom *ddata = dev_get_drvdata(&pdev->dev); + struct device_node *np = pdev->dev.of_node; + u32 flx_shrd_pins[2], val; + int err, i, count; + + count = of_property_count_u32_elems(np, "microchip,flx-shrd-pins"); + if (count <= 0 || count > 2) { + dev_err(&pdev->dev, "Invalid %s property (%d)\n", "flx-shrd-pins", + count); + return -EINVAL; + } + + err = of_property_read_u32_array(np, "microchip,flx-shrd-pins", flx_shrd_pins, count); + if (err) + return err; + + for (i = 0; i < count; i++) { + const char *flx_cs; + + if (flx_shrd_pins[i] > 20) + return -EINVAL; + + val = ~(1 << flx_shrd_pins[i]) & FLEX_SHRD_MASK; + + err = of_property_read_string_index(np, "microchip,flx-cs", i, &flx_cs); + if (err) + return err; + + if (!strcmp(flx_cs, "cs0") || !strcmp(flx_cs, "cts")) + writel(val, ddata->flexcom_shared_base + FLEX_SHRD_SS_MASK_0); + else if (!strcmp(flx_cs, "cs1") || !strcmp(flx_cs, "rts")) + writel(val, ddata->flexcom_shared_base + FLEX_SHRD_SS_MASK_1); + } + + return 0; +} + static int atmel_flexcom_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; + const struct atmel_flex_caps *caps; struct resource *res; struct atmel_flexcom *ddata; int err; @@ -76,13 +125,46 @@ static int atmel_flexcom_probe(struct platform_device *pdev) */ writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR); + caps = of_device_get_match_data(&pdev->dev); + if (!caps) { + dev_err(&pdev->dev, "Could not retrieve flexcom caps\n"); + return -EINVAL; + } + + if (caps->has_flx_cs) { + ddata->flexcom_shared_base = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); + if (IS_ERR(ddata->flexcom_shared_base)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ddata->flexcom_shared_base), + "failed to get flexcom shared base address\n"); + + err = atmel_flexcom_lan966x_cs_config(pdev); + if (err) + return err; + } + clk_disable_unprepare(ddata->clk); return devm_of_platform_populate(&pdev->dev); } +static const struct atmel_flex_caps atmel_flexcom_caps = {}; + +static const struct atmel_flex_caps lan966x_flexcom_caps = { + .has_flx_cs = true, +}; + static const struct of_device_id atmel_flexcom_of_match[] = { - { .compatible = "atmel,sama5d2-flexcom" }, + { + .compatible = "atmel,sama5d2-flexcom", + .data = &atmel_flexcom_caps, + }, + + { + .compatible = "microchip,lan966x-flexcom", + .data = &lan966x_flexcom_caps, + }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match);