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Fri, 03 Jun 2022 09:33:47 -0700 (PDT) Received: from localhost ([12.3.194.138]) by smtp.gmail.com with ESMTPSA id h9-20020ac85e09000000b002f93c5444e3sm5481315qtx.52.2022.06.03.09.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jun 2022 09:33:46 -0700 (PDT) Date: Fri, 03 Jun 2022 09:33:46 -0700 (PDT) X-Google-Original-Date: Fri, 03 Jun 2022 09:33:44 PDT (-0700) Subject: [GIT PULL] RISC-V Patches for the 5.19 Merge Window, Part 2 CC: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org From: Palmer Dabbelt To: Linus Torvalds Message-ID: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220603_093352_615077_B1A97BCF X-CRM114-Status: GOOD ( 11.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org merged tag 'riscv-for-linus-5.19-mw0' The following changes since commit 35b51afd23c98e2f055ac563aca36173a12588b9: Merge tag 'riscv-for-linus-5.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux (2022-05-31 14:10:54 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.19-mw2 for you to fetch changes up to 61114e734ccb804bc12561ab4020745e02c468c2: riscv: Move alternative length validation into subsection (2022-06-02 15:55:22 -0700) ---------------------------------------------------------------- RISC-V Patches for the 5.19 Merge Window, Part 2 This is mostly some DT updates, but also a handful of cleanups and some fixes. The most user-visible of those are: * A device tree for the Sundance Polarberry, along with a handful of fixes and clenups to the PolarFire SOC device trees and bindings. * The memfd_secret syscall number is now visible to userspace, * Some improvements to the vm layout dump, which really should have followed shortly after the sv48 patches but I missed. ---------------------------------------------------------------- Alexandre Ghiti (3): Documentation: riscv: Add sv48 description to VM layout riscv: Initialize thread pointer before calling C functions riscv: Improve virtual kernel memory layout dump Conor Dooley (10): riscv: dts: microchip: remove icicle memory clocks riscv: dts: microchip: move sysctrlr out of soc bus riscv: dts: microchip: remove soc vendor from filenames dt-bindings: riscv: microchip: document icicle reference design riscv: dts: microchip: make the fabric dtsi board specific dt-bindings: vendor-prefixes: add Sundance DSP dt-bindings: riscv: microchip: add polarberry compatible string riscv: dts: microchip: add the sundance polarberry riscv: microchip: icicle: readability fixes riscv: dts: icicle: sort nodes alphabetically Jisheng Zhang (1): riscv: mm: init: make pt_ops_set_[early|late|fixmap] static Masahiro Yamada (1): riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild Nathan Chancellor (1): riscv: Move alternative length validation into subsection Palmer Dabbelt (2): RISC-V: PolarFire SoC Device Tree Updates RISC-V: Only default to spinwait on SBI-0.1 and M-mode Samuel Holland (1): riscv: Fix irq_work when SMP is disabled Tobias Klauser (1): riscv: Wire up memfd_secret in UAPI header Xianting Tian (1): RISC-V: Mark IORESOURCE_EXCLUSIVE for reserved mem instead of IORESOURCE_BUSY .../devicetree/bindings/riscv/microchip.yaml | 2 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + Documentation/riscv/vm-layout.rst | 36 +++++++ arch/riscv/Kbuild | 2 + arch/riscv/Kconfig | 8 +- arch/riscv/Makefile | 3 - arch/riscv/boot/dts/microchip/Makefile | 3 +- ...pfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 + ...hip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 105 +++++++++++---------- .../boot/dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++ arch/riscv/boot/dts/microchip/mpfs-polarberry.dts | 99 +++++++++++++++++++ .../microchip/{microchip-mpfs.dtsi => mpfs.dtsi} | 11 +-- arch/riscv/include/asm/alternative-macros.h | 4 +- arch/riscv/include/asm/irq_work.h | 2 +- arch/riscv/include/asm/unistd.h | 1 - arch/riscv/include/uapi/asm/unistd.h | 1 + arch/riscv/kernel/head.S | 1 + arch/riscv/kernel/setup.c | 4 +- arch/riscv/mm/init.c | 72 ++++++++++---- 19 files changed, 287 insertions(+), 87 deletions(-) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%)