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Sun, 5 Jun 2022 23:25:30 -0700 Envelope-to: git@xilinx.com, broonie@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [10.140.6.18] (port=43118 helo=xhdlakshmis40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1ny6B8-0007aL-1H; Sun, 05 Jun 2022 23:25:30 -0700 From: Amit Kumar Mahapatra To: CC: , , , Sai Krishna Potthuri , Amit Kumar Mahapatra Subject: [PATCH] spi: spi-cadence: Fix SPI CS gets toggling sporadically Date: Mon, 6 Jun 2022 11:55:25 +0530 Message-ID: <20220606062525.18447-1-amit.kumar-mahapatra@xilinx.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8ef5f96d-bd3d-474d-b299-08da47855b79 X-MS-TrafficTypeDiagnostic: PH0PR02MB8550:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Sxpsj1eneA0qCPcczWhle8U2qvQd/1wuZ4yzCe3SZEGdhI+swKVKYk7Cbc+QI9t2sdcQerZC6KJzwjS9uVCm4wPvR8O4urol2k5gmclAHfnTg/XGbDFYEpg99Ks4lF9T8l5Si/CgrXTUGR0gyaoxpok+gNsuB9zzHdsvBiHt9kRe21SOPhHB2L60+Sobmy03YQbOBmFGE8O8Pmv6IO6O9SoGlSZYEWGiMQw2HVSfXey3+ky5rhlB01aUG6lTdJUWOnRSEgTxKuI79pLHZKoXfNDs9XKHEkEPLrLsjO/Bz33HcQsx0f6UcVeGrWBSr4VhWkYPNLLX8tb8fzbhDw9tX2Og6GtcbEXCv6yh/o8+z8RE2ewZllLiVJRzH2eAmTD7QQKg3Cs4RLxs10NXCenBcCVnR5P+WESUYkyDb1dlmRZ8T+BQUhh9nzkaF+vjXjauZp1weWOiICm6pwRBrYwu6KfQvfkpTrSlF6nwRVCYgAVXoEw3+7ztJ4DAY+qJGkpJkQSpXo/r1zzXHBhqNEPdKdn8SWqHCzz9xqiq8/TIDlYPj9f5SlAzsBQuBW3VdeXu428ud+a6plkRyaixQ1MZ6HPJc35ujVifhE49i7LrE1QK0+pAXe71jcgkvweHv2emLyCV6aYGUf0cyIeQjag+bltfr5m1qZzeN4L46xeccBwphschNWkrCXds/BjY6Tyu4MRQLjTSOoc+X+k7EtzbLw== X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch02.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(36756003)(6916009)(7636003)(54906003)(508600001)(9786002)(356005)(83380400001)(8936002)(316002)(5660300002)(26005)(107886003)(2616005)(2906002)(70586007)(1076003)(186003)(70206006)(36860700001)(8676002)(47076005)(336012)(426003)(4326008)(40460700003)(6666004)(82310400005)(7696005)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 06:25:31.6333 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ef5f96d-bd3d-474d-b299-08da47855b79 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT050.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR02MB8550 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Sai Krishna Potthuri As part of unprepare_transfer_hardware, SPI controller will be disabled which will indirectly deassert the CS line. This will create a problem in some of the devices where message will be transferred with cs_change flag set(CS should not be deasserted). As per SPI controller implementation, if SPI controller is disabled then all output enables are inactive and all pins are set to input mode which means CS will go to default state high(deassert). This leads to an issue when core explicitly ask not to deassert the CS (cs_change = 1). This patch fix the above issue by checking the Slave select status bits from configuration register before disabling the SPI. Signed-off-by: Sai Krishna Potthuri Signed-off-by: Amit Kumar Mahapatra --- BRANCH: mtd/next --- drivers/spi/spi-cadence.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c index b509eefe16a8..e832ae09e0cd 100644 --- a/drivers/spi/spi-cadence.c +++ b/drivers/spi/spi-cadence.c @@ -69,6 +69,7 @@ #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */ #define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */ #define CDNS_SPI_SS0 0x1 /* Slave Select zero */ +#define CDNS_SPI_NOSS 0x3C /* No Slave select */ /* * SPI Interrupt Registers bit Masks @@ -449,15 +450,20 @@ static int cdns_prepare_transfer_hardware(struct spi_master *master) * @master: Pointer to the spi_master structure which provides * information about the controller. * - * This function disables the SPI master controller. + * This function disables the SPI master controller when no slave selected. * * Return: 0 always */ static int cdns_unprepare_transfer_hardware(struct spi_master *master) { struct cdns_spi *xspi = spi_master_get_devdata(master); + u32 ctrl_reg; - cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); + /* Disable the SPI if slave is deselected */ + ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); + ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT; + if (ctrl_reg == CDNS_SPI_NOSS) + cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); return 0; }