From patchwork Mon Jun 6 13:45:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 12870377 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72AC7CCA482 for ; Mon, 6 Jun 2022 13:46:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239065AbiFFNqR (ORCPT ); Mon, 6 Jun 2022 09:46:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239047AbiFFNqP (ORCPT ); Mon, 6 Jun 2022 09:46:15 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D5A11C2D60 for ; Mon, 6 Jun 2022 06:46:14 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id gl15so15207065ejb.4 for ; Mon, 06 Jun 2022 06:46:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hM/8L0QQElJsG/ZP5E7Xm7971VYDngZ9OkzPm4OYvuE=; b=OJs8LpvrKqi5Cd/dGV4X9s3P+/ySjRV6bVK4kcv4eoRQDVu8BWaMoFAMh81BUHldVs L3JfVc21sD/XqfokWo0cpvMxm3hbVeaFI0Jt693xfKSsG6dbpulwLsu2EYZQ/KJGHyBu Qh4dcbTDjxCnrY9P+TvPwLihtKe6DfBR+dL9o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hM/8L0QQElJsG/ZP5E7Xm7971VYDngZ9OkzPm4OYvuE=; b=PTiJmsjIXflUzMkEjOBJ+f+XLHM7cXhKhD0hcgFUlHWwwb3sohO7JTnf4qmbz6w4CR 166p0eESQq9nZp7i9v6uyGmciDe6twQK/M3lJa30eILGEagXey3VCbbi5lzA4vY0u3Nc rIhDBmvaayz+Ror6PMvXdlNJqwbc12XiiVwlleFa2esTyDJkF7H9Ws30RYuGp3DxQUMl 1TxXHuDFTiN9A4rY0+j93mts9BRSsFTxyAKqY0EsZOze4nhmwa4kANSbuWNS/P1QKRS9 OXmHzNIj290w3ZTbyYrKyxb98YGbRKD9/16ZPRDOInRDXv/85sSOIbrzCE7LAuN98HEw U6MQ== X-Gm-Message-State: AOAM531TW6WkUwmXBM3SNncxoEW2D45yKt0ERCn/myg8V6bN1v8HxRQk RU70hJFnZsSBopvD8De6NrVevQ== X-Google-Smtp-Source: ABdhPJwDtrN5NZdSXdvq60ci2ZzH2UR8lC1o4NQ/iJefcuNGMyK/r2DHNkCOrIizzW/WLbjiNyv2CA== X-Received: by 2002:a17:907:7da5:b0:711:c9cd:61e0 with SMTP id oz37-20020a1709077da500b00711c9cd61e0mr6287983ejc.443.1654523172865; Mon, 06 Jun 2022 06:46:12 -0700 (PDT) Received: from localhost.localdomain (80.71.142.18.ipv4.parknet.dk. [80.71.142.18]) by smtp.gmail.com with ESMTPSA id a26-20020a1709062b1a00b006f3ef214db4sm5496538ejg.26.2022.06.06.06.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 06:46:12 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: luizluca@gmail.com, Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/5] net: dsa: realtek: rtl8365mb: rename macro RTL8367RB -> RTL8367RB_VB Date: Mon, 6 Jun 2022 15:45:49 +0200 Message-Id: <20220606134553.2919693-2-alvin@pqrs.dk> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220606134553.2919693-1-alvin@pqrs.dk> References: <20220606134553.2919693-1-alvin@pqrs.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Alvin Šipraga The official name of this switch is RTL8367RB-VB, not RTL8367RB. There is also an RTL8367RB-VC which is rather different. Change the name of the CHIP_ID/_VER macros for reasons of consistency. Signed-off-by: Alvin Šipraga Reviewed-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/rtl8365mb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c index 3bb42a9f236d..0cc90e96aab7 100644 --- a/drivers/net/dsa/realtek/rtl8365mb.c +++ b/drivers/net/dsa/realtek/rtl8365mb.c @@ -108,8 +108,8 @@ #define RTL8365MB_CHIP_ID_8367S 0x6367 #define RTL8365MB_CHIP_VER_8367S 0x00A0 -#define RTL8365MB_CHIP_ID_8367RB 0x6367 -#define RTL8365MB_CHIP_VER_8367RB 0x0020 +#define RTL8365MB_CHIP_ID_8367RB_VB 0x6367 +#define RTL8365MB_CHIP_VER_8367RB_VB 0x0020 /* Family-specific data and limits */ #define RTL8365MB_PHYADDRMAX 7 @@ -2008,7 +2008,7 @@ static int rtl8365mb_detect(struct realtek_priv *priv) "found an RTL8365MB-VC switch (ver=0x%04x)\n", chip_ver); break; - case RTL8365MB_CHIP_VER_8367RB: + case RTL8365MB_CHIP_VER_8367RB_VB: dev_info(priv->dev, "found an RTL8367RB-VB switch (ver=0x%04x)\n", chip_ver); From patchwork Mon Jun 6 13:45:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 12870378 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 674A2C43334 for ; Mon, 6 Jun 2022 13:46:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239189AbiFFNqW (ORCPT ); Mon, 6 Jun 2022 09:46:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239070AbiFFNqR (ORCPT ); Mon, 6 Jun 2022 09:46:17 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DEAA1B1865 for ; Mon, 6 Jun 2022 06:46:16 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id s12so21853421ejx.3 for ; Mon, 06 Jun 2022 06:46:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VYeSg1ZVJyO1wF6nKJrR5sFbD4VG+uA01p3eRJoARxI=; b=BlqD4OrH8ijJBv3g48jIRjkB144fnXNgPgxahFkUUCU2nkV1FJ0YTeVOOj6rlB/vJf 0muLJg/FvIipcuViQyVfJPAuh3IjsNCWXVCZnMFqFGgoV6hzjiRXYjmcOTCNR2FKFF9J 5FGB682nb6m9sUhEAK/HpPpQJmeLhkUYUJU48= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VYeSg1ZVJyO1wF6nKJrR5sFbD4VG+uA01p3eRJoARxI=; b=nHs1A6RSNIKDKB7JdA9cK4DjxR0+iUEYFjV7PnijlduwbBz02/HMJLRSR9pcSgmFMY aLlVqtPg5RZ104j9Ux5GxnUFXYnUE3NGRDDlNJjLWQFQrMB9d8xjiQECVbwXVqE5eYx0 uvmRLHlFkX0IL7HQ7/Tyosfq8KauuODplqAYREges39rqPXijsIA+xDowQAHSo6dyWop V2vCbxNVeHk3ZYHCZkHxADz+XwM2+rEvFdOSusd2AZhLZwWQfD0NQO7dTVEmC0ozh+WL kPBp4JwppG+JI2qwc/vT/f7rxAp6iVU7NVAcjXqRdc2vn4001hnNJXsPzaoJ+ZHX5ARL j90w== X-Gm-Message-State: AOAM532aK0D31GXiUH/n/5DRmsOOdtqRYXqJBDt/ZmxhoSmLtHXM/AJC mOJmXtU2ZrsS+3uyGRHPljwzqg== X-Google-Smtp-Source: ABdhPJyfCep4n7xquLlwy7AVxmn0xa/oWVEI+ZOZvyZi6iA+YjNd0eF+CH6vK89MeOD2mZ5kkia2AA== X-Received: by 2002:a17:907:1c8d:b0:6f2:eb2:1cd6 with SMTP id nb13-20020a1709071c8d00b006f20eb21cd6mr20960665ejc.568.1654523174637; Mon, 06 Jun 2022 06:46:14 -0700 (PDT) Received: from localhost.localdomain (80.71.142.18.ipv4.parknet.dk. [80.71.142.18]) by smtp.gmail.com with ESMTPSA id a26-20020a1709062b1a00b006f3ef214db4sm5496538ejg.26.2022.06.06.06.46.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 06:46:14 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: luizluca@gmail.com, Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/5] net: dsa: realtek: rtl8365mb: remove port_mask private data member Date: Mon, 6 Jun 2022 15:45:50 +0200 Message-Id: <20220606134553.2919693-3-alvin@pqrs.dk> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220606134553.2919693-1-alvin@pqrs.dk> References: <20220606134553.2919693-1-alvin@pqrs.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Alvin Šipraga There is no real need for this variable: the line change interrupt mask is sufficiently masked out when getting linkup_ind and linkdown_ind in the interrupt handler. Signed-off-by: Alvin Šipraga --- drivers/net/dsa/realtek/rtl8365mb.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c index 0cc90e96aab7..c64219271a2b 100644 --- a/drivers/net/dsa/realtek/rtl8365mb.c +++ b/drivers/net/dsa/realtek/rtl8365mb.c @@ -564,7 +564,6 @@ struct rtl8365mb_port { * @irq: registered IRQ or zero * @chip_id: chip identifier * @chip_ver: chip silicon revision - * @port_mask: mask of all ports * @learn_limit_max: maximum number of L2 addresses the chip can learn * @cpu: CPU tagging and CPU port configuration for this chip * @mib_lock: prevent concurrent reads of MIB counters @@ -579,7 +578,6 @@ struct rtl8365mb { int irq; u32 chip_id; u32 chip_ver; - u32 port_mask; u32 learn_limit_max; struct rtl8365mb_cpu cpu; struct mutex mib_lock; @@ -1540,7 +1538,7 @@ static irqreturn_t rtl8365mb_irq(int irq, void *data) linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val); - line_changes = (linkup_ind | linkdown_ind) & mb->port_mask; + line_changes = linkup_ind | linkdown_ind; } if (!line_changes) @@ -2029,7 +2027,6 @@ static int rtl8365mb_detect(struct realtek_priv *priv) mb->priv = priv; mb->chip_id = chip_id; mb->chip_ver = chip_ver; - mb->port_mask = GENMASK(priv->num_ports - 1, 0); mb->learn_limit_max = RTL8365MB_LEARN_LIMIT_MAX; mb->jam_table = rtl8365mb_init_jam_8365mb_vc; mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc); From patchwork Mon Jun 6 13:45:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 12870379 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 724F1C43334 for ; Mon, 6 Jun 2022 13:46:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239196AbiFFNqY (ORCPT ); Mon, 6 Jun 2022 09:46:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239181AbiFFNqS (ORCPT ); Mon, 6 Jun 2022 09:46:18 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B315E2A25F3 for ; Mon, 6 Jun 2022 06:46:17 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id fd25so18912894edb.3 for ; Mon, 06 Jun 2022 06:46:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BnPeSuEupDbmGQ7GCHy4it+pAl5TcIPr5v39wk3VDWY=; b=STlEAzxRwWbhrR37+QIghU6zligTbGACIocWguIbaXysVb7dqmW3Z161foAucHd9Fq WNIf8NieYkCmdcGQTS1p1cXcFVxm1KlqCanD4uHpbsnV0AbX8PW+G0J8vmPYJSKHPA6m z+Ou3/2aC6js2qQUDtJnp31U0ToUuhybLK5Qg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BnPeSuEupDbmGQ7GCHy4it+pAl5TcIPr5v39wk3VDWY=; b=e8hzCHKOwqj6DDeEfOzE9bWtfecjehZzWnIevNfih/Ik/mhlZkuJrghTcDbdf+IQYL SAjEL2u7+JDt7E05zA/nZLnQFk/ijYZOL/+i6NgqAGOrq4o2VR48ERi8KWj0D685jhiO h6iywRtR8SABYIhmLM6C0Zb2Dh7hp7Nd9KyLqoq0+bOAnDrsgYId4+FlUz770uCCw5d8 GD4O+rsws4fKOuZ/p1MRO8c3AH5wmsIW4D6e60RAOAMjdk5RIANwyBjkLVv3+VGxhQMW sBOQsWTQsvQWmIVk+Y24W3/NKCYQgZCk8gTdSP7vr5lM0MBe9RkmuUoiNIGMmiEGKHMK X0/w== X-Gm-Message-State: AOAM53129P7VTwhcT099S5kJ3kMeHOJc3ZN8BN6T9tnPkHIF7x/kU/4d biyk11oG84gwI1xCUqveeGZINw== X-Google-Smtp-Source: ABdhPJzUbpoI88p20ePtUpE/Efbx+rxctOBRmEkVhIGUkdBZ5Jl3JJOTojP18Va0VLSDZe/khPlZFw== X-Received: by 2002:a05:6402:1941:b0:413:2822:9c8 with SMTP id f1-20020a056402194100b00413282209c8mr27443321edz.13.1654523176298; Mon, 06 Jun 2022 06:46:16 -0700 (PDT) Received: from localhost.localdomain (80.71.142.18.ipv4.parknet.dk. [80.71.142.18]) by smtp.gmail.com with ESMTPSA id a26-20020a1709062b1a00b006f3ef214db4sm5496538ejg.26.2022.06.06.06.46.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 06:46:15 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: luizluca@gmail.com, Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 3/5] net: dsa: realtek: rtl8365mb: correct the max number of ports Date: Mon, 6 Jun 2022 15:45:51 +0200 Message-Id: <20220606134553.2919693-4-alvin@pqrs.dk> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220606134553.2919693-1-alvin@pqrs.dk> References: <20220606134553.2919693-1-alvin@pqrs.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Alvin Šipraga The maximum number of ports is actually 11, according to two observations: 1. The highest port ID used in the vendor driver is 10. Since port IDs are indexed from 0, and since DSA follows the same numbering system, this means up to 11 ports are to be presumed. 2. The registers with port mask fields always amount to a maximum port mask of 0x7FF, corresponding to a maximum 11 ports. In view of this, I also deleted the comment. Signed-off-by: Alvin Šipraga Reviewed-by: Luiz Angelo Daros de Luca --- drivers/net/dsa/realtek/rtl8365mb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c index c64219271a2b..392047558656 100644 --- a/drivers/net/dsa/realtek/rtl8365mb.c +++ b/drivers/net/dsa/realtek/rtl8365mb.c @@ -115,8 +115,7 @@ #define RTL8365MB_PHYADDRMAX 7 #define RTL8365MB_NUM_PHYREGS 32 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1) -/* RTL8370MB and RTL8310SR, possibly suportable by this driver, have 10 ports */ -#define RTL8365MB_MAX_NUM_PORTS 10 +#define RTL8365MB_MAX_NUM_PORTS 11 #define RTL8365MB_LEARN_LIMIT_MAX 2112 /* valid for all 6-port or less variants */ From patchwork Mon Jun 6 13:45:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 12870380 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B594AC43334 for ; Mon, 6 Jun 2022 13:46:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239224AbiFFNqs (ORCPT ); Mon, 6 Jun 2022 09:46:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239184AbiFFNqU (ORCPT ); Mon, 6 Jun 2022 09:46:20 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4C3D2B1956 for ; Mon, 6 Jun 2022 06:46:19 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id u12so29081569eja.8 for ; Mon, 06 Jun 2022 06:46:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uHwQH74Q7N25Q2zdI6IdVXzOKcdi3juWfll5ugT6Tp8=; b=HYqm1kQIFYFjJDQgAJt9wjqHr/Y/X21kXW7swzLHk/yT4N57VjWHoyBsEzw0XckAYq qCqyJ3ooMy+n3Xw+Ldk31A1qJZmqEOBs7J7IKp2mOCuSjGchK+xPq//cpeKvmAhkmrH5 m0dVaugF7kY3M/AI+WOLm5+8OL8xEeDqaWV8s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uHwQH74Q7N25Q2zdI6IdVXzOKcdi3juWfll5ugT6Tp8=; b=27gUbzTn8vzPzdAbPIuvLn6Nl5SAk824VecKHLAGS37RlUVePZX5iJ2x/nTBA01EuV AGo0pWkpCSmdy9pWA54hkKC7BYz+AuzH5DHRsG09VjEUOVeKeS9Qt1MFwe4D7zeSaSwV ay+AlTbegWy16+a3m9C/9CuC23FVzK9ClmRXh+B8EXW2kDUeWmYRTaTn27gsQnaDWR1c 62qRRfOh2mqRq1vEDH4VrDc1Be49JQcpsx70zUoRerFEP3myoivArsBOhMzysQLoB751 PjNxEMSeSyRQv6ClPvTq5mTLIHBaKzpVymrHdRMbFGyCvu9xlNlZN9+/2mB5G2ajYIOE AOdg== X-Gm-Message-State: AOAM530LKdnWNVPU05d8hC+nrPzOOWF8eAQvfB0OtQpF0n7aF/R7NMKL GfXxGVrK9aUHB5w+fdEJIjkvbQ== X-Google-Smtp-Source: ABdhPJxHAmaTQ7SoG4xOWZo1AxxrADEQ2354vOZDz2LunO92X2LOOVaWdpZupcrtKG2bjWHbFEFu3Q== X-Received: by 2002:a17:907:2d2a:b0:710:76a1:4d89 with SMTP id gs42-20020a1709072d2a00b0071076a14d89mr11993861ejc.307.1654523178289; Mon, 06 Jun 2022 06:46:18 -0700 (PDT) Received: from localhost.localdomain (80.71.142.18.ipv4.parknet.dk. [80.71.142.18]) by smtp.gmail.com with ESMTPSA id a26-20020a1709062b1a00b006f3ef214db4sm5496538ejg.26.2022.06.06.06.46.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 06:46:17 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: luizluca@gmail.com, Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/5] net: dsa: realtek: rtl8365mb: remove learn_limit_max private data member Date: Mon, 6 Jun 2022 15:45:52 +0200 Message-Id: <20220606134553.2919693-5-alvin@pqrs.dk> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220606134553.2919693-1-alvin@pqrs.dk> References: <20220606134553.2919693-1-alvin@pqrs.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Alvin Šipraga The variable is just assigned the value of a macro, so it can be removed. Signed-off-by: Alvin Šipraga --- drivers/net/dsa/realtek/rtl8365mb.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c index 392047558656..a3a4454f77bf 100644 --- a/drivers/net/dsa/realtek/rtl8365mb.c +++ b/drivers/net/dsa/realtek/rtl8365mb.c @@ -563,7 +563,6 @@ struct rtl8365mb_port { * @irq: registered IRQ or zero * @chip_id: chip identifier * @chip_ver: chip silicon revision - * @learn_limit_max: maximum number of L2 addresses the chip can learn * @cpu: CPU tagging and CPU port configuration for this chip * @mib_lock: prevent concurrent reads of MIB counters * @ports: per-port data @@ -577,7 +576,6 @@ struct rtl8365mb { int irq; u32 chip_id; u32 chip_ver; - u32 learn_limit_max; struct rtl8365mb_cpu cpu; struct mutex mib_lock; struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS]; @@ -1108,15 +1106,13 @@ static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port, static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port, bool enable) { - struct rtl8365mb *mb = priv->chip_data; - /* Enable/disable learning by limiting the number of L2 addresses the * port can learn. Realtek documentation states that a limit of zero * disables learning. When enabling learning, set it to the chip's * maximum. */ return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port), - enable ? mb->learn_limit_max : 0); + enable ? RTL8365MB_LEARN_LIMIT_MAX : 0); } static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port, @@ -2026,7 +2022,6 @@ static int rtl8365mb_detect(struct realtek_priv *priv) mb->priv = priv; mb->chip_id = chip_id; mb->chip_ver = chip_ver; - mb->learn_limit_max = RTL8365MB_LEARN_LIMIT_MAX; mb->jam_table = rtl8365mb_init_jam_8365mb_vc; mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc); From patchwork Mon Jun 6 13:45:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 12870381 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D48A2C433EF for ; Mon, 6 Jun 2022 13:46:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239192AbiFFNqt (ORCPT ); Mon, 6 Jun 2022 09:46:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239048AbiFFNqY (ORCPT ); Mon, 6 Jun 2022 09:46:24 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C6242B1964 for ; Mon, 6 Jun 2022 06:46:21 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id x5so13810265edi.2 for ; Mon, 06 Jun 2022 06:46:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+prGQaCEIgFN71c5M9SNYfoEIfjYo8Cc5lTo+wFh6BE=; b=Vfp0ZeSY2GtdN0TOvYIz47jTO8DJxOLRf7OllZ8h5ahSlKDxh46Nla6zo3kD5kQnkh Xe3okGbcXTrr06LZKofSZIlzMUhTP9FHJnKz6aVEsUTAgPWjChcl863C4YGAORDCIl82 lW9sd+tCYou9d5VGtzutNHNpRScThOdAjewPE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+prGQaCEIgFN71c5M9SNYfoEIfjYo8Cc5lTo+wFh6BE=; b=DsVMbhCIxY2lS4vPGSGdLUvJYDIUvR2kMtjE8oaTDFcSU73bXiJm37rma8aXPltP5X Gfeevaxpl7vxjo/w7/TkUyaJs0pceWeoUyU7dTclOLt1z1jEXM5lv/5E9rljGaMujQeP bhahJhPtHdPgyw5KmKKN6uJ+tTjk7TR4M8wVBsPkDlFXxkrgukIhjgEKmHk2y+85vzEr V/Rh8hM6R3C3ed5u9NJ+T+wl6PodRb1w6kWA499M7gfsavtUjAWDBlhbh3ZxgAYcIZVU +xdp/ncrQ2mvd6QugljNEuyXq3n3ZPS/b67mECDhnehgpyvECe2aoCnTVck79FxlzR5D OHyg== X-Gm-Message-State: AOAM530UaLpOzkpX17Z5AWMAyUIApsXdw/PYGXKqRfCAWp1dJaXSY0Vt lcByClFD30hTX+PxDprVzdcUyw== X-Google-Smtp-Source: ABdhPJzzbzaRw04WEzuuxy4f1/A3haCV+AzRlq9xgxB4rRr3TTwto7u6DvgWEnes+6k3QJOOb85Xgg== X-Received: by 2002:aa7:cc8f:0:b0:42d:f88c:9f63 with SMTP id p15-20020aa7cc8f000000b0042df88c9f63mr27535199edt.288.1654523180079; Mon, 06 Jun 2022 06:46:20 -0700 (PDT) Received: from localhost.localdomain (80.71.142.18.ipv4.parknet.dk. [80.71.142.18]) by smtp.gmail.com with ESMTPSA id a26-20020a1709062b1a00b006f3ef214db4sm5496538ejg.26.2022.06.06.06.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jun 2022 06:46:19 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: luizluca@gmail.com, Linus Walleij , =?utf-8?q?Alvin_=C5=A0ipraga?= , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 5/5] net: dsa: realtek: rtl8365mb: handle PHY interface modes correctly Date: Mon, 6 Jun 2022 15:45:53 +0200 Message-Id: <20220606134553.2919693-6-alvin@pqrs.dk> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220606134553.2919693-1-alvin@pqrs.dk> References: <20220606134553.2919693-1-alvin@pqrs.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Alvin Šipraga Realtek switches in the rtl8365mb family always have at least one port with a so-called external interface, supporting PHY interface modes such as RGMII or SGMII. The purpose of this patch is to improve the driver's handling of these ports. A new struct rtl8365mb_chip_info is introduced. A static instance of this struct is added for each supported switch, which is distinguished by its chip ID and version. Embedded in each chip_info struct is an array of struct rtl8365mb_extint, describing the external interfaces available. This is more specific than the old rtl8365mb_extint_port_map, which was only valid for switches with up to 6 ports. The struct rtl8365mb_extint also contains a bitmask of supported PHY interface modes, which allows the driver to distinguish which ports support RGMII. This corrects a previous mistake in the driver whereby it was assumed that any port with an external interface supports RGMII. This is not actually the case: for example, the RTL8367S has two external interfaces, only the second of which supports RGMII. The first supports only SGMII and HSGMII. This new design will make it easier to add support for other interface modes. Finally, rtl8365mb_phylink_get_caps() is fixed up to return supported capabilities based on the external interface properties described above. This allows for ports with an external interface to be treated as DSA user ports, and for ports with an internal PHY to be treated as DSA CPU ports. Link: https://lore.kernel.org/netdev/20220510192301.5djdt3ghoavxulhl@bang-olufsen.dk/ Signed-off-by: Alvin Šipraga --- drivers/net/dsa/realtek/rtl8365mb.c | 247 +++++++++++++++++++++------- 1 file changed, 183 insertions(+), 64 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c index a3a4454f77bf..2dc0459af5a4 100644 --- a/drivers/net/dsa/realtek/rtl8365mb.c +++ b/drivers/net/dsa/realtek/rtl8365mb.c @@ -118,9 +118,6 @@ #define RTL8365MB_MAX_NUM_PORTS 11 #define RTL8365MB_LEARN_LIMIT_MAX 2112 -/* valid for all 6-port or less variants */ -static const int rtl8365mb_extint_port_map[] = { -1, -1, -1, -1, -1, -1, 1, 2, -1, -1}; - /* Chip identification registers */ #define RTL8365MB_CHIP_ID_REG 0x1300 @@ -200,7 +197,7 @@ static const int rtl8365mb_extint_port_map[] = { -1, -1, -1, -1, -1, -1, 1, 2, /* The PHY OCP addresses of PHY registers 0~31 start here */ #define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400 -/* EXT interface port mode values - used in DIGITAL_INTERFACE_SELECT */ +/* External interface port mode values - used in DIGITAL_INTERFACE_SELECT */ #define RTL8365MB_EXT_PORT_MODE_DISABLE 0 #define RTL8365MB_EXT_PORT_MODE_RGMII 1 #define RTL8365MB_EXT_PORT_MODE_MII_MAC 2 @@ -216,19 +213,7 @@ static const int rtl8365mb_extint_port_map[] = { -1, -1, -1, -1, -1, -1, 1, 2, #define RTL8365MB_EXT_PORT_MODE_1000X 12 #define RTL8365MB_EXT_PORT_MODE_100FX 13 -/* Realtek docs and driver uses logic number as EXT_PORT0=16, EXT_PORT1=17, - * EXT_PORT2=18, to interact with switch ports. That logic number is internally - * converted to either a physical port number (0..9) or an external interface id (0..2), - * depending on which function was called. The external interface id is calculated as - * (ext_id=logic_port-15), while the logical to physical map depends on the chip id/version. - * - * EXT_PORT0 mentioned in datasheets and rtl8367c driver is used in this driver - * as extid==1, EXT_PORT2, mentioned in Realtek rtl8367c driver for 10-port switches, - * would have an ext_id of 3 (out of range for most extint macros) and ext_id 0 does - * not seem to be used as well for this family. - */ - -/* EXT interface mode configuration registers 0~1 */ +/* External interface mode configuration registers 0~1 */ #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305 /* EXT1 */ #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 /* EXT2 */ #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \ @@ -240,7 +225,7 @@ static const int rtl8365mb_extint_port_map[] = { -1, -1, -1, -1, -1, -1, 1, 2, #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \ (((_extint) % 2) * 4) -/* EXT interface RGMII TX/RX delay configuration registers 0~2 */ +/* External interface RGMII TX/RX delay configuration registers 0~2 */ #define RTL8365MB_EXT_RGMXF_REG0 0x1306 /* EXT0 */ #define RTL8365MB_EXT_RGMXF_REG1 0x1307 /* EXT1 */ #define RTL8365MB_EXT_RGMXF_REG2 0x13C5 /* EXT2 */ @@ -257,7 +242,7 @@ static const int rtl8365mb_extint_port_map[] = { -1, -1, -1, -1, -1, -1, 1, 2, #define RTL8365MB_PORT_SPEED_100M 1 #define RTL8365MB_PORT_SPEED_1000M 2 -/* EXT interface force configuration registers 0~2 */ +/* External interface force configuration registers 0~2 */ #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */ #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311 /* EXT1 */ #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 /* EXT2 */ @@ -489,6 +474,100 @@ static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = { { 0x1D32, 0x0002 }, }; +enum rtl8365mb_phy_interface_mode { + RTL8365MB_PHY_INTERFACE_MODE_INVAL = 0, /* used as sentinel */ + RTL8365MB_PHY_INTERFACE_MODE_INTERNAL = BIT(0), + RTL8365MB_PHY_INTERFACE_MODE_MII = BIT(1), + RTL8365MB_PHY_INTERFACE_MODE_TMII = BIT(2), + RTL8365MB_PHY_INTERFACE_MODE_RMII = BIT(3), + RTL8365MB_PHY_INTERFACE_MODE_RGMII = BIT(4), + RTL8365MB_PHY_INTERFACE_MODE_SGMII = BIT(5), + RTL8365MB_PHY_INTERFACE_MODE_HSGMII = BIT(6), +}; + +/** + * struct rtl8365mb_extint - external interface info + * @port: the port with an external interface + * @id: the external interface ID, which is either 0, 1, or 2 + * @supported_interfaces: a bitmask of supported PHY interface modes + * + * Represents a mapping: port -> { id, supported_interfaces }. To be embedded + * in &struct rtl8365mb_chip_info for every port with an external interface. + */ +struct rtl8365mb_extint { + int port; + int id; + unsigned int supported_interfaces; +}; + +/** + * struct rtl8365mb_chip_info - static chip-specific info + * @name: human-readable chip name + * @chip_id: chip identifier + * @chip_ver: chip silicon revision + * @jam_table: chip-specific initialization jam table + * @jam_size: size of the chip's jam table + * @extints: external interfaces, followed by a zero sentinel + * + * These data are specific to a given chip in the family of switches supported + * by this driver. When adding support for another chip in the family, a new + * static struct of this type should be defined, and assigned in the + * rtl8365mb_detect() function based on chip ID/version. + */ +struct rtl8365mb_chip_info { + const char *name; + u32 chip_id; + u32 chip_ver; + const struct rtl8365mb_jam_tbl_entry *jam_table; + size_t jam_size; + const struct rtl8365mb_extint extints[]; +}; + +/* Chip info for each supported switch in the family */ +#define PHY_INTF(_mode) (RTL8365MB_PHY_INTERFACE_MODE_ ## _mode) + +static const struct rtl8365mb_chip_info rtl8365mb_chip_info_8365mb_vc = { + .name = "RTL8365MB-VC", + .chip_id = RTL8365MB_CHIP_ID_8365MB_VC, + .chip_ver = RTL8365MB_CHIP_VER_8365MB_VC, + .extints = { + { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) | PHY_INTF(RMII) | + PHY_INTF(RGMII) }, + { /* sentinel */ } + }, + .jam_table = rtl8365mb_init_jam_8365mb_vc, + .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), +}; + +static const struct rtl8365mb_chip_info rtl8365mb_chip_info_8367s = { + .name = "RTL8367S", + .chip_id = RTL8365MB_CHIP_ID_8367S, + .chip_ver = RTL8365MB_CHIP_VER_8367S, + .extints = { + { 6, 1, PHY_INTF(SGMII) | PHY_INTF(HSGMII) }, + { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) | PHY_INTF(RMII) | + PHY_INTF(RGMII) }, + { /* sentinel */ } + }, + .jam_table = rtl8365mb_init_jam_8365mb_vc, + .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), +}; + +static const struct rtl8365mb_chip_info rtl8365mb_chip_info_8367rb_vb = { + .name = "RTL8367RB-VB", + .chip_id = RTL8365MB_CHIP_ID_8367RB_VB, + .chip_ver = RTL8365MB_CHIP_VER_8367RB_VB, + .extints = { + { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) | PHY_INTF(RMII) | + PHY_INTF(RGMII) }, + { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) | PHY_INTF(RMII) | + PHY_INTF(RGMII) }, + { /* sentinel */ } + }, + .jam_table = rtl8365mb_init_jam_8365mb_vc, + .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), +}; + enum rtl8365mb_stp_state { RTL8365MB_STP_STATE_DISABLED = 0, RTL8365MB_STP_STATE_BLOCKING = 1, @@ -558,7 +637,7 @@ struct rtl8365mb_port { }; /** - * struct rtl8365mb - private chip-specific driver data + * struct rtl8365mb - driver private data * @priv: pointer to parent realtek_priv data * @irq: registered IRQ or zero * @chip_id: chip identifier @@ -574,13 +653,10 @@ struct rtl8365mb_port { struct rtl8365mb { struct realtek_priv *priv; int irq; - u32 chip_id; - u32 chip_ver; + const struct rtl8365mb_chip_info *chip_info; struct rtl8365mb_cpu cpu; struct mutex mib_lock; struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS]; - const struct rtl8365mb_jam_tbl_entry *jam_table; - size_t jam_size; }; static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv) @@ -775,6 +851,31 @@ static int rtl8365mb_dsa_phy_write(struct dsa_switch *ds, int phy, int regnum, return rtl8365mb_phy_write(ds->priv, phy, regnum, val); } +const struct rtl8365mb_extint * +rtl8365mb_get_port_extint(struct realtek_priv *priv, int port) +{ + struct rtl8365mb *mb = priv->chip_data; + const struct rtl8365mb_extint *extint; + const struct rtl8365mb_chip_info *ci; + + ci = mb->chip_info; + extint = &ci->extints[0]; + + /* Every external interface supports at least one mode, so at least one + * bit should be set in supported_interfaces. We use 0 as a sentinel, + * cf. @RTL8265MB_PHY_INTERFACE_MODE_INVAL = 0. + */ + while (extint->supported_interfaces != + RTL8365MB_PHY_INTERFACE_MODE_INVAL) { + if (extint->port == port) + return extint; + + extint++; + } + + return NULL; +} + static enum dsa_tag_protocol rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port, enum dsa_tag_protocol mp) @@ -795,18 +896,23 @@ rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port, static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, phy_interface_t interface) { + const struct rtl8365mb_extint *extint = + rtl8365mb_get_port_extint(priv, port); struct device_node *dn; struct dsa_port *dp; int tx_delay = 0; int rx_delay = 0; - int ext_int; u32 val; int ret; - ext_int = rtl8365mb_extint_port_map[port]; + if (!extint) { + dev_err(priv->dev, "port %d has no external interface\n", port); + return -EINVAL; + } - if (ext_int <= 0) { - dev_err(priv->dev, "Port %d is not an external interface port\n", port); + if (!(extint->supported_interfaces & + RTL8365MB_PHY_INTERFACE_MODE_RGMII)) { + dev_err(priv->dev, "port %d doesn't support RGMII\n", port); return -EINVAL; } @@ -842,7 +948,7 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, tx_delay = val / 2; else dev_warn(priv->dev, - "EXT interface TX delay must be 0 or 2 ns\n"); + "RGMII TX delay must be 0 or 2 ns\n"); } if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) { @@ -852,11 +958,11 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, rx_delay = val; else dev_warn(priv->dev, - "EXT interface RX delay must be 0 to 2.1 ns\n"); + "RGMII RX delay must be 0 to 2.1 ns\n"); } ret = regmap_update_bits( - priv->map, RTL8365MB_EXT_RGMXF_REG(ext_int), + priv->map, RTL8365MB_EXT_RGMXF_REG(extint->id), RTL8365MB_EXT_RGMXF_TXDELAY_MASK | RTL8365MB_EXT_RGMXF_RXDELAY_MASK, FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) | @@ -865,11 +971,11 @@ static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, return ret; ret = regmap_update_bits( - priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(ext_int), - RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_int), + priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(extint->id), + RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(extint->id), RTL8365MB_EXT_PORT_MODE_RGMII << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( - ext_int)); + extint->id)); if (ret) return ret; @@ -880,19 +986,18 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, bool link, int speed, int duplex, bool tx_pause, bool rx_pause) { + const struct rtl8365mb_extint *extint = + rtl8365mb_get_port_extint(priv, port); u32 r_tx_pause; u32 r_rx_pause; u32 r_duplex; u32 r_speed; u32 r_link; - int ext_int; int val; int ret; - ext_int = rtl8365mb_extint_port_map[port]; - - if (ext_int <= 0) { - dev_err(priv->dev, "Port %d is not an external interface port\n", port); + if (!extint) { + dev_err(priv->dev, "port %d has no external interface\n", port); return -EINVAL; } @@ -942,7 +1047,7 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, r_duplex) | FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); ret = regmap_write(priv->map, - RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(ext_int), + RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id), val); if (ret) return ret; @@ -974,14 +1079,31 @@ static bool rtl8365mb_phy_mode_supported(struct dsa_switch *ds, int port, static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { - if (dsa_is_user_port(ds, port)) - __set_bit(PHY_INTERFACE_MODE_INTERNAL, - config->supported_interfaces); - else if (dsa_is_cpu_port(ds, port)) - phy_interface_set_rgmii(config->supported_interfaces); + const struct rtl8365mb_extint *extint = + rtl8365mb_get_port_extint(ds->priv, port); config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; + + if (!extint) { + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + + /* GMII is the default interface mode for phylib, so + * we have to support it for ports with integrated PHY. + */ + __set_bit(PHY_INTERFACE_MODE_GMII, + config->supported_interfaces); + return; + } + + /* Populate according to the modes supported by _this driver_, + * not necessarily the modes supported by the hardware, some of + * which remain unimplemented. + */ + + if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII) + phy_interface_set_rgmii(config->supported_interfaces); } static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port, @@ -1805,14 +1927,17 @@ static int rtl8365mb_change_tag_protocol(struct dsa_switch *ds, static int rtl8365mb_switch_init(struct realtek_priv *priv) { struct rtl8365mb *mb = priv->chip_data; + const struct rtl8365mb_chip_info *ci; int ret; int i; + ci = mb->chip_info; + /* Do any chip-specific init jam before getting to the common stuff */ - if (mb->jam_table) { - for (i = 0; i < mb->jam_size; i++) { - ret = regmap_write(priv->map, mb->jam_table[i].reg, - mb->jam_table[i].val); + if (ci->jam_table) { + for (i = 0; i < ci->jam_size; i++) { + ret = regmap_write(priv->map, ci->jam_table[i].reg, + ci->jam_table[i].val); if (ret) return ret; } @@ -1997,33 +2122,27 @@ static int rtl8365mb_detect(struct realtek_priv *priv) case RTL8365MB_CHIP_ID_8365MB_VC: switch (chip_ver) { case RTL8365MB_CHIP_VER_8365MB_VC: - dev_info(priv->dev, - "found an RTL8365MB-VC switch (ver=0x%04x)\n", - chip_ver); + mb->chip_info = &rtl8365mb_chip_info_8365mb_vc; break; case RTL8365MB_CHIP_VER_8367RB_VB: - dev_info(priv->dev, - "found an RTL8367RB-VB switch (ver=0x%04x)\n", - chip_ver); + mb->chip_info = &rtl8365mb_chip_info_8367rb_vb; break; case RTL8365MB_CHIP_VER_8367S: - dev_info(priv->dev, - "found an RTL8367S switch (ver=0x%04x)\n", - chip_ver); + mb->chip_info = &rtl8365mb_chip_info_8367s; break; default: - dev_err(priv->dev, "unrecognized switch version (ver=0x%04x)", - chip_ver); + dev_err(priv->dev, + "unrecognized switch (id=0x%04x, ver=0x%04x)", + chip_id, chip_ver); return -ENODEV; } + dev_info(priv->dev, "found an %s switch\n", + mb->chip_info->name); + priv->num_ports = RTL8365MB_MAX_NUM_PORTS; mb->priv = priv; - mb->chip_id = chip_id; - mb->chip_ver = chip_ver; - mb->jam_table = rtl8365mb_init_jam_8365mb_vc; - mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc); mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS; mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;