From patchwork Tue Jun 7 03:28:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12871322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76B95C43334 for ; Tue, 7 Jun 2022 03:33:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236272AbiFGDcI (ORCPT ); Mon, 6 Jun 2022 23:32:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230101AbiFGDcG (ORCPT ); Mon, 6 Jun 2022 23:32:06 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5151445782; Mon, 6 Jun 2022 20:32:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654572725; x=1686108725; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nphOBXs/+SI9u+eGqjgatvTTn0XBshiwzlb3vatLVc0=; b=F+z/Vt0JlYEkLLZPyOzvANMh2JdToFOz1Mv/Hi2q2L86FP6cFTth+H7w 7H4zjlXgoR0UuMbLlL0AWtWCyaxfWv4VdS5rf6psp7okmEjJ5F7A9bcyA W4DYDWIXHktgelLROG7Vjfs6WYchdYLUkJEpZGxWl1/FlXddfSuNqlpvE tNJUrECkL3O2eUH4NNlne+vMa0/kSjbdjBVSVuZEb8cpdetRda7pQlQlr PVZPpRiNAwrYfqSptmDrUbL/HUYem0XIBkpQxoqj+OycegHoTBqDpCwgL D1R21y9R4z7E+xpNUtMtM1oRn9yGG1eVV+MdYOrIcu/cN+WXXd54ptPtL Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="337908379" X-IronPort-AV: E=Sophos;i="5.91,282,1647327600"; d="scan'208";a="337908379" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 20:32:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,282,1647327600"; d="scan'208";a="826161222" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by fmsmga006.fm.intel.com with ESMTP; 06 Jun 2022 20:32:02 -0700 From: Tianfei Zhang To: yilun.xu@intel.com, lee.jones@linaro.org Cc: hao.wu@intel.com, trix@redhat.com, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org, russell.h.weight@intel.com, matthew.gerlach@linux.intel.com, Tianfei Zhang Subject: [PATCH v1 1/4] mfd: intel-m10-bmc: rename the local variables Date: Mon, 6 Jun 2022 23:28:30 -0400 Message-Id: <20220607032833.3482-2-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220607032833.3482-1-tianfei.zhang@intel.com> References: <20220607032833.3482-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org It had better use ddata for local variables which directly interacts with dev_get_drvdata()/dev_set_drvdata(). Signed-off-by: Tianfei Zhang --- drivers/mfd/intel-m10-bmc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c index 8db3bcf5fccc..7e521df29c72 100644 --- a/drivers/mfd/intel-m10-bmc.c +++ b/drivers/mfd/intel-m10-bmc.c @@ -86,15 +86,15 @@ static DEVICE_ATTR_RO(bmcfw_version); static ssize_t mac_address_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct intel_m10bmc *max10 = dev_get_drvdata(dev); + struct intel_m10bmc *ddata = dev_get_drvdata(dev); unsigned int macaddr_low, macaddr_high; int ret; - ret = m10bmc_sys_read(max10, M10BMC_MAC_LOW, &macaddr_low); + ret = m10bmc_sys_read(ddata, M10BMC_MAC_LOW, &macaddr_low); if (ret) return ret; - ret = m10bmc_sys_read(max10, M10BMC_MAC_HIGH, &macaddr_high); + ret = m10bmc_sys_read(ddata, M10BMC_MAC_HIGH, &macaddr_high); if (ret) return ret; @@ -111,11 +111,11 @@ static DEVICE_ATTR_RO(mac_address); static ssize_t mac_count_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct intel_m10bmc *max10 = dev_get_drvdata(dev); + struct intel_m10bmc *ddata = dev_get_drvdata(dev); unsigned int macaddr_high; int ret; - ret = m10bmc_sys_read(max10, M10BMC_MAC_HIGH, &macaddr_high); + ret = m10bmc_sys_read(ddata, M10BMC_MAC_HIGH, &macaddr_high); if (ret) return ret; From patchwork Tue Jun 7 03:28:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12871323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 832CCC433EF for ; Tue, 7 Jun 2022 03:33:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236291AbiFGDcM (ORCPT ); Mon, 6 Jun 2022 23:32:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236296AbiFGDcJ (ORCPT ); Mon, 6 Jun 2022 23:32:09 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDCE845782; Mon, 6 Jun 2022 20:32:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654572727; x=1686108727; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=blj+rejLf/gw1PeBjTDEjNTgzu52qf7qMB3ZiGYEiWQ=; b=NytzOpWqv9gYuf1SUrZYroFdNRZC5Zguo8hK4wtpbhlF2/nhHuCgAhGw 98/hTBjzMQRLDnhV/VDE0/pE+ktp4HWRoXEhQDvPke1vX8TxzGklFbNJd CJyaKOVAD73iNi/vuGqcmCVRDGeJ+7S+PYOnx0t9qcj51DL92P4JdVXC7 rg5Fz+BuxMqTbVwbnUNvkxlqMcZuJtgjxrCcmzTkKF7sCJiAL2BIzmp5v DNHuiwwI3Zl9tETX/HBinjcJDPPb543Gk3I2zrwzIL/Lt63A8kvKE6i3U E5SEGoJCNekinyei9AS4t2hHlLn3t0LwZ82Y49cvHSsCdTn6p3UM0VP99 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="337908392" X-IronPort-AV: E=Sophos;i="5.91,282,1647327600"; d="scan'208";a="337908392" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 20:32:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,282,1647327600"; d="scan'208";a="826161230" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by fmsmga006.fm.intel.com with ESMTP; 06 Jun 2022 20:32:05 -0700 From: Tianfei Zhang To: yilun.xu@intel.com, lee.jones@linaro.org Cc: hao.wu@intel.com, trix@redhat.com, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org, russell.h.weight@intel.com, matthew.gerlach@linux.intel.com, Tianfei Zhang Subject: [PATCH v1 2/4] mfd: intel-m10-bmc: split into core and spi Date: Mon, 6 Jun 2022 23:28:31 -0400 Message-Id: <20220607032833.3482-3-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220607032833.3482-1-tianfei.zhang@intel.com> References: <20220607032833.3482-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Split the common code from intel-m10-bmc driver into intel-m10-bmc-core. intel-m10-bmc-core is the core MFD functions which can support multiple bus interfaces like SPI bus. Signed-off-by: Tianfei Zhang --- drivers/mfd/Kconfig | 30 +++--- drivers/mfd/Makefile | 5 +- .../{intel-m10-bmc.c => intel-m10-bmc-core.c} | 101 +++++------------- drivers/mfd/intel-m10-bmc-spi.c | 83 ++++++++++++++ include/linux/mfd/intel-m10-bmc.h | 15 +++ 5 files changed, 144 insertions(+), 90 deletions(-) rename drivers/mfd/{intel-m10-bmc.c => intel-m10-bmc-core.c} (63%) create mode 100644 drivers/mfd/intel-m10-bmc-spi.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 3b59456f5545..ee8398b02321 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2158,18 +2158,24 @@ config SGI_MFD_IOC3 If you have an SGI Origin, Octane, or a PCI IOC3 card, then say Y. Otherwise say N. -config MFD_INTEL_M10_BMC - tristate "Intel MAX 10 Board Management Controller" - depends on SPI_MASTER - select REGMAP_SPI_AVMM - select MFD_CORE - help - Support for the Intel MAX 10 board management controller using the - SPI interface. - - This driver provides common support for accessing the device, - additional drivers must be enabled in order to use the functionality - of the device. +config MFD_INTEL_M10_BMC_CORE + tristate + select MFD_CORE + select REGMAP + default n + +config MFD_INTEL_M10_BMC_SPI + tristate "Intel MAX 10 Board Management Controller with SPI" + depends on SPI_MASTER + select MFD_INTEL_M10_BMC_CORE + select REGMAP_SPI_AVMM + help + Support for the Intel MAX 10 board management controller using the + SPI interface. + + This driver provides common support for accessing the device, + additional drivers must be enabled in order to use the functionality + of the device. config MFD_RSMU_I2C tristate "Renesas Synchronization Management Unit with I2C" diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 858cacf659d6..b5d3263c1205 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -266,7 +266,10 @@ obj-$(CONFIG_MFD_QCOM_PM8008) += qcom-pm8008.o obj-$(CONFIG_SGI_MFD_IOC3) += ioc3.o obj-$(CONFIG_MFD_SIMPLE_MFD_I2C) += simple-mfd-i2c.o -obj-$(CONFIG_MFD_INTEL_M10_BMC) += intel-m10-bmc.o + +intel-m10-bmc-objs := intel-m10-bmc-core.o +obj-$(CONFIG_MFD_INTEL_M10_BMC_CORE) += intel-m10-bmc.o +obj-$(CONFIG_MFD_INTEL_M10_BMC_SPI) += intel-m10-bmc-spi.o obj-$(CONFIG_MFD_ATC260X) += atc260x-core.o obj-$(CONFIG_MFD_ATC260X_I2C) += atc260x-i2c.o diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc-core.c similarity index 63% rename from drivers/mfd/intel-m10-bmc.c rename to drivers/mfd/intel-m10-bmc-core.c index 7e521df29c72..f6dc549e1bc3 100644 --- a/drivers/mfd/intel-m10-bmc.c +++ b/drivers/mfd/intel-m10-bmc-core.c @@ -1,23 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Intel MAX 10 Board Management Controller chip + * Intel MAX 10 Board Management Controller chip - common code * - * Copyright (C) 2018-2020 Intel Corporation. All rights reserved. + * Copyright (C) 2018-2022 Intel Corporation. All rights reserved. */ #include #include #include #include #include -#include -#include -#include - -enum m10bmc_type { - M10_N3000, - M10_D5005, - M10_N5010, -}; static struct mfd_cell m10bmc_d5005_subdevs[] = { { .name = "d5005bmc-hwmon" }, @@ -33,26 +24,6 @@ static struct mfd_cell m10bmc_n5010_subdevs[] = { { .name = "n5010bmc-hwmon" }, }; -static const struct regmap_range m10bmc_regmap_range[] = { - regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER), - regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END), - regmap_reg_range(M10BMC_FLASH_BASE, M10BMC_FLASH_END), -}; - -static const struct regmap_access_table m10bmc_access_table = { - .yes_ranges = m10bmc_regmap_range, - .n_yes_ranges = ARRAY_SIZE(m10bmc_regmap_range), -}; - -static struct regmap_config intel_m10bmc_regmap_config = { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .wr_table = &m10bmc_access_table, - .rd_table = &m10bmc_access_table, - .max_register = M10BMC_MEM_END, -}; - static ssize_t bmc_version_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -131,7 +102,16 @@ static struct attribute *m10bmc_attrs[] = { &dev_attr_mac_count.attr, NULL, }; -ATTRIBUTE_GROUPS(m10bmc); + +static const struct attribute_group m10bmc_group = { + .attrs = m10bmc_attrs, +}; + +const struct attribute_group *m10bmc_dev_groups[] = { + &m10bmc_group, + NULL, +}; +EXPORT_SYMBOL_GPL(m10bmc_dev_groups); static int check_m10bmc_version(struct intel_m10bmc *ddata) { @@ -158,37 +138,21 @@ static int check_m10bmc_version(struct intel_m10bmc *ddata) return 0; } -static int intel_m10_bmc_spi_probe(struct spi_device *spi) +int m10bmc_dev_init(struct intel_m10bmc *m10bmc) { - const struct spi_device_id *id = spi_get_device_id(spi); - struct device *dev = &spi->dev; + enum m10bmc_type type = m10bmc->type; struct mfd_cell *cells; - struct intel_m10bmc *ddata; int ret, n_cell; - ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); - if (!ddata) - return -ENOMEM; - - ddata->dev = dev; - - ddata->regmap = - devm_regmap_init_spi_avmm(spi, &intel_m10bmc_regmap_config); - if (IS_ERR(ddata->regmap)) { - ret = PTR_ERR(ddata->regmap); - dev_err(dev, "Failed to allocate regmap: %d\n", ret); - return ret; - } - - spi_set_drvdata(spi, ddata); + dev_set_drvdata(m10bmc->dev, m10bmc); - ret = check_m10bmc_version(ddata); + ret = check_m10bmc_version(m10bmc); if (ret) { - dev_err(dev, "Failed to identify m10bmc hardware\n"); + dev_err(m10bmc->dev, "Failed to identify m10bmc hardware\n"); return ret; } - switch (id->driver_data) { + switch (type) { case M10_N3000: cells = m10bmc_pacn3000_subdevs; n_cell = ARRAY_SIZE(m10bmc_pacn3000_subdevs); @@ -205,33 +169,16 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi) return -ENODEV; } - ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cells, n_cell, - NULL, 0, NULL); + ret = devm_mfd_add_devices(m10bmc->dev, PLATFORM_DEVID_AUTO, + cells, n_cell, NULL, 0, NULL); if (ret) - dev_err(dev, "Failed to register sub-devices: %d\n", ret); + dev_err(m10bmc->dev, "Failed to register sub-devices: %d\n", + ret); return ret; } +EXPORT_SYMBOL_GPL(m10bmc_dev_init); -static const struct spi_device_id m10bmc_spi_id[] = { - { "m10-n3000", M10_N3000 }, - { "m10-d5005", M10_D5005 }, - { "m10-n5010", M10_N5010 }, - { } -}; -MODULE_DEVICE_TABLE(spi, m10bmc_spi_id); - -static struct spi_driver intel_m10bmc_spi_driver = { - .driver = { - .name = "intel-m10-bmc", - .dev_groups = m10bmc_groups, - }, - .probe = intel_m10_bmc_spi_probe, - .id_table = m10bmc_spi_id, -}; -module_spi_driver(intel_m10bmc_spi_driver); - -MODULE_DESCRIPTION("Intel MAX 10 BMC Device Driver"); +MODULE_DESCRIPTION("Intel MAX 10 BMC core MFD driver"); MODULE_AUTHOR("Intel Corporation"); MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("spi:intel-m10-bmc"); diff --git a/drivers/mfd/intel-m10-bmc-spi.c b/drivers/mfd/intel-m10-bmc-spi.c new file mode 100644 index 000000000000..9cafbc0f89f0 --- /dev/null +++ b/drivers/mfd/intel-m10-bmc-spi.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel MAX 10 Board Management Controller chip + * + * Copyright (C) 2018-2021 Intel Corporation. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include + +static const struct regmap_range m10bmc_regmap_range[] = { + regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER), + regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END), + regmap_reg_range(M10BMC_FLASH_BASE, M10BMC_FLASH_END), +}; + +static const struct regmap_access_table m10bmc_access_table = { + .yes_ranges = m10bmc_regmap_range, + .n_yes_ranges = ARRAY_SIZE(m10bmc_regmap_range), +}; + +static struct regmap_config intel_m10bmc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .wr_table = &m10bmc_access_table, + .rd_table = &m10bmc_access_table, + .max_register = M10BMC_MEM_END, +}; + +static int intel_m10_bmc_spi_probe(struct spi_device *spi) +{ + const struct spi_device_id *id = spi_get_device_id(spi); + struct device *dev = &spi->dev; + struct intel_m10bmc *ddata; + int ret; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->dev = dev; + ddata->type = (enum m10bmc_type)(id->driver_data); + + ddata->regmap = + devm_regmap_init_spi_avmm(spi, &intel_m10bmc_regmap_config); + if (IS_ERR(ddata->regmap)) { + ret = PTR_ERR(ddata->regmap); + dev_err(dev, "Failed to allocate regmap: %d\n", ret); + return ret; + } + + spi_set_drvdata(spi, ddata); + + return m10bmc_dev_init(ddata); +} + +static const struct spi_device_id m10bmc_spi_id[] = { + { "m10-n3000", M10_N3000 }, + { "m10-d5005", M10_D5005 }, + { "m10-n5010", M10_N5010 }, + { } +}; +MODULE_DEVICE_TABLE(spi, m10bmc_spi_id); + +static struct spi_driver intel_m10bmc_spi_driver = { + .driver = { + .name = "intel-m10-bmc", + .dev_groups = m10bmc_dev_groups, + }, + .probe = intel_m10_bmc_spi_probe, + .id_table = m10bmc_spi_id, +}; +module_spi_driver(intel_m10bmc_spi_driver); + +MODULE_DESCRIPTION("Intel MAX 10 BMC SPI bus interface"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("spi:intel-m10-bmc"); diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h index f0044b14136e..dd81ffdcf168 100644 --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h @@ -118,14 +118,23 @@ /* Address of 4KB inverted bit vector containing staging area FLASH count */ #define STAGING_FLASH_COUNT 0x17ffb000 +/* Supported MAX10 BMC types */ +enum m10bmc_type { + M10_N3000, + M10_D5005, + M10_N5010, +}; + /** * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure * @dev: this device * @regmap: the regmap used to access registers by m10bmc itself + * @type: the type of MAX10 BMC */ struct intel_m10bmc { struct device *dev; struct regmap *regmap; + enum m10bmc_type type; }; /* @@ -159,4 +168,10 @@ m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr, #define m10bmc_sys_read(m10bmc, offset, val) \ m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val) +/* + * MAX10 BMC Core support + */ +int m10bmc_dev_init(struct intel_m10bmc *m10bmc); +extern const struct attribute_group *m10bmc_dev_groups[]; + #endif /* __MFD_INTEL_M10_BMC_H */ From patchwork Tue Jun 7 03:28:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12871325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD7FEC433EF for ; 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X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="337908397" X-IronPort-AV: E=Sophos;i="5.91,282,1647327600"; d="scan'208";a="337908397" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 20:32:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,282,1647327600"; d="scan'208";a="826161236" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by fmsmga006.fm.intel.com with ESMTP; 06 Jun 2022 20:32:07 -0700 From: Tianfei Zhang To: yilun.xu@intel.com, lee.jones@linaro.org Cc: hao.wu@intel.com, trix@redhat.com, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org, russell.h.weight@intel.com, matthew.gerlach@linux.intel.com, Tianfei Zhang Subject: [PATCH v1 3/4] mfd: intel-m10-bmc: add PMCI driver Date: Mon, 6 Jun 2022 23:28:32 -0400 Message-Id: <20220607032833.3482-4-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220607032833.3482-1-tianfei.zhang@intel.com> References: <20220607032833.3482-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Adding a driver for the PMCI-base interface of Intel MAX10 BMC controller. PMCI(Platform Management Control Interface) is a software-visible interface, conneted to card BMC which provided telemetry and mailbox functionalities. Signed-off-by: Tianfei Zhang Signed-off-by: Russ Weight Reported-by: kernel test robot Reported-by: kernel test robot Reported-by: kernel test robot --- .../ABI/testing/sysfs-driver-intel-m10-bmc | 8 +- drivers/mfd/Kconfig | 12 +++ drivers/mfd/Makefile | 1 + drivers/mfd/intel-m10-bmc-core.c | 23 ++++- drivers/mfd/intel-m10-bmc-pmci.c | 88 +++++++++++++++++++ include/linux/mfd/intel-m10-bmc.h | 8 ++ 6 files changed, 132 insertions(+), 8 deletions(-) create mode 100644 drivers/mfd/intel-m10-bmc-pmci.c diff --git a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc index 9773925138af..a8ab58035c95 100644 --- a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc +++ b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc @@ -1,4 +1,4 @@ -What: /sys/bus/spi/devices/.../bmc_version +What: /sys/bus/.../drivers/intel-m10-bmc/.../bmc_version Date: June 2020 KernelVersion: 5.10 Contact: Xu Yilun @@ -6,7 +6,7 @@ Description: Read only. Returns the hardware build version of Intel MAX10 BMC chip. Format: "0x%x". -What: /sys/bus/spi/devices/.../bmcfw_version +What: /sys/bus/.../drivers/intel-m10-bmc/.../bmcfw_version Date: June 2020 KernelVersion: 5.10 Contact: Xu Yilun @@ -14,7 +14,7 @@ Description: Read only. Returns the firmware version of Intel MAX10 BMC chip. Format: "0x%x". -What: /sys/bus/spi/devices/.../mac_address +What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_address Date: January 2021 KernelVersion: 5.12 Contact: Russ Weight @@ -25,7 +25,7 @@ Description: Read only. Returns the first MAC address in a block space. Format: "%02x:%02x:%02x:%02x:%02x:%02x". -What: /sys/bus/spi/devices/.../mac_count +What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_count Date: January 2021 KernelVersion: 5.12 Contact: Russ Weight diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index ee8398b02321..7300efec3617 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2177,6 +2177,18 @@ config MFD_INTEL_M10_BMC_SPI additional drivers must be enabled in order to use the functionality of the device. +config MFD_INTEL_M10_BMC_PMCI + tristate "Intel MAX 10 Board Management Controller with PMCI" + depends on FPGA_DFL + select MFD_INTEL_M10_BMC_CORE + select REGMAP_INDIRECT_REGISTER + help + Support for the Intel MAX 10 board management controller via PMCI. + + This driver provides common support for accessing the device, + additional drivers must be enabled in order to use the functionality + of the device. + config MFD_RSMU_I2C tristate "Renesas Synchronization Management Unit with I2C" depends on I2C && OF diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index b5d3263c1205..a8ffdc223cf7 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -270,6 +270,7 @@ obj-$(CONFIG_MFD_SIMPLE_MFD_I2C) += simple-mfd-i2c.o intel-m10-bmc-objs := intel-m10-bmc-core.o obj-$(CONFIG_MFD_INTEL_M10_BMC_CORE) += intel-m10-bmc.o obj-$(CONFIG_MFD_INTEL_M10_BMC_SPI) += intel-m10-bmc-spi.o +obj-$(CONFIG_MFD_INTEL_M10_BMC_PMCI) += intel-m10-bmc-pmci.o obj-$(CONFIG_MFD_ATC260X) += atc260x-core.o obj-$(CONFIG_MFD_ATC260X_I2C) += atc260x-i2c.o diff --git a/drivers/mfd/intel-m10-bmc-core.c b/drivers/mfd/intel-m10-bmc-core.c index f6dc549e1bc3..20796f0c4a20 100644 --- a/drivers/mfd/intel-m10-bmc-core.c +++ b/drivers/mfd/intel-m10-bmc-core.c @@ -10,6 +10,15 @@ #include #include +static struct mfd_cell m10bmc_n6000_bmc_subdevs[] = { + { .name = "n6000bmc-hwmon" }, + { .name = "n6000bmc-sec-update" } +}; + +static const struct regmap_range n6000_fw_handshake_regs[] = { + regmap_reg_range(M10BMC_PMCI_TELEM_START, M10BMC_PMCI_TELEM_END), +}; + static struct mfd_cell m10bmc_d5005_subdevs[] = { { .name = "d5005bmc-hwmon" }, }; @@ -146,10 +155,12 @@ int m10bmc_dev_init(struct intel_m10bmc *m10bmc) dev_set_drvdata(m10bmc->dev, m10bmc); - ret = check_m10bmc_version(m10bmc); - if (ret) { - dev_err(m10bmc->dev, "Failed to identify m10bmc hardware\n"); - return ret; + if (type == M10_N3000 || type == M10_D5005 || type == M10_N5010) { + ret = check_m10bmc_version(m10bmc); + if (ret) { + dev_err(m10bmc->dev, "Failed to identify m10bmc hardware\n"); + return ret; + } } switch (type) { @@ -165,6 +176,10 @@ int m10bmc_dev_init(struct intel_m10bmc *m10bmc) cells = m10bmc_n5010_subdevs; n_cell = ARRAY_SIZE(m10bmc_n5010_subdevs); break; + case M10_N6000: + cells = m10bmc_n6000_bmc_subdevs; + n_cell = ARRAY_SIZE(m10bmc_n6000_bmc_subdevs); + break; default: return -ENODEV; } diff --git a/drivers/mfd/intel-m10-bmc-pmci.c b/drivers/mfd/intel-m10-bmc-pmci.c new file mode 100644 index 000000000000..319397774d6e --- /dev/null +++ b/drivers/mfd/intel-m10-bmc-pmci.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PMCI-based interface to MAX10 BMC + * + * Copyright (C) 2020-2022 Intel Corporation, Inc. + * + */ + +#include +#include +#include +#include + +#define M10BMC_PMCI_INDIRECT_BASE 0x400 + +struct pmci_device { + void __iomem *base; + struct device *dev; + struct intel_m10bmc m10bmc; +}; + +static const struct regmap_range m10bmc_pmci_regmap_range[] = { + regmap_reg_range(M10BMC_PMCI_SYS_BASE, M10BMC_PMCI_SYS_END), +}; + +static const struct regmap_access_table m10_access_table = { + .yes_ranges = m10bmc_pmci_regmap_range, + .n_yes_ranges = ARRAY_SIZE(m10bmc_pmci_regmap_range), +}; + +static struct regmap_config m10bmc_pmci_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .wr_table = &m10_access_table, + .rd_table = &m10_access_table, + .max_register = M10BMC_PMCI_SYS_END, +}; + +static int pmci_probe(struct dfl_device *ddev) +{ + struct device *dev = &ddev->dev; + struct pmci_device *pmci; + + pmci = devm_kzalloc(dev, sizeof(*pmci), GFP_KERNEL); + if (!pmci) + return -ENOMEM; + + pmci->m10bmc.dev = dev; + pmci->dev = dev; + pmci->m10bmc.type = M10_N6000; + + pmci->base = devm_ioremap_resource(dev, &ddev->mmio_res); + if (IS_ERR(pmci->base)) + return PTR_ERR(pmci->base); + + pmci->m10bmc.regmap = + devm_regmap_init_indirect_register(dev, + pmci->base + M10BMC_PMCI_INDIRECT_BASE, + &m10bmc_pmci_regmap_config); + if (IS_ERR(pmci->m10bmc.regmap)) + return PTR_ERR(pmci->m10bmc.regmap); + + return m10bmc_dev_init(&pmci->m10bmc); +} + +#define FME_FEATURE_ID_PMCI_BMC 0x12 + +static const struct dfl_device_id pmci_ids[] = { + { FME_ID, FME_FEATURE_ID_PMCI_BMC }, + { } +}; +MODULE_DEVICE_TABLE(dfl, pmci_ids); + +static struct dfl_driver pmci_driver = { + .drv = { + .name = "intel-m10-bmc", + .dev_groups = m10bmc_dev_groups, + }, + .id_table = pmci_ids, + .probe = pmci_probe, +}; + +module_dfl_driver(pmci_driver); + +MODULE_DESCRIPTION("MAX10 BMC PMCI-based interface"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h index dd81ffdcf168..83c4d3993dcb 100644 --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h @@ -118,11 +118,19 @@ /* Address of 4KB inverted bit vector containing staging area FLASH count */ #define STAGING_FLASH_COUNT 0x17ffb000 +#define M10BMC_PMCI_SYS_BASE 0x0 +#define M10BMC_PMCI_SYS_END 0xfff + +/* Telemetry registers */ +#define M10BMC_PMCI_TELEM_START 0x400 +#define M10BMC_PMCI_TELEM_END 0x78c + /* Supported MAX10 BMC types */ enum m10bmc_type { M10_N3000, M10_D5005, M10_N5010, + M10_N6000 }; /** From patchwork Tue Jun 7 03:28:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12871324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73392C433EF for ; Tue, 7 Jun 2022 03:34:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236336AbiFGDcW (ORCPT ); Mon, 6 Jun 2022 23:32:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236316AbiFGDcS (ORCPT ); Mon, 6 Jun 2022 23:32:18 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03FB7C3E; Mon, 6 Jun 2022 20:32:12 -0700 (PDT) DKIM-Signature: v=1; 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06 Jun 2022 20:32:09 -0700 From: Tianfei Zhang To: yilun.xu@intel.com, lee.jones@linaro.org Cc: hao.wu@intel.com, trix@redhat.com, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org, russell.h.weight@intel.com, matthew.gerlach@linux.intel.com, Tianfei Zhang Subject: [PATCH v1 4/4] mfd: intel-m10-bmc: support multiple register layouts Date: Mon, 6 Jun 2022 23:28:33 -0400 Message-Id: <20220607032833.3482-5-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220607032833.3482-1-tianfei.zhang@intel.com> References: <20220607032833.3482-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org There are different base addresses for the MAX10 CSR regiter. Introducing a new data structure m10bmc_csr for the register definition of MAX10 CSR. Embedded m10bmc_csr into struct intel_m10bmc to support multiple register layouts. Signed-off-by: Tianfei Zhang --- drivers/mfd/intel-m10-bmc-core.c | 30 +++++++++++++++++++++++++----- include/linux/mfd/intel-m10-bmc.h | 20 +++++++++++++++++++- 2 files changed, 44 insertions(+), 6 deletions(-) diff --git a/drivers/mfd/intel-m10-bmc-core.c b/drivers/mfd/intel-m10-bmc-core.c index 20796f0c4a20..b37fcbadf279 100644 --- a/drivers/mfd/intel-m10-bmc-core.c +++ b/drivers/mfd/intel-m10-bmc-core.c @@ -10,6 +10,22 @@ #include #include +static const struct m10bmc_csr m10bmc_pmci_csr = { + .base = M10BMC_PMCI_SYS_BASE, + .build_version = M10BMC_PMCI_BUILD_VER, + .fw_version = NIOS2_PMCI_FW_VERSION, + .mac_low = M10BMC_PMCI_MAC_LOW, + .mac_high = M10BMC_PMCI_MAC_HIGH, +}; + +static const struct m10bmc_csr m10bmc_spi_csr = { + .base = M10BMC_SYS_BASE, + .build_version = M10BMC_BUILD_VER, + .fw_version = NIOS2_FW_VERSION, + .mac_low = M10BMC_MAC_LOW, + .mac_high = M10BMC_MAC_HIGH, +}; + static struct mfd_cell m10bmc_n6000_bmc_subdevs[] = { { .name = "n6000bmc-hwmon" }, { .name = "n6000bmc-sec-update" } @@ -40,7 +56,7 @@ static ssize_t bmc_version_show(struct device *dev, unsigned int val; int ret; - ret = m10bmc_sys_read(ddata, M10BMC_BUILD_VER, &val); + ret = m10bmc_sys_read(ddata, ddata->csr->build_version, &val); if (ret) return ret; @@ -55,7 +71,7 @@ static ssize_t bmcfw_version_show(struct device *dev, unsigned int val; int ret; - ret = m10bmc_sys_read(ddata, NIOS2_FW_VERSION, &val); + ret = m10bmc_sys_read(ddata, ddata->csr->fw_version, &val); if (ret) return ret; @@ -70,11 +86,11 @@ static ssize_t mac_address_show(struct device *dev, unsigned int macaddr_low, macaddr_high; int ret; - ret = m10bmc_sys_read(ddata, M10BMC_MAC_LOW, &macaddr_low); + ret = m10bmc_sys_read(ddata, ddata->csr->mac_low, &macaddr_low); if (ret) return ret; - ret = m10bmc_sys_read(ddata, M10BMC_MAC_HIGH, &macaddr_high); + ret = m10bmc_sys_read(ddata, ddata->csr->mac_high, &macaddr_high); if (ret) return ret; @@ -95,7 +111,7 @@ static ssize_t mac_count_show(struct device *dev, unsigned int macaddr_high; int ret; - ret = m10bmc_sys_read(ddata, M10BMC_MAC_HIGH, &macaddr_high); + ret = m10bmc_sys_read(ddata, ddata->csr->mac_high, &macaddr_high); if (ret) return ret; @@ -167,18 +183,22 @@ int m10bmc_dev_init(struct intel_m10bmc *m10bmc) case M10_N3000: cells = m10bmc_pacn3000_subdevs; n_cell = ARRAY_SIZE(m10bmc_pacn3000_subdevs); + m10bmc->csr = &m10bmc_spi_csr; break; case M10_D5005: cells = m10bmc_d5005_subdevs; n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs); + m10bmc->csr = &m10bmc_spi_csr; break; case M10_N5010: cells = m10bmc_n5010_subdevs; n_cell = ARRAY_SIZE(m10bmc_n5010_subdevs); + m10bmc->csr = &m10bmc_spi_csr; break; case M10_N6000: cells = m10bmc_n6000_bmc_subdevs; n_cell = ARRAY_SIZE(m10bmc_n6000_bmc_subdevs); + m10bmc->csr = &m10bmc_pmci_csr; break; default: return -ENODEV; diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h index 83c4d3993dcb..3a4fdab2acbd 100644 --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h @@ -125,6 +125,11 @@ #define M10BMC_PMCI_TELEM_START 0x400 #define M10BMC_PMCI_TELEM_END 0x78c +#define M10BMC_PMCI_BUILD_VER 0x0 +#define NIOS2_PMCI_FW_VERSION 0x4 +#define M10BMC_PMCI_MAC_LOW 0x20 +#define M10BMC_PMCI_MAC_HIGH 0x24 + /* Supported MAX10 BMC types */ enum m10bmc_type { M10_N3000, @@ -133,16 +138,29 @@ enum m10bmc_type { M10_N6000 }; +/** + * struct m10bmc_csr - Intel MAX 10 BMC CSR register + */ +struct m10bmc_csr { + unsigned int base; + unsigned int build_version; + unsigned int fw_version; + unsigned int mac_low; + unsigned int mac_high; +}; + /** * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure * @dev: this device * @regmap: the regmap used to access registers by m10bmc itself * @type: the type of MAX10 BMC + * @csr: the register definition of MAX10 BMC */ struct intel_m10bmc { struct device *dev; struct regmap *regmap; enum m10bmc_type type; + const struct m10bmc_csr *csr; }; /* @@ -174,7 +192,7 @@ m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr, * M10BMC_SYS_BASE accordingly. */ #define m10bmc_sys_read(m10bmc, offset, val) \ - m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val) + m10bmc_raw_read(m10bmc, m10bmc->csr->base + (offset), val) /* * MAX10 BMC Core support