From patchwork Tue Jun 7 08:59:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 12871618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95691C433EF for ; Tue, 7 Jun 2022 09:29:07 +0000 (UTC) Received: from localhost ([::1]:45982 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyVWM-0006Ju-Cx for qemu-devel@archiver.kernel.org; Tue, 07 Jun 2022 05:29:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyV3x-00073W-I1 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 04:59:46 -0400 Received: from mail.ispras.ru ([83.149.199.84]:39530) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyV3v-0005Mi-Dt for qemu-devel@nongnu.org; Tue, 07 Jun 2022 04:59:45 -0400 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id C78324076B37; Tue, 7 Jun 2022 08:59:19 +0000 (UTC) Subject: [PATCH 1/3] target/mips: introduce generic Cavium Octeon CPU model From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, f4bug@amsat.org, jiaxun.yang@flygoat.com, aurelien@aurel32.net, aleksandar.rikalo@syrmia.com Date: Tue, 07 Jun 2022 11:59:19 +0300 Message-ID: <165459235959.143371.13189201469172149052.stgit@pasha-ThinkPad-X280> In-Reply-To: <165459235408.143371.17715826203190085295.stgit@pasha-ThinkPad-X280> References: <165459235408.143371.17715826203190085295.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patch adds generic Octeon vCPU for providing Octeon-specific instructions. Signed-off-by: Pavel Dovgalyuk --- target/mips/cpu-defs.c.inc | 30 ++++++++++++++++++++++++++++++ target/mips/mips-defs.h | 1 + 2 files changed, 31 insertions(+) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 582f940070..a60e48433c 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -921,6 +921,36 @@ const mips_def_t mips_defs[] = .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2, .mmu_type = MMU_TYPE_R4000, }, + { + /* + * A generic CPU providing MIPS64 Cavium Octeon features. + * PRid is taken from Octeon 68xx CPUs + * FIXME: Eventually this should be replaced by a real CPU model. + */ + .name = "Octeon", + .CP0_PRid = 0x000D9100, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) , + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | + (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) | + (3U << CP0C4_MMUSizeExt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .CP0_PageGrain = (1 << CP0PG_ELPA), + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x12F8FFFF, + .SEGBITS = 42, + .PABITS = 49, + .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP, + .mmu_type = MMU_TYPE_R4000, + }, #endif }; diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 0a12d982a7..a6cebe0265 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -42,6 +42,7 @@ #define INSN_LOONGSON2E 0x0000040000000000ULL #define INSN_LOONGSON2F 0x0000080000000000ULL #define INSN_LOONGSON3A 0x0000100000000000ULL +#define INSN_OCTEON 0x0000200000000000ULL /* * bits 52-63: vendor-specific ASEs */ From patchwork Tue Jun 7 08:59:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 12871631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A7A5C433EF for ; Tue, 7 Jun 2022 09:32:35 +0000 (UTC) Received: from localhost ([::1]:49554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyVZi-0000UF-Cp for qemu-devel@archiver.kernel.org; Tue, 07 Jun 2022 05:32:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56208) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyV41-0007BT-Np for qemu-devel@nongnu.org; Tue, 07 Jun 2022 04:59:49 -0400 Received: from mail.ispras.ru ([83.149.199.84]:39564) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyV3z-0005NE-Qx for qemu-devel@nongnu.org; Tue, 07 Jun 2022 04:59:49 -0400 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id 2EEAC4142B3D; Tue, 7 Jun 2022 08:59:25 +0000 (UTC) Subject: [PATCH 2/3] target/mips: implement Octeon-specific BBIT instructions From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, f4bug@amsat.org, jiaxun.yang@flygoat.com, aurelien@aurel32.net, aleksandar.rikalo@syrmia.com Date: Tue, 07 Jun 2022 11:59:25 +0300 Message-ID: <165459236498.143371.12833007759486308114.stgit@pasha-ThinkPad-X280> In-Reply-To: <165459235408.143371.17715826203190085295.stgit@pasha-ThinkPad-X280> References: <165459235408.143371.17715826203190085295.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patch introduces Octeon-specific decoder and implements check-bit-and-jump instructions. Signed-off-by: Pavel Dovgalyuk --- target/mips/tcg/meson.build | 2 + target/mips/tcg/octeon.decode | 14 ++++++++++ target/mips/tcg/octeon_translate.c | 53 ++++++++++++++++++++++++++++++++++++ target/mips/tcg/translate.c | 5 +++ target/mips/tcg/translate.h | 1 + 5 files changed, 75 insertions(+) create mode 100644 target/mips/tcg/octeon.decode create mode 100644 target/mips/tcg/octeon_translate.c diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 98003779ae..7ee969ec8f 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -3,6 +3,7 @@ gen = [ decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'), + decodetree.process('octeon.decode', extra_args: '--decode=decode_ext_octeon'), ] mips_ss.add(gen) @@ -24,6 +25,7 @@ mips_ss.add(files( )) mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', + 'octeon_translate.c', ), if_false: files( 'mxu_translate.c', )) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode new file mode 100644 index 0000000000..c06d576292 --- /dev/null +++ b/target/mips/tcg/octeon.decode @@ -0,0 +1,14 @@ +# Octeon Architecture Module instruction set +# +# Copyright (C) 2022 Pavel Dovgalyuk +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# + +# Branch on bit set or clear +# BBIT0 110010 ..... ..... ................ +# BBIT032 110110 ..... ..... ................ +# BBIT1 111010 ..... ..... ................ +# BBIT132 111110 ..... ..... ................ + +BBIT 11 set:1 shift:1 10 rs:5 p:5 offset:16 diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c new file mode 100644 index 0000000000..bd87066b01 --- /dev/null +++ b/target/mips/tcg/octeon_translate.c @@ -0,0 +1,53 @@ +/* + * Octeon-specific instructions translation routines + * + * Copyright (c) 2022 Pavel Dovgalyuk + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "exec/helper-gen.h" +#include "translate.h" + +/* Include the auto-generated decoder. */ +#include "decode-octeon.c.inc" + +static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) +{ + int p = a->p; + + if (ctx->hflags & MIPS_HFLAG_BMASK) { +#ifdef MIPS_DEBUG_DISAS + LOG_DISAS("Branch in delay / forbidden slot at PC 0x" + TARGET_FMT_lx "\n", ctx->base.pc_next); +#endif + generate_exception_end(ctx, EXCP_RI); + return true; + } + + /* Load needed operands */ + TCGv t0 = tcg_temp_new(); + gen_load_gpr(t0, a->rs); + + if (a->shift) { + p += 32; + } + tcg_gen_andi_tl(t0, t0, 1ULL << p); + + /* Jump conditions */ + if (a->set) { + tcg_gen_setcondi_tl(TCG_COND_NE, bcond, t0, 0); + } else { + tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, t0, 0); + } + + ctx->hflags |= MIPS_HFLAG_BC; + ctx->btarget = ctx->base.pc_next + 4 + a->offset * 4; + ctx->hflags |= MIPS_HFLAG_BDS32; + + tcg_temp_free(t0); + return true; +} diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 6de5b66650..4f41a9b00a 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15963,6 +15963,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) { return; } +#if defined(TARGET_MIPS64) + if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) { + return; + } +#endif /* ISA extensions */ if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 9997fe2f3c..55053226ae 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -215,6 +215,7 @@ bool decode_ase_msa(DisasContext *ctx, uint32_t insn); bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); #if defined(TARGET_MIPS64) bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); +bool decode_ext_octeon(DisasContext *ctx, uint32_t insn); #endif bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn); From patchwork Tue Jun 7 08:59:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 12871632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8AD94C43334 for ; Tue, 7 Jun 2022 09:35:11 +0000 (UTC) Received: from localhost ([::1]:51918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyVcE-0002DG-Bh for qemu-devel@archiver.kernel.org; Tue, 07 Jun 2022 05:35:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56268) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyV47-0007OA-An for qemu-devel@nongnu.org; Tue, 07 Jun 2022 04:59:59 -0400 Received: from mail.ispras.ru ([83.149.199.84]:39584) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyV45-0005Ni-7A for qemu-devel@nongnu.org; Tue, 07 Jun 2022 04:59:55 -0400 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id 851254142B44; Tue, 7 Jun 2022 08:59:30 +0000 (UTC) Subject: [PATCH 3/3] target/mips: implement Octeon-specific arithmetic instructions From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, f4bug@amsat.org, jiaxun.yang@flygoat.com, aurelien@aurel32.net, aleksandar.rikalo@syrmia.com Date: Tue, 07 Jun 2022 11:59:30 +0300 Message-ID: <165459237035.143371.5795143736970750111.stgit@pasha-ThinkPad-X280> In-Reply-To: <165459235408.143371.17715826203190085295.stgit@pasha-ThinkPad-X280> References: <165459235408.143371.17715826203190085295.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patch implements several Octeon-specific instructions: - BADDU - DMUL - EXTS/EXTS32 - CINS/CINS32 - POP/DPOP - SEQ/SEQI - SNE/SNEI Signed-off-by: Pavel Dovgalyuk --- target/mips/helper.h | 1 target/mips/tcg/meson.build | 1 target/mips/tcg/octeon.decode | 25 +++++ target/mips/tcg/octeon_helper.c | 22 ++++ target/mips/tcg/octeon_helper.h.inc | 10 ++ target/mips/tcg/octeon_translate.c | 182 +++++++++++++++++++++++++++++++++++ 6 files changed, 241 insertions(+) create mode 100644 target/mips/tcg/octeon_helper.c create mode 100644 target/mips/tcg/octeon_helper.h.inc diff --git a/target/mips/helper.h b/target/mips/helper.h index de32d82e98..d68abdeac1 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -597,3 +597,4 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) /* Vendor extensions */ #include "tcg/vr54xx_helper.h.inc" +#include "tcg/octeon_helper.h.inc" diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 7ee969ec8f..1852366846 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -26,6 +26,7 @@ mips_ss.add(files( mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', 'octeon_translate.c', + 'octeon_helper.c', ), if_false: files( 'mxu_translate.c', )) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index c06d576292..ababf59e42 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -12,3 +12,28 @@ # BBIT132 111110 ..... ..... ................ BBIT 11 set:1 shift:1 10 rs:5 p:5 offset:16 + +# Arithmetic +# BADDU rd, rs, rt +# DMUL rd, rs, rt +# EXTS rt, rs, p, lenm1 +# EXTS32 rt, rs, p, lenm1 +# CINS rt, rs, p, lenm1 +# CINS32 rt, rs, p, lenm1 +# DPOP rd, rs +# POP rd, rs +# SEQ rd, rs, rt +# SEQI rt, rs, immediate +# SNE rd, rs, rt +# SNEI rt, rs, immediate + +@r3 ...... rs:5 rt:5 rd:5 ..... ...... +@bitfield ...... rs:5 rt:5 lenm1:5 p:5 ..... shift:1 + +BADDU 011100 ..... ..... ..... 00000 101000 @r3 +DMUL 011100 ..... ..... ..... 00000 000011 @r3 +EXTS 011100 ..... ..... ..... ..... 11101 . @bitfield +CINS 011100 ..... ..... ..... ..... 11001 . @bitfield +POP 011100 rs:5 00000 rd:5 00000 10110 dw:1 +SEQNE 011100 rs:5 rt:5 rd:5 00000 10101 ne:1 +SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1 diff --git a/target/mips/tcg/octeon_helper.c b/target/mips/tcg/octeon_helper.c new file mode 100644 index 0000000000..e9650c58bd --- /dev/null +++ b/target/mips/tcg/octeon_helper.c @@ -0,0 +1,22 @@ +/* + * MIPS Octeon emulation helpers + * + * Copyright (c) 2022 Pavel Dovgalyuk + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" + +target_ulong helper_pop(target_ulong arg) +{ + int i; + int res = 0; + for (i = 0 ; i < 64 ; ++i) { + res += arg & 1; + arg >>= 1; + } + + return res; +} diff --git a/target/mips/tcg/octeon_helper.h.inc b/target/mips/tcg/octeon_helper.h.inc new file mode 100644 index 0000000000..cfc051ef47 --- /dev/null +++ b/target/mips/tcg/octeon_helper.h.inc @@ -0,0 +1,10 @@ +/* + * MIPS Octeon emulation helpers + * + * Copyright (c) 2022 Pavel Dovgalyuk + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#if defined(TARGET_MIPS64) +DEF_HELPER_1(pop, tl, tl) +#endif diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c index bd87066b01..c4ef3e5bcb 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -51,3 +51,185 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) tcg_temp_free(t0); return true; } + +static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a) +{ + TCGv t0, t1; + + if (a->rt == 0) { + /* nop */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + gen_load_gpr(t0, a->rs); + gen_load_gpr(t1, a->rt); + + tcg_gen_add_tl(t0, t0, t1); + tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff); + + tcg_temp_free(t0); + tcg_temp_free(t1); + + return true; +} + +static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a) +{ + TCGv t0, t1; + + if (a->rt == 0) { + /* nop */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + gen_load_gpr(t0, a->rs); + gen_load_gpr(t1, a->rt); + + tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + + return true; +} + +static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a) +{ + TCGv t0, t1; + int p; + TCGLabel *l1; + + if (a->rt == 0) { + /* nop */ + return true; + } + + p = a->p; + if (a->shift) { + p += 32; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + gen_load_gpr(t1, a->rs); + + tcg_gen_movi_tl(t0, ((1ULL << (a->lenm1 + 1)) - 1) << p); + tcg_gen_and_tl(t1, t1, t0); + tcg_gen_movi_tl(t0, p); + tcg_gen_shr_tl(cpu_gpr[a->rt], t1, t0); + + l1 = gen_new_label(); + tcg_gen_movi_tl(t0, 1ULL << a->lenm1); + tcg_gen_and_tl(t0, cpu_gpr[a->rt], t0); + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); + tcg_gen_movi_tl(t0, ~((1ULL << (a->lenm1 + 1)) - 1)); + tcg_gen_or_tl(cpu_gpr[a->rt], cpu_gpr[a->rt], t0); + gen_set_label(l1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + + return true; +} + +static bool trans_CINS(DisasContext *ctx, arg_CINS *a) +{ + TCGv t0, t1; + + if (a->rt == 0) { + /* nop */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + gen_load_gpr(t1, a->rs); + + tcg_gen_movi_tl(t0, (1ULL << (a->lenm1 + 1)) - 1); + tcg_gen_and_tl(t1, t1, t0); + tcg_gen_movi_tl(t0, a->p + a->shift ? 32 : 0); + tcg_gen_shl_tl(cpu_gpr[a->rt], t1, t0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + + return true; +} + +static bool trans_POP(DisasContext *ctx, arg_POP *a) +{ + TCGv t0; + + if (a->rd == 0) { + /* nop */ + return true; + } + + t0 = tcg_temp_new(); + gen_load_gpr(t0, a->rs); + if (!a->dw) { + tcg_gen_andi_i64(t0, t0, 0xffffffff); + } + gen_helper_pop(cpu_gpr[a->rd], t0); + + tcg_temp_free(t0); + + return true; +} + +static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a) +{ + TCGv t0, t1; + + if (a->rd == 0) { + /* nop */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + gen_load_gpr(t0, a->rs); + gen_load_gpr(t1, a->rt); + + if (a->ne) { + tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr[a->rd], t1, t0); + } else { + tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0); + } + + tcg_temp_free(t0); + tcg_temp_free(t1); + + return true; +} + +static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a) +{ + TCGv t0; + + if (a->rt == 0) { + /* nop */ + return true; + } + + t0 = tcg_temp_new(); + + gen_load_gpr(t0, a->rs); + + /* Sign-extend to 64 bit value */ + target_ulong imm = a->imm; + if (a->ne) { + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm); + } else { + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm); + } + + tcg_temp_free(t0); + + return true; +}