From patchwork Tue Jun 7 13:16:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 12871917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C402FC43334 for ; Tue, 7 Jun 2022 13:18:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vMkw4TCMu0D94LpuwsDIIRXiblMGd5GWtwvdC25HayI=; b=XNqm/HaQDYXpWM y/ShWnbPir/Kh+XDOa/Th//56ltobmF6aSiBU3Go77JwXAvEBv0hkTK5llWDmIxthj7CgiIC9fPdv JhldvCWKhh2JZTCi0rXgrxElCsb6bc93dYJxPAA8x3/+VTKmZLMRV1pjhfQiuDLnMCh7UUPdNCaD9 sMMIHeBxMsq1fV2KDphpvcDdAopf4As6x5CNzCy8F0z/5IimFmMmtVdfklNwJYGSAbrzn2jKsP/xe TkAFPT9iBOLdsgAQRIGrb8D7ihaqDgcVjrOk6VmwVYKFOAwo8M9sYXFEAnTTzSIS60ZCdy2/vGUb0 B54RkKORUs15VWQbf+KQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nyZ5k-007cwS-D3; Tue, 07 Jun 2022 13:17:52 +0000 Received: from forward501o.mail.yandex.net ([2a02:6b8:0:1a2d::611]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nyZ5H-007cXS-RX; Tue, 07 Jun 2022 13:17:26 +0000 Received: from myt6-26f37b5fec36.qloud-c.yandex.net (myt6-26f37b5fec36.qloud-c.yandex.net [IPv6:2a02:6b8:c12:5527:0:640:26f3:7b5f]) by forward501o.mail.yandex.net (Yandex) with ESMTP id 5183B45C4E6C; Tue, 7 Jun 2022 16:16:56 +0300 (MSK) Received: from myt6-654ec0a0ab93.qloud-c.yandex.net (myt6-654ec0a0ab93.qloud-c.yandex.net [2a02:6b8:c12:1d80:0:640:654e:c0a0]) by myt6-26f37b5fec36.qloud-c.yandex.net (mxback/Yandex) with ESMTP id smaqJmKSH2-GtfeQLwf; Tue, 07 Jun 2022 16:16:56 +0300 X-Yandex-Fwd: 2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1654607816; bh=JvNF2tl4VACbLjlnTM0H4TIIrNNoBngMOz0q/FiVjZc=; h=In-Reply-To:References:Date:Subject:Cc:To:From:Message-Id; b=GwKizgbQ3nskMntGKiwqljCR4wdHj/+4vKGtzccxpe1C/zu43jeu6N0Z3YY5QLCNE uWEItwdNbsgAJmICe+XDiErcvn3CS65MmNoFUGN0PfOcQSFjUzRzFl72WtYX3ApqD+ camc4PT2YMpr77TN4A0atwWhVWkaHMLY0zq6/QmQ= Authentication-Results: myt6-26f37b5fec36.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by myt6-654ec0a0ab93.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id sOXgg17Zrk-GrM4PiLo; Tue, 07 Jun 2022 16:16:53 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin To: Cc: Genevieve Chan , =?utf-8?b?Sm/Do28gTcOh?= =?utf-8?b?cmlvIERvbWluZ29z?= , Nikita Shubin , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Mark Rutland , Geert Uytterhoeven , linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM PMU PROFILING AND DEBUGGING) Subject: [PATCH v3 1/4] RISC-V: Create unique identification for SoC PMU Date: Tue, 7 Jun 2022 16:16:44 +0300 Message-Id: <20220607131648.29439-2-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607131648.29439-1-nikita.shubin@maquefel.me> References: <20220607131648.29439-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_061724_367808_1B1DBC6B X-CRM114-Status: GOOD ( 15.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: João Mário Domingos The SBI PMU platform driver did not provide any identification for perf events matching. This patch introduces a new sysfs file inside the platform device (soc:pmu/id) for pmu identification. The identification is a 64-bit value generated as: [63-32]: mvendorid; [31]: marchid[MSB]; [30-16]: marchid[15-0]; [15-0]: mimpid[15MSBs]; The CSRs are detailed in the RISC-V privileged spec [1]. The marchid is split in MSB + 15LSBs, due to the MSB being used for open-source architecture identification. [1] https://github.com/riscv/riscv-isa-manual Signed-off-by: João Mário Domingos Tested-by: Nikita Shubin --- arch/riscv/kernel/sbi.c | 3 +++ drivers/perf/riscv_pmu_sbi.c | 47 ++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 775d3322b422..50dd9b6ecc9e 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -627,16 +627,19 @@ long sbi_get_mvendorid(void) { return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID); } +EXPORT_SYMBOL(sbi_get_mvendorid); long sbi_get_marchid(void) { return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID); } +EXPORT_SYMBOL(sbi_get_marchid); long sbi_get_mimpid(void) { return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID); } +EXPORT_SYMBOL(sbi_get_mimpid); static void sbi_send_cpumask_ipi(const struct cpumask *target) { diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index a1317a483512..15ab3dc68e7a 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -693,6 +693,46 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde return 0; } +static uint64_t pmu_sbi_get_pmu_id(void) +{ + union sbi_pmu_id { + uint64_t value; + struct { + uint16_t imp:16; + uint16_t arch:16; + uint32_t vendor:32; + }; + } pmuid; + + pmuid.value = 0; + pmuid.vendor = (uint32_t) sbi_get_mvendorid(); + pmuid.arch = (sbi_get_marchid() >> (63 - 15) & (1 << 15)) | (sbi_get_marchid() & 0x7FFF); + pmuid.imp = (sbi_get_mimpid() >> 16); + + return pmuid.value; +} + +static ssize_t pmu_sbi_id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len; + + len = sprintf(buf, "0x%llx\n", pmu_sbi_get_pmu_id()); + if (len <= 0) + dev_err(dev, "mydrv: Invalid sprintf len: %dn", len); + + return len; +} + +static DEVICE_ATTR(id, S_IRUGO | S_IWUSR, pmu_sbi_id_show, 0); + +static struct attribute *pmu_sbi_attrs[] = { + &dev_attr_id.attr, + NULL +}; + +ATTRIBUTE_GROUPS(pmu_sbi); + static int pmu_sbi_device_probe(struct platform_device *pdev) { struct riscv_pmu *pmu = NULL; @@ -729,6 +769,13 @@ static int pmu_sbi_device_probe(struct platform_device *pdev) pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx; pmu->ctr_read = pmu_sbi_ctr_read; + ret = sysfs_create_group(&pdev->dev.kobj, &pmu_sbi_group); + if (ret) { + dev_err(&pdev->dev, "sysfs creation failed\n"); + return ret; + } + pdev->dev.groups = pmu_sbi_groups; + ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); if (ret) return ret; From patchwork Tue Jun 7 13:16:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 12871914 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B3B5C43334 for ; Tue, 7 Jun 2022 13:17:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; 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Tue, 07 Jun 2022 16:16:59 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin To: Cc: Genevieve Chan , =?utf-8?b?Sm/Do28gTcOh?= =?utf-8?b?cmlvIERvbWluZ29z?= , Nikita Shubin , Atish Patra , Anup Patel , Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-kernel@vger.kernel.org (open list), linux-riscv@lists.infradead.org (open list:RISC-V PMU DRIVERS), linux-arm-kernel@lists.infradead.org (moderated list:ARM PMU PROFILING AND DEBUGGING), linux-perf-users@vger.kernel.org (open list:PERFORMANCE EVENTS SUBSYSTEM) Subject: [PATCH v3 2/4] RISC-V: Support CPUID for risc-v in perf Date: Tue, 7 Jun 2022 16:16:45 +0300 Message-Id: <20220607131648.29439-3-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607131648.29439-1-nikita.shubin@maquefel.me> References: <20220607131648.29439-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_061708_176782_D16D8B72 X-CRM114-Status: GOOD ( 19.75 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: João Mário Domingos This patch creates the header.c file for the risc-v architecture and introduces support for PMU identification through sysfs. It is now possible to configure pmu-events in risc-v. Depends on patch [1], that introduces the id sysfs file. Signed-off-by: João Mário Domingos [Nikita: replaced soc:pmu to riscv-pmu/id] Signed-off-by: Nikita Shubin Tested-by: Nikita Shubin --- v2->v3: - Change 'soc/soc:pmu/id' to 'riscv-pmu/id' --- drivers/perf/riscv_pmu.c | 18 ++++++++ tools/perf/arch/riscv/util/Build | 1 + tools/perf/arch/riscv/util/header.c | 66 +++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 tools/perf/arch/riscv/util/header.c diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c index b2b8d2074ed0..d1aa4e0e527f 100644 --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -17,6 +17,23 @@ #include +PMU_FORMAT_ATTR(event, "config:0-63"); + +static struct attribute *riscv_arch_formats_attr[] = { + &format_attr_event.attr, + NULL, +}; + +static struct attribute_group riscv_pmu_format_group = { + .name = "format", + .attrs = riscv_arch_formats_attr, +}; + +static const struct attribute_group *riscv_pmu_attr_groups[] = { + &riscv_pmu_format_group, + NULL, +}; + static unsigned long csr_read_num(int csr_num) { #define switchcase_csr_read(__csr_num, __val) {\ @@ -307,6 +324,7 @@ struct riscv_pmu *riscv_pmu_alloc(void) cpuc->events[i] = NULL; } pmu->pmu = (struct pmu) { + .attr_groups = riscv_pmu_attr_groups, .event_init = riscv_pmu_event_init, .add = riscv_pmu_add, .del = riscv_pmu_del, diff --git a/tools/perf/arch/riscv/util/Build b/tools/perf/arch/riscv/util/Build index 7d3050134ae0..603dbb5ae4dc 100644 --- a/tools/perf/arch/riscv/util/Build +++ b/tools/perf/arch/riscv/util/Build @@ -1,4 +1,5 @@ perf-y += perf_regs.o +perf-y += header.o perf-$(CONFIG_DWARF) += dwarf-regs.o perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o diff --git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c new file mode 100644 index 000000000000..98d40b87c9f3 --- /dev/null +++ b/tools/perf/arch/riscv/util/header.c @@ -0,0 +1,66 @@ +#include +#include +#include +#include +#include "../../util/debug.h" +#include "../../util/header.h" + +#define STR_LEN 1024 +#define ID_SIZE 64 + +static int _get_cpuid(char *buf, size_t sz) +{ + const char *sysfs = sysfs__mountpoint(); + u64 id = 0; + char path[PATH_MAX]; + FILE *file; + + if (!sysfs || sz < ID_SIZE) + return -EINVAL; + + scnprintf(path, PATH_MAX, "%s/devices/platform/riscv-pmu/id", + sysfs); + + file = fopen(path, "r"); + if (!file) { + pr_debug("fopen failed for file %s\n", path); + return -EINVAL; + } + if (!fgets(buf, ID_SIZE, file)) { + fclose(file); + return -EINVAL; + } + + fclose(file); + + /*Check if value is numeric and remove special characters*/ + id = strtoul(buf, NULL, 16); + if (!id) + return -EINVAL; + scnprintf(buf, ID_SIZE, "0x%lx", id); + + return 0; +} + +char *get_cpuid_str(struct perf_pmu *pmu __maybe_unused) +{ + char *buf = NULL; + int res; + + if (!pmu) + return NULL; + + buf = malloc(ID_SIZE); + if (!buf) + return NULL; + + /* read id */ + res = _get_cpuid(buf, ID_SIZE); + if (res) { + pr_err("failed to get cpuid string for PMU %s\n", pmu->name); + free(buf); + buf = NULL; + } + + return buf; +} From patchwork Tue Jun 7 13:16:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 12871916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB354C43334 for ; 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dkim=pass header.i=@maquefel.me Received: by myt6-654ec0a0ab93.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id sOXgg17Zrk-H5M4o90G; Tue, 07 Jun 2022 16:17:05 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin To: Cc: Genevieve Chan , =?utf-8?b?Sm/Do28gTcOh?= =?utf-8?b?cmlvIERvbWluZ29z?= , Nikita Shubin , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kernel@vger.kernel.org (open list), linux-perf-users@vger.kernel.org (open list:PERFORMANCE EVENTS SUBSYSTEM), linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE) Subject: [PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile Date: Tue, 7 Jun 2022 16:16:46 +0300 Message-Id: <20220607131648.29439-4-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607131648.29439-1-nikita.shubin@maquefel.me> References: <20220607131648.29439-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_061724_348695_5862B7D4 X-CRM114-Status: GOOD ( 13.08 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: João Mário Domingos The pmu-events now supports custom events for RISC-V, plus the cycle, time and instret events were defined. Signed-off-by: João Mário Domingos Tested-by: Nikita Shubin --- tools/perf/pmu-events/arch/riscv/mapfile.csv | 14 +++++++++++++ .../pmu-events/arch/riscv/riscv-generic.json | 20 +++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv new file mode 100644 index 000000000000..4f2aa199d9cb --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -0,0 +1,14 @@ +# Format: +# MIDR,Version,JSON/file/pathname,Type +# +# where +# MIDR Processor version +# Variant[23:20] and Revision [3:0] should be zero. +# Version could be used to track version of JSON file +# but currently unused. +# JSON/file/pathname is the path to JSON file, relative +# to tools/perf/pmu-events/arch/riscv/. +# Type is core, uncore etc +# +# +#Family-model,Version,Filename,EventType diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json b/tools/perf/pmu-events/arch/riscv/riscv-generic.json new file mode 100644 index 000000000000..013e50efad99 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json @@ -0,0 +1,20 @@ +[ + { + "PublicDescription": "CPU Cycles", + "EventCode": "0x00", + "EventName": "riscv_cycles", + "BriefDescription": "CPU cycles RISC-V generic counter" + }, + { + "PublicDescription": "CPU Time", + "EventCode": "0x01", + "EventName": "riscv_time", + "BriefDescription": "CPU time RISC-V generic counter" + }, + { + "PublicDescription": "CPU Instructions", + "EventCode": "0x02", + "EventName": "riscv_instret", + "BriefDescription": "CPU retired instructions RISC-V generic counter" + } +] \ No newline at end of file From patchwork Tue Jun 7 13:16:47 2022 Content-Type: text/plain; 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Tue, 07 Jun 2022 16:17:15 +0300 X-Yandex-Fwd: 2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1654607835; bh=T/sjv6r+evzZz3D9hOnrBsFuwTi03hkMjzMpfeipj8g=; h=In-Reply-To:References:Date:Subject:Cc:To:From:Message-Id; b=l5oGOhT7hZTF8satbdLVJ0oUXVdcdHju83EkF1ccx4nf2uh4NtHjtBlJ8FXfFwklS 2jXlFB5FC2zIaXKj4+YrRxIcpVZQmroRUDUdUpuhuWC3fnDJTKITWlQ9k/QUkw6CKk Iqdsr29Somb6sF5nZVmwwj4juo6G22c9zqjhzagk= Authentication-Results: myt5-3819f28180eb.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by myt6-654ec0a0ab93.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id sOXgg17Zrk-HEM4WJNa; Tue, 07 Jun 2022 16:17:14 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin To: Cc: Genevieve Chan , =?utf-8?b?Sm/Do28gTcOh?= =?utf-8?b?cmlvIERvbWluZ29z?= , Nikita Shubin , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kernel@vger.kernel.org (open list), linux-perf-users@vger.kernel.org (open list:PERFORMANCE EVENTS SUBSYSTEM), linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE) Subject: [PATCH v3 4/4] RISC-V: Added HiFive Unmatched PMU events Date: Tue, 7 Jun 2022 16:16:47 +0300 Message-Id: <20220607131648.29439-5-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607131648.29439-1-nikita.shubin@maquefel.me> References: <20220607131648.29439-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_061722_872914_A4DAFC04 X-CRM114-Status: GOOD ( 14.14 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: João Mário Domingos This patch contains all the available events for the HiFive Unmatched performance monitoring unit. Depends on patch [3], for the base mapfile.csv file. Signed-off-by: João Mário Domingos Tested-by: Nikita Shubin --- tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + .../arch/riscv/sifive/u74/instructions.json | 92 +++++++++++++++++++ .../arch/riscv/sifive/u74/memory.json | 32 +++++++ .../arch/riscv/sifive/u74/microarch.json | 57 ++++++++++++ 4 files changed, 182 insertions(+) create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv index 4f2aa199d9cb..bda3fb9382f1 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -12,3 +12,4 @@ # # #Family-model,Version,Filename,EventType +0x48980072018,v1,sifive/u74,core diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json new file mode 100644 index 000000000000..5eab718c9256 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json @@ -0,0 +1,92 @@ +[ + { + "EventName": "EXCEPTION_TAKEN", + "EventCode": "0x0000100", + "BriefDescription": "Exception taken" + }, + { + "EventName": "INTEGER_LOAD_RETIRED", + "EventCode": "0x0000200", + "BriefDescription": "Integer load instruction retired" + }, + { + "EventName": "INTEGER_STORE_RETIRED", + "EventCode": "0x0000400", + "BriefDescription": "Integer store instruction retired" + }, + { + "EventName": "ATOMIC_MEMORY_RETIRED", + "EventCode": "0x0000800", + "BriefDescription": "Atomic memory operation retired" + }, + { + "EventName": "SYSTEM_INSTRUCTION_RETIRED", + "EventCode": "0x0001000", + "BriefDescription": "System instruction retired" + }, + { + "EventName": "INTEGER_ARITHMETIC_RETIRED", + "EventCode": "0x0002000", + "BriefDescription": "Integer arithmetic instruction retired" + }, + { + "EventName": "CONDITIONAL_BRANCH_RETIRED", + "EventCode": "0x0004000", + "BriefDescription": "Conditional branch retired" + }, + { + "EventName": "JAL_INSTRUCTION_RETIRED", + "EventCode": "0x0008000", + "BriefDescription": "JAL instruction retired" + }, + { + "EventName": "JALR_INSTRUCTION_RETIRED", + "EventCode": "0x0010000", + "BriefDescription": "JALR instruction retired" + }, + { + "EventName": "INTEGER_MULTIPLICATION_RETIRED", + "EventCode": "0x0020000", + "BriefDescription": "Integer multiplication instruction retired" + }, + { + "EventName": "INTEGER_DIVISION_RETIRED", + "EventCode": "0x0040000", + "BriefDescription": "Integer division instruction retired" + }, + { + "EventName": "FP_LOAD_RETIRED", + "EventCode": "0x0080000", + "BriefDescription": "Floating-point load instruction retired" + }, + { + "EventName": "FP_STORE_RETIRED", + "EventCode": "0x0100000", + "BriefDescription": "Floating-point store instruction retired" + }, + { + "EventName": "FP_ADDITION_RETIRED", + "EventCode": "0x0200000", + "BriefDescription": "Floating-point addition retired" + }, + { + "EventName": "FP_MULTIPLICATION_RETIRED", + "EventCode": "0x0400000", + "BriefDescription": "Floating-point multiplication retired" + }, + { + "EventName": "FP_FUSEDMADD_RETIRED", + "EventCode": "0x0800000", + "BriefDescription": "Floating-point fused multiply-add retired" + }, + { + "EventName": "FP_DIV_SQRT_RETIRED", + "EventCode": "0x1000000", + "BriefDescription": "Floating-point division or square-root retired" + }, + { + "EventName": "OTHER_FP_RETIRED", + "EventCode": "0x2000000", + "BriefDescription": "Other floating-point instruction retired" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json new file mode 100644 index 000000000000..be1a46312ac3 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json @@ -0,0 +1,32 @@ +[ + { + "EventName": "ICACHE_RETIRED", + "EventCode": "0x0000102", + "BriefDescription": "Instruction cache miss" + }, + { + "EventName": "DCACHE_MISS_MMIO_ACCESSES", + "EventCode": "0x0000202", + "BriefDescription": "Data cache miss or memory-mapped I/O access" + }, + { + "EventName": "DCACHE_WRITEBACK", + "EventCode": "0x0000402", + "BriefDescription": "Data cache write-back" + }, + { + "EventName": "INST_TLB_MISS", + "EventCode": "0x0000802", + "BriefDescription": "Instruction TLB miss" + }, + { + "EventName": "DATA_TLB_MISS", + "EventCode": "0x0001002", + "BriefDescription": "Data TLB miss" + }, + { + "EventName": "UTLB_MISS", + "EventCode": "0x0002002", + "BriefDescription": "UTLB miss" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json new file mode 100644 index 000000000000..50ffa55418cb --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json @@ -0,0 +1,57 @@ +[ + { + "EventName": "ADDRESSGEN_INTERLOCK", + "EventCode": "0x0000101", + "BriefDescription": "Address-generation interlock" + }, + { + "EventName": "LONGLAT_INTERLOCK", + "EventCode": "0x0000201", + "BriefDescription": "Long-latency interlock" + }, + { + "EventName": "CSR_READ_INTERLOCK", + "EventCode": "0x0000401", + "BriefDescription": "CSR read interlock" + }, + { + "EventName": "ICACHE_ITIM_BUSY", + "EventCode": "0x0000801", + "BriefDescription": "Instruction cache/ITIM busy" + }, + { + "EventName": "DCACHE_DTIM_BUSY", + "EventCode": "0x0001001", + "BriefDescription": "Data cache/DTIM busy" + }, + { + "EventName": "BRANCH_DIRECTION_MISPREDICTION", + "EventCode": "0x0002001", + "BriefDescription": "Branch direction misprediction" + }, + { + "EventName": "BRANCH_TARGET_MISPREDICTION", + "EventCode": "0x0004001", + "BriefDescription": "Branch/jump target misprediction" + }, + { + "EventName": "PIPE_FLUSH_CSR_WRITE", + "EventCode": "0x0008001", + "BriefDescription": "Pipeline flush from CSR write" + }, + { + "EventName": "PIPE_FLUSH_OTHER_EVENT", + "EventCode": "0x0010001", + "BriefDescription": "Pipeline flush from other event" + }, + { + "EventName": "INTEGER_MULTIPLICATION_INTERLOCK", + "EventCode": "0x0020001", + "BriefDescription": "Integer multiplication interlock" + }, + { + "EventName": "FP_INTERLOCK", + "EventCode": "0x0040001", + "BriefDescription": "Floating-point interlock" + } +] \ No newline at end of file