From patchwork Wed Jun 8 08:35:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12873023 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EA9517FB for ; Wed, 8 Jun 2022 08:36:16 +0000 (UTC) X-UUID: b566a5b6eae447c9897858eace2fbdea-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:0d5b83aa-2477-46cd-b412-e843e534e382,OB:0,LO B:20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:95 X-CID-INFO: VERSION:1.1.5,REQID:0d5b83aa-2477-46cd-b412-e843e534e382,OB:0,LOB: 20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09,CLOUDID:ac2415e5-2ba2-4dc1-b6c5-11feb6c769e0,C OID:ab9fe7398c47,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: b566a5b6eae447c9897858eace2fbdea-20220608 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 788356503; Wed, 08 Jun 2022 16:36:03 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Lee Jones , Benson Leung , "Guenter Roeck" , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 1/9] dt-binding: remoteproc: mediatek: Support dual-core SCP Date: Wed, 8 Jun 2022 16:35:45 +0800 Message-ID: <20220608083553.8697-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N The MT8195 SCP co-processor is a dual-core RISC-V MCU. Add a new property to reference the sibling core and to assign core id to SCP nodes. Also add a new compatile for the driver of SCP 2nd core. Signed-off-by: Tinghan Shen Reviewed-by: Rob Herring --- .../devicetree/bindings/remoteproc/mtk,scp.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml index eec3b9c4c713..4576ff9b1f2d 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt8186-scp - mediatek,mt8192-scp - mediatek,mt8195-scp + - mediatek,mt8195-scp-dual reg: description: @@ -57,6 +58,17 @@ properties: memory-region: maxItems: 1 + mediatek,scp-core: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + Reference to the sibling SCP core. This is required to + enable support for dual-core SCP. + items: + - items: + - description: Phandle of sibling SCP node. + - description: Core id of this SCP node + enum: [0, 1] + required: - compatible - reg @@ -115,6 +127,7 @@ examples: reg-names = "sram", "cfg", "l1tcm"; clocks = <&infracfg CLK_INFRA_SCPSYS>; clock-names = "main"; + mediatek,scp-core = <&scp_dual 0>; cros_ec { mediatek,rpmsg-name = "cros-ec-rpmsg"; From patchwork Wed Jun 8 08:35:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12873036 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D41E87B for ; Wed, 8 Jun 2022 08:37:25 +0000 (UTC) X-UUID: a7cb309ee8e24eb09d43e1b2af1509dd-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:1e3e44ea-f46a-4ea5-8e99-c65a970772f7,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,ACT ION:release,TS:95 X-CID-INFO: VERSION:1.1.5,REQID:1e3e44ea-f46a-4ea5-8e99-c65a970772f7,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,ACT ION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09,CLOUDID:b03a15e5-2ba2-4dc1-b6c5-11feb6c769e0,C OID:8f91e81df6c9,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: a7cb309ee8e24eb09d43e1b2af1509dd-20220608 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 212095045; Wed, 08 Jun 2022 16:37:21 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Lee Jones , Benson Leung , Guenter Roeck , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 2/9] remoteproc: mediatek: Support hanlding scp core 1 wdt timeout Date: Wed, 8 Jun 2022 16:35:46 +0800 Message-ID: <20220608083553.8697-3-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N MT8195 SCP is a dual-core processor. The SCP core 1 watchdog timeout interrupt uses the same interrupt line of SCP core 0 watchdog timeout interrupt. Add support for handling SCP core 1 watchdog timeout interrupt in the SCP IRQ handler. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_common.h | 4 ++++ drivers/remoteproc/mtk_scp.c | 27 ++++++++++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index ea6fa1100a00..73e8adf00de3 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -54,6 +54,10 @@ #define MT8192_CORE0_WDT_IRQ 0x10030 #define MT8192_CORE0_WDT_CFG 0x10034 +#define MT8195_SYS_STATUS 0x4004 +#define MT8195_CORE0_WDT BIT(16) +#define MT8195_CORE1_WDT BIT(17) + #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) #define SCP_FW_VER_LEN 32 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 47b2a40e1b4a..3510c6d0bbc8 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -212,6 +212,31 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } +static void mt8195_scp_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { + scp_ipi_handler(scp); + + /* + * SCP won't send another interrupt until we clear + * MT8192_SCP2APMCU_IPC. + */ + writel(MT8192_SCP_IPC_INT_BIT, + scp->reg_base + MT8192_SCP2APMCU_IPC_CLR); + } else { + if (readl(scp->reg_base + MT8195_SYS_STATUS) & MT8195_CORE1_WDT) { + writel(1, scp->reg_base + MT8195_CORE1_WDT_IRQ); + } else { + writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ); + scp_wdt_handler(scp, scp_to_host); + } + } +} + static irqreturn_t scp_irq_handler(int irq, void *priv) { struct mtk_scp *scp = priv; @@ -961,7 +986,7 @@ static const struct mtk_scp_of_data mt8192_of_data = { static const struct mtk_scp_of_data mt8195_of_data = { .scp_clk_get = mt8195_scp_clk_get, .scp_before_load = mt8195_scp_before_load, - .scp_irq_handler = mt8192_scp_irq_handler, + .scp_irq_handler = mt8195_scp_irq_handler, .scp_reset_assert = mt8192_scp_reset_assert, .scp_reset_deassert = mt8192_scp_reset_deassert, .scp_stop = mt8195_scp_stop, From patchwork Wed Jun 8 08:35:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12873020 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCFEC18F for ; Wed, 8 Jun 2022 08:36:15 +0000 (UTC) X-UUID: 048a3eaa67b9411fa163e65141b652ba-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:cdb083ea-238d-44b5-b0c2-5e1e28fce40f,OB:0,LO B:10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:90 X-CID-INFO: VERSION:1.1.5,REQID:cdb083ea-238d-44b5-b0c2-5e1e28fce40f,OB:0,LOB: 10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:90 X-CID-META: VersionHash:2a19b09,CLOUDID:b27c9f7e-c8dc-403a-96e8-6237210dceee,C OID:049188456f91,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: 048a3eaa67b9411fa163e65141b652ba-20220608 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 285445624; Wed, 08 Jun 2022 16:36:03 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Lee Jones , Benson Leung , "Guenter Roeck" , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 3/9] remoteproc: mediatek: Add SCP core 1 register definitions Date: Wed, 8 Jun 2022 16:35:47 +0800 Message-ID: <20220608083553.8697-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Add MT8195 SCP core 1 related register definitions. Signed-off-by: Tinghan Shen Reviewed-by: Mathieu Poirier --- drivers/remoteproc/mtk_common.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index 73e8adf00de3..5582f4207fbf 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -47,6 +47,7 @@ #define MT8192_SCP2SPM_IPC_CLR 0x4094 #define MT8192_GIPC_IN_SET 0x4098 #define MT8192_HOST_IPC_INT_BIT BIT(0) +#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4) #define MT8192_CORE0_SW_RSTN_CLR 0x10000 #define MT8192_CORE0_SW_RSTN_SET 0x10004 @@ -60,6 +61,26 @@ #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) +#define MT8195_CPU1_SRAM_PD 0x1084 +#define MT8195_SSHUB2APMCU_IPC_SET 0x4088 +#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C +#define MT8195_CORE1_SW_RSTN_CLR 0x20000 +#define MT8195_CORE1_SW_RSTN_SET 0x20004 +#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_IRQ 0x20030 +#define MT8195_CORE1_WDT_CFG 0x20034 + +#define MT8195_SEC_CTRL 0x85000 +#define MT8195_CORE_OFFSET_ENABLE_D BIT(13) +#define MT8195_CORE_OFFSET_ENABLE_I BIT(12) +#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0 +#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4 +#define MT8195_L2TCM_OFFSET 0x850d0 +#define SCP_SRAM_REMAP_LOW 0 +#define SCP_SRAM_REMAP_HIGH 1 +#define SCP_SRAM_REMAP_OFFSET 2 +#define SCP_SRAM_REMAP_SIZE 3 + #define SCP_FW_VER_LEN 32 #define SCP_SHARE_BUFFER_SIZE 288 From patchwork Wed Jun 8 08:35:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12873021 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEF8217F9 for ; Wed, 8 Jun 2022 08:36:15 +0000 (UTC) X-UUID: 4470ec7dfb57491faada2c210a6babfb-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:970d56f0-9126-468c-a77c-e980752fd990,OB:10,L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:95 X-CID-INFO: VERSION:1.1.5,REQID:970d56f0-9126-468c-a77c-e980752fd990,OB:10,LOB :0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09,CLOUDID:3e2515e5-2ba2-4dc1-b6c5-11feb6c769e0,C OID:ab9fe7398c47,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: 4470ec7dfb57491faada2c210a6babfb-20220608 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 676625393; Wed, 08 Jun 2022 16:36:04 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Lee Jones , Benson Leung , "Guenter Roeck" , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 4/9] remoteproc: mediatek: Support probing for the 2nd core of dual-core SCP Date: Wed, 8 Jun 2022 16:35:48 +0800 Message-ID: <20220608083553.8697-5-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N The mtk_scp.c driver only supports the single core SCP and the 1st core of a dual-core SCP. This patch extends it for the 2nd core. MT8195 SCP is a dual-core MCU. Both cores are housed in the same subsys. They have the same viewpoint of registers and memory. Core 1 of the SCP features its own set of core configuration registers, interrupt controller, timers, and DMAs. The rest of the peripherals in this subsystem are shared by core 0 and core 1. As for memory, core 1 has its own cache memory. the SCP SRAM is shared by core 0 and core 1. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_scp.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 3510c6d0bbc8..91b4aefde4ac 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -23,6 +23,10 @@ #define MAX_CODE_SIZE 0x500000 #define SECTION_NAME_IPI_BUFFER ".ipi_buffer" +#define SCP_CORE_0 0 +#define SCP_CORE_1 1 +#define SCP_CORE_SINGLE 0xF + /** * scp_get() - get a reference to SCP. * @@ -836,6 +840,7 @@ static int scp_probe(struct platform_device *pdev) struct resource *res; const char *fw_name = "scp.img"; int ret, i; + u32 core_id = SCP_CORE_SINGLE; ret = rproc_of_parse_firmware(dev, 0, &fw_name); if (ret < 0 && ret != -EINVAL) @@ -851,8 +856,16 @@ static int scp_probe(struct platform_device *pdev) scp->data = of_device_get_match_data(dev); platform_set_drvdata(pdev, scp); + ret = of_property_read_u32_index(dev->of_node, "mediatek,scp-core", 1, &core_id); + if (ret == 0) + dev_info(dev, "Boot SCP dual core %u\n", core_id); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); - scp->sram_base = devm_ioremap_resource(dev, res); + if (core_id == SCP_CORE_1) + scp->sram_base = devm_ioremap(dev, res->start, resource_size(res)); + else + scp->sram_base = devm_ioremap_resource(dev, res); + if (IS_ERR(scp->sram_base)) return dev_err_probe(dev, PTR_ERR(scp->sram_base), "Failed to parse and map sram memory\n"); @@ -873,7 +886,12 @@ static int scp_probe(struct platform_device *pdev) scp->l1tcm_phys = res->start; } - scp->reg_base = devm_platform_ioremap_resource_byname(pdev, "cfg"); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + if (core_id == SCP_CORE_1) + scp->reg_base = devm_ioremap(dev, res->start, resource_size(res)); + else + scp->reg_base = devm_ioremap_resource(dev, res); + if (IS_ERR(scp->reg_base)) return dev_err_probe(dev, PTR_ERR(scp->reg_base), "Failed to parse and map cfg memory\n"); From patchwork Wed Jun 8 08:35:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12873024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF6F317FA for ; Wed, 8 Jun 2022 08:36:17 +0000 (UTC) X-UUID: c835ab158e284bddb1877ac900538f02-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:f3055498-72a6-4c8e-b6f1-c622fac0ef7e,OB:20,L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.5,REQID:f3055498-72a6-4c8e-b6f1-c622fac0ef7e,OB:20,LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09,CLOUDID:577d9f7e-c8dc-403a-96e8-6237210dceee,C OID:ab9fe7398c47,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: c835ab158e284bddb1877ac900538f02-20220608 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 18680939; Wed, 08 Jun 2022 16:36:04 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Lee Jones , Benson Leung , "Guenter Roeck" , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 5/9] remoteproc: mediatek: Add chip dependent operations for SCP core 1 Date: Wed, 8 Jun 2022 16:35:49 +0800 Message-ID: <20220608083553.8697-6-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N The SCP rproc operations has chip dependent callbacks. Implement a version of these callbacks for MT8195 SCP core 1. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_scp.c | 65 ++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 91b4aefde4ac..731a8094c373 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -180,6 +180,16 @@ static void mt8192_scp_reset_deassert(struct mtk_scp *scp) writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR); } +static void mt8195_scp_dual_reset_assert(struct mtk_scp *scp) +{ + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_SET); +} + +static void mt8195_scp_dual_reset_deassert(struct mtk_scp *scp) +{ + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_CLR); +} + static void mt8183_scp_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; @@ -241,6 +251,24 @@ static void mt8195_scp_irq_handler(struct mtk_scp *scp) } } +static void mt8195_scp_dual_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host = readl(scp->reg_base + MT8195_SSHUB2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { + scp_ipi_handler(scp); + + /* + * SCP won't send another interrupt until we clear + * MT8195_SSHUB2APMCU_IPC_CLR. + */ + writel(MT8192_SCP_IPC_INT_BIT, + scp->reg_base + MT8195_SSHUB2APMCU_IPC_CLR); + } +} + static irqreturn_t scp_irq_handler(int irq, void *priv) { struct mtk_scp *scp = priv; @@ -474,6 +502,21 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) return 0; } +static int mt8195_scp_dual_before_load(struct mtk_scp *scp) +{ + u32 sec_ctrl; + + scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* hold SCP in reset while loading FW. */ + scp->data->scp_reset_assert(scp); + + /* enable MPU for all memory regions */ + writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + + return 0; +} + static int scp_load(struct rproc *rproc, const struct firmware *fw) { struct mtk_scp *scp = rproc->priv; @@ -646,6 +689,15 @@ static void mt8195_scp_stop(struct mtk_scp *scp) writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG); } +static void mt8195_scp_dual_stop(struct mtk_scp *scp) +{ + /* Power off CPU SRAM */ + scp_sram_power_off(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* Disable SCP watchdog */ + writel(0, scp->reg_base + MT8195_CORE1_WDT_CFG); +} + static int scp_stop(struct rproc *rproc) { struct mtk_scp *scp = (struct mtk_scp *)rproc->priv; @@ -1013,11 +1065,24 @@ static const struct mtk_scp_of_data mt8195_of_data = { .host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT, }; +static const struct mtk_scp_of_data mt8195_scp_dual_of_data = { + .scp_clk_get = mt8195_scp_clk_get, + .scp_before_load = mt8195_scp_dual_before_load, + .scp_irq_handler = mt8195_scp_dual_irq_handler, + .scp_reset_assert = mt8195_scp_dual_reset_assert, + .scp_reset_deassert = mt8195_scp_dual_reset_deassert, + .scp_stop = mt8195_scp_dual_stop, + .scp_da_to_va = mt8192_scp_da_to_va, + .host_to_scp_reg = MT8192_GIPC_IN_SET, + .host_to_scp_int_bit = MT8195_CORE1_HOST_IPC_INT_BIT, +}; + static const struct of_device_id mtk_scp_of_match[] = { { .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data }, { .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data }, { .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data }, { .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data }, + { .compatible = "mediatek,mt8195-scp-dual", .data = &mt8195_scp_dual_of_data }, {}, }; MODULE_DEVICE_TABLE(of, mtk_scp_of_match); From patchwork Wed Jun 8 08:35:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12873022 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4BE17B for ; Wed, 8 Jun 2022 08:36:16 +0000 (UTC) X-UUID: d6de6976b3ba4611902d7eb46160c50d-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:fdf95160-d3b8-466b-9dce-cb9891f2b2ea,OB:30,L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.5,REQID:fdf95160-d3b8-466b-9dce-cb9891f2b2ea,OB:30,LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09,CLOUDID:3f2515e5-2ba2-4dc1-b6c5-11feb6c769e0,C OID:ab9fe7398c47,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: d6de6976b3ba4611902d7eb46160c50d-20220608 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1726167700; Wed, 08 Jun 2022 16:36:04 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Lee Jones , Benson Leung , "Guenter Roeck" , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 6/9] remoteproc: mediatek: Add SCP core 1 SRAM offset Date: Wed, 8 Jun 2022 16:35:50 +0800 Message-ID: <20220608083553.8697-7-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Because SCP core 0 and core 1 both boot from address 0 and have the same viewpoint of memory, HW has a set of registers, "SRAM offset", to add offset to accessed address for SCP core 1 to solve this problem. The "SRAM offset" configuration is composed by specifying a range and an offset. The value of range is from the viewpoint of SCP core 1. When SCP core 1 accessing addresses in the configured range, SCP bus adds an offset to shift the destination on SCP SRAM. This shift is transparent to the software running on SCP core 1. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_scp.c | 42 ++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 731a8094c373..b8a4db581179 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -505,6 +505,27 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) static int mt8195_scp_dual_before_load(struct mtk_scp *scp) { u32 sec_ctrl; + struct device *dev = scp->dev; + struct device_node *main_np; + struct platform_device *main_pdev; + struct mtk_scp *scp_core0; + + /* Get sram start address from SCP core 0 */ + main_np = of_parse_phandle(dev->of_node, "mediatek,scp-core", 0); + if (!main_np) { + dev_warn(dev, "Invalid SCP main core phandle\n"); + return -EINVAL; + } + + main_pdev = of_find_device_by_node(main_np); + of_node_put(main_np); + + if (!main_pdev) { + dev_err(dev, "Cannot find SCP core 0 device\n"); + return -ENODEV; + } + scp_core0 = platform_get_drvdata(main_pdev); + put_device(&main_pdev->dev); scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); @@ -514,6 +535,27 @@ static int mt8195_scp_dual_before_load(struct mtk_scp *scp) /* enable MPU for all memory regions */ writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + /* The value of SRAM offset range is from the viewpoint of SCP core 1. + * This configuration adds an offset on SCP bus when SCP core 1 accesses SCP SRAM + * to solve the SCP core 0 and core 1 both fetch the 1st instruction from the same + * SRAM address. + * + * Because SCP core 0 and core 1 both boot from address 0, this must be configured + * before boot SCP core 1. + * + * Configure the range of SRAM addresses will be added offset. + */ + writel(0, scp->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW); + writel(scp->sram_size, scp->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_HIGH); + + /* configure the offset value */ + writel(scp->sram_phys - scp_core0->sram_phys, scp->reg_base + MT8195_L2TCM_OFFSET); + + /* enable adding sram offset when fetching instruction and data */ + sec_ctrl = readl(scp->reg_base + MT8195_SEC_CTRL); + sec_ctrl |= MT8195_CORE_OFFSET_ENABLE_I | MT8195_CORE_OFFSET_ENABLE_D; + writel(sec_ctrl, scp->reg_base + MT8195_SEC_CTRL); + return 0; } From patchwork Wed Jun 8 08:35:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12873037 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E913517F9 for ; Wed, 8 Jun 2022 08:37:26 +0000 (UTC) X-UUID: f5c1e9e9b2634d548c8b7d0de3b55509-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:1a601765-eea6-4ef0-9d17-adc775769923,OB:10,L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.5,REQID:1a601765-eea6-4ef0-9d17-adc775769923,OB:10,LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09,CLOUDID:b73a15e5-2ba2-4dc1-b6c5-11feb6c769e0,C OID:8f91e81df6c9,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: f5c1e9e9b2634d548c8b7d0de3b55509-20220608 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 265310191; Wed, 08 Jun 2022 16:37:21 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 8 Jun 2022 16:36:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:02 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Lee Jones , Benson Leung , Guenter Roeck , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 7/9] remoteproc: mediatek: Add SCP core 1 as a rproc subdevice Date: Wed, 8 Jun 2022 16:35:51 +0800 Message-ID: <20220608083553.8697-8-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Because the clock and SRAM power is controlled by SCP core 0, SCP core 1 has to be boot after SCP core 0. We use the rproc subdev to achieve this purpose. The watchdog timeout handler of SCP core 1 is added as part of the rproc subdevice. This allows SCP core 0 to handle watchdog timeout coming from SCP core 1. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_common.h | 9 +++ drivers/remoteproc/mtk_scp.c | 130 ++++++++++++++++++++++++++++++++ 2 files changed, 139 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index 5582f4207fbf..67b41866a100 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -99,6 +99,14 @@ struct scp_ipi_desc { void *priv; }; +struct scp_subdev_core { + struct rproc_subdev subdev; + struct mtk_scp *main_scp; + void (*scp_dual_wdt_timeout)(struct mtk_scp *scp, u32 scp_to_host); +}; + +#define to_subdev_core(d) container_of(d, struct scp_subdev_core, subdev) + struct mtk_scp; struct mtk_scp_of_data { @@ -144,6 +152,7 @@ struct mtk_scp { size_t dram_size; struct rproc_subdev *rpmsg_subdev; + struct rproc_subdev *dual_subdev; }; /** diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index b8a4db581179..d0e9e19e251f 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -244,6 +244,13 @@ static void mt8195_scp_irq_handler(struct mtk_scp *scp) } else { if (readl(scp->reg_base + MT8195_SYS_STATUS) & MT8195_CORE1_WDT) { writel(1, scp->reg_base + MT8195_CORE1_WDT_IRQ); + + if (scp->dual_subdev) { + struct scp_subdev_core *subdev_core; + + subdev_core = to_subdev_core(scp->dual_subdev); + subdev_core->scp_dual_wdt_timeout(scp, scp_to_host); + } } else { writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ); scp_wdt_handler(scp, scp_to_host); @@ -925,6 +932,118 @@ static void scp_remove_rpmsg_subdev(struct mtk_scp *scp) } } +static struct mtk_scp *scp_dual_get(struct mtk_scp *scp) +{ + struct device *dev = scp->dev; + struct device_node *np; + struct platform_device *dual_pdev; + + np = of_parse_phandle(dev->of_node, "mediatek,scp-core", 0); + dual_pdev = of_find_device_by_node(np); + of_node_put(np); + + if (!dual_pdev) { + dev_err(dev, "No scp-dual pdev\n"); + return NULL; + } + + return platform_get_drvdata(dual_pdev); +} + +static void scp_dual_put(struct mtk_scp *scp) +{ + put_device(scp->dev); +} + +static int scp_dual_rproc_start(struct rproc_subdev *subdev) +{ + struct scp_subdev_core *subdev_core = to_subdev_core(subdev); + struct mtk_scp *scp_dual; + + scp_dual = scp_dual_get(subdev_core->main_scp); + if (!scp_dual) + return -ENODEV; + + rproc_boot(scp_dual->rproc); + scp_dual_put(scp_dual); + + return 0; +} + +static void scp_dual_rproc_stop(struct rproc_subdev *subdev, bool crashed) +{ + struct scp_subdev_core *subdev_core = to_subdev_core(subdev); + struct mtk_scp *scp_dual; + + scp_dual = scp_dual_get(subdev_core->main_scp); + if (!scp_dual) + return; + + rproc_shutdown(scp_dual->rproc); + scp_dual_put(scp_dual); +} + +static void scp_dual_wdt_handler(struct mtk_scp *scp, u32 scp_to_host) +{ + struct mtk_scp *scp_dual; + + scp_dual = scp_dual_get(scp); + if (!scp_dual) + return; + + dev_err(scp_dual->dev, "SCP watchdog timeout! 0x%x\n", scp_to_host); + rproc_report_crash(scp_dual->rproc, RPROC_WATCHDOG); + scp_dual_put(scp_dual); +} + +static struct rproc_subdev *scp_dual_create_subdev(struct mtk_scp *scp) +{ + struct device *dev = scp->dev; + struct scp_subdev_core *subdev_core; + struct device_node *np; + + np = of_parse_phandle(dev->of_node, "mediatek,scp-core", 0); + if (!np) + return NULL; + + of_node_put(np); + + subdev_core = devm_kzalloc(dev, sizeof(*subdev_core), GFP_KERNEL); + if (!subdev_core) + return NULL; + + subdev_core->main_scp = scp; + subdev_core->scp_dual_wdt_timeout = scp_dual_wdt_handler; + subdev_core->subdev.start = scp_dual_rproc_start; + subdev_core->subdev.stop = scp_dual_rproc_stop; + + return &subdev_core->subdev; +} + +static void scp_dual_destroy_subdev(struct rproc_subdev *subdev) +{ + struct scp_subdev_core *subdev_core = to_subdev_core(subdev); + + devm_kfree(subdev_core->main_scp->dev, subdev_core); +} + +static void scp_add_dual_subdev(struct mtk_scp *scp) +{ + scp->dual_subdev = scp_dual_create_subdev(scp); + + if (scp->dual_subdev) + rproc_add_subdev(scp->rproc, scp->dual_subdev); +} + +static void scp_remove_dual_subdev(struct mtk_scp *scp) +{ + if (scp->dual_subdev) { + rproc_remove_subdev(scp->rproc, scp->dual_subdev); + scp_dual_destroy_subdev(scp->dual_subdev); + scp->dual_subdev = NULL; + } +} + static int scp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1014,6 +1133,9 @@ static int scp_probe(struct platform_device *pdev) scp_add_rpmsg_subdev(scp); + if (core_id == SCP_CORE_0) + scp_add_dual_subdev(scp); + ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), NULL, scp_irq_handler, IRQF_ONESHOT, pdev->name, scp); @@ -1023,6 +1145,12 @@ static int scp_probe(struct platform_device *pdev) goto remove_subdev; } + /* disable auto boot before register rproc. + * scp core 1 is booted as a subdevice of scp core 0. + */ + if (core_id == SCP_CORE_1) + rproc->auto_boot = false; + ret = rproc_add(rproc); if (ret) goto remove_subdev; @@ -1030,6 +1158,7 @@ static int scp_probe(struct platform_device *pdev) return 0; remove_subdev: + scp_remove_dual_subdev(scp); scp_remove_rpmsg_subdev(scp); scp_ipi_unregister(scp, SCP_IPI_INIT); release_dev_mem: @@ -1047,6 +1176,7 @@ static int scp_remove(struct platform_device *pdev) int i; rproc_del(scp->rproc); + scp_remove_dual_subdev(scp); scp_remove_rpmsg_subdev(scp); scp_ipi_unregister(scp, SCP_IPI_INIT); scp_unmap_memory_region(scp); From patchwork Wed Jun 8 08:35:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12873025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E066017FB for ; Wed, 8 Jun 2022 08:36:18 +0000 (UTC) X-UUID: 09d8dafa31464edba8697fe29c733233-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:238cc072-fe5f-4b93-8438-131e46df9dcf,OB:10,L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:95 X-CID-INFO: VERSION:1.1.5,REQID:238cc072-fe5f-4b93-8438-131e46df9dcf,OB:10,LOB :0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09,CLOUDID:3d2515e5-2ba2-4dc1-b6c5-11feb6c769e0,C OID:ab9fe7398c47,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: 09d8dafa31464edba8697fe29c733233-20220608 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 484781445; Wed, 08 Jun 2022 16:36:04 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Jun 2022 16:36:03 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:03 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Lee Jones , Benson Leung , "Guenter Roeck" , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 8/9] remoteproc: mediatek: Wait SCP core 1 probe done Date: Wed, 8 Jun 2022 16:35:52 +0800 Message-ID: <20220608083553.8697-9-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N SCP core 1 driver probing must finish before start loading SCP core 1 image. Add a simple flag checking mechanism when preparing SCP core 1 subdevice. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_common.h | 1 + drivers/remoteproc/mtk_scp.c | 38 ++++++++++++++++++++++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index 67b41866a100..89f9e53a5879 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -153,6 +153,7 @@ struct mtk_scp { struct rproc_subdev *rpmsg_subdev; struct rproc_subdev *dual_subdev; + int dual_probe_done; }; /** diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index d0e9e19e251f..b66bee4beb4d 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -937,6 +937,7 @@ static struct mtk_scp *scp_dual_get(struct mtk_scp *scp) struct device *dev = scp->dev; struct device_node *np; struct platform_device *dual_pdev; + struct mtk_scp *scp_dual; np = of_parse_phandle(dev->of_node, "mediatek,scp-core", 0); dual_pdev = of_find_device_by_node(np); @@ -947,7 +948,11 @@ static struct mtk_scp *scp_dual_get(struct mtk_scp *scp) return NULL; } - return platform_get_drvdata(dual_pdev); + scp_dual = platform_get_drvdata(dual_pdev); + if (!scp_dual) + put_device(&dual_pdev->dev); + + return scp_dual; } static void scp_dual_put(struct mtk_scp *scp) @@ -955,6 +960,33 @@ static void scp_dual_put(struct mtk_scp *scp) put_device(scp->dev); } +static int scp_dual_rproc_prepare(struct rproc_subdev *subdev) +{ + struct scp_subdev_core *subdev_core = to_subdev_core(subdev); + struct mtk_scp *scp = subdev_core->main_scp; + unsigned long timeout; + + timeout = jiffies + msecs_to_jiffies(100); + while (1) { + struct mtk_scp *scp_dual = scp_dual_get(scp); + + if (scp_dual && scp_dual->dual_probe_done) { + scp_dual_put(scp_dual); + break; + } + + if (scp_dual && !scp_dual->dual_probe_done) + scp_dual_put(scp_dual); + + if (time_after(jiffies, timeout)) { + dev_err(scp->dev, "scp-dual probe timeout\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + static int scp_dual_rproc_start(struct rproc_subdev *subdev) { struct scp_subdev_core *subdev_core = to_subdev_core(subdev); @@ -1014,6 +1046,7 @@ static struct rproc_subdev *scp_dual_create_subdev(struct mtk_scp *scp) subdev_core->main_scp = scp; subdev_core->scp_dual_wdt_timeout = scp_dual_wdt_handler; + subdev_core->subdev.prepare = scp_dual_rproc_prepare; subdev_core->subdev.start = scp_dual_rproc_start; subdev_core->subdev.stop = scp_dual_rproc_stop; @@ -1155,6 +1188,9 @@ static int scp_probe(struct platform_device *pdev) if (ret) goto remove_subdev; + if (core_id == SCP_CORE_1) + scp->dual_probe_done = 1; + return 0; remove_subdev: From patchwork Wed Jun 8 08:35:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12873026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2FDE7B for ; Wed, 8 Jun 2022 08:36:19 +0000 (UTC) X-UUID: 569b3735fca34859a0ff75c044fca289-20220608 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:4df39298-de03-4d3e-b3bb-0ce690f802b3,OB:50,L OB:20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.5,REQID:4df39298-de03-4d3e-b3bb-0ce690f802b3,OB:50,LOB :20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09,CLOUDID:907d9f7e-c8dc-403a-96e8-6237210dceee,C OID:ab9fe7398c47,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: 569b3735fca34859a0ff75c044fca289-20220608 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 586299730; Wed, 08 Jun 2022 16:36:04 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Jun 2022 16:36:03 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 8 Jun 2022 16:36:03 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Lee Jones , Benson Leung , "Guenter Roeck" , Sebastian Reichel , Daisuke Nojiri , Kees Cook , Tinghan Shen , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra CC: , , , , , , , Subject: [PATCH v2 9/9] mfd: cros_ec: Add SCP core 1 as a new CrOS EC MCU Date: Wed, 8 Jun 2022 16:35:53 +0800 Message-ID: <20220608083553.8697-10-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N MT8195 System Companion Processors(SCP) is a dual-core RISC-V MCU. Add a new cros feature id to represent the SCP 2nd core. The 1st core is referred to as 'core 0', and the 2nd core is referred to as 'core 1'. Signed-off-by: Tinghan Shen --- drivers/mfd/cros_ec_dev.c | 5 +++++ include/linux/platform_data/cros_ec_commands.h | 2 ++ include/linux/platform_data/cros_ec_proto.h | 1 + 3 files changed, 8 insertions(+) diff --git a/drivers/mfd/cros_ec_dev.c b/drivers/mfd/cros_ec_dev.c index 546feef851ab..7be2e23525e1 100644 --- a/drivers/mfd/cros_ec_dev.c +++ b/drivers/mfd/cros_ec_dev.c @@ -64,6 +64,11 @@ static const struct cros_feature_to_name cros_mcu_devices[] = { .name = CROS_EC_DEV_SCP_NAME, .desc = "System Control Processor", }, + { + .id = EC_FEATURE_SCP_C1, + .name = CROS_EC_DEV_SCP_C1_NAME, + .desc = "System Control Processor 2nd Core", + }, { .id = EC_FEATURE_TOUCHPAD, .name = CROS_EC_DEV_TP_NAME, diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux/platform_data/cros_ec_commands.h index c23554531961..1176cdc92d23 100644 --- a/include/linux/platform_data/cros_ec_commands.h +++ b/include/linux/platform_data/cros_ec_commands.h @@ -1296,6 +1296,8 @@ enum ec_feature_code { * mux. */ EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43, + /* The MCU is a System Companion Processor (SCP) 2nd Core. */ + EC_FEATURE_SCP_C1 = 45, }; #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) diff --git a/include/linux/platform_data/cros_ec_proto.h b/include/linux/platform_data/cros_ec_proto.h index df3c78c92ca2..12fc60f3c90d 100644 --- a/include/linux/platform_data/cros_ec_proto.h +++ b/include/linux/platform_data/cros_ec_proto.h @@ -19,6 +19,7 @@ #define CROS_EC_DEV_ISH_NAME "cros_ish" #define CROS_EC_DEV_PD_NAME "cros_pd" #define CROS_EC_DEV_SCP_NAME "cros_scp" +#define CROS_EC_DEV_SCP_C1_NAME "cros_scp_c1" #define CROS_EC_DEV_TP_NAME "cros_tp" /*