From patchwork Wed Jun 8 15:40:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12874160 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD764C433EF for ; Wed, 8 Jun 2022 15:40:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244453AbiFHPkc (ORCPT ); Wed, 8 Jun 2022 11:40:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244488AbiFHPkb (ORCPT ); Wed, 8 Jun 2022 11:40:31 -0400 Received: from andre.telenet-ops.be (andre.telenet-ops.be [IPv6:2a02:1800:120:4::f00:15]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F94A1CC605 for ; Wed, 8 Jun 2022 08:40:27 -0700 (PDT) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed30:243a:e14b:d107:1f56]) by andre.telenet-ops.be with bizsmtp id gfgR270021qF9lr01fgRkL; Wed, 08 Jun 2022 17:40:25 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1nyxnE-003E0B-Kx; Wed, 08 Jun 2022 17:40:24 +0200 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1nyxnE-008kJT-5P; Wed, 08 Jun 2022 17:40:24 +0200 From: Geert Uytterhoeven To: Magnus Damm , Yoshihiro Shimoda Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH 1/4] arm64: dts: renesas: r8a779f0: Add L3 cache controller Date: Wed, 8 Jun 2022 17:40:19 +0200 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Describe the cache configuration for the first Cortex-A55 CPU core on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index ad8c77edb12699d5..41aa23e557179af8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -23,6 +23,14 @@ a55_0: cpu@0 { reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA55_0>; + }; + + L3_CA55_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; }; }; From patchwork Wed Jun 8 15:40:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12874161 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52AF8C43334 for ; Wed, 8 Jun 2022 15:40:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244488AbiFHPkd (ORCPT ); Wed, 8 Jun 2022 11:40:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244140AbiFHPkb (ORCPT ); Wed, 8 Jun 2022 11:40:31 -0400 Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [IPv6:2a02:1800:120:4::f00:14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EFEA1CC5EA for ; Wed, 8 Jun 2022 08:40:27 -0700 (PDT) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed30:243a:e14b:d107:1f56]) by xavier.telenet-ops.be with bizsmtp id gfgR270071qF9lr01fgRmT; Wed, 08 Jun 2022 17:40:25 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1nyxnE-003E0C-Nu; Wed, 08 Jun 2022 17:40:24 +0200 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1nyxnE-008kJa-60; Wed, 08 Jun 2022 17:40:24 +0200 From: Geert Uytterhoeven To: Magnus Damm , Yoshihiro Shimoda Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH 2/4] arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores Date: Wed, 8 Jun 2022 17:40:20 +0200 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Complete the description of the Cortex-A55 CPU cores and L3 cache controllers on the Renesas R-Car S4-8 (R8A779F0) SoC, including CPU topology and PSCI support for enabling CPU cores. R-Car S4-8 has 8 Cortex-A55 cores, grouped in 4 clusters. Based on patches in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 138 +++++++++++++++++++++- 1 file changed, 133 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 41aa23e557179af8..197e452c8623dffb 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -18,12 +18,114 @@ cpus { #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a55_0>; + }; + core1 { + cpu = <&a55_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&a55_2>; + }; + core1 { + cpu = <&a55_3>; + }; + }; + + cluster2 { + core0 { + cpu = <&a55_4>; + }; + core1 { + cpu = <&a55_5>; + }; + }; + + cluster3 { + core0 { + cpu = <&a55_6>; + }; + core1 { + cpu = <&a55_7>; + }; + }; + }; + a55_0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; next-level-cache = <&L3_CA55_0>; + enable-method = "psci"; + }; + + a55_1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; + next-level-cache = <&L3_CA55_0>; + enable-method = "psci"; + }; + + a55_2: cpu@10000 { + compatible = "arm,cortex-a55"; + reg = <0x10000>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; + next-level-cache = <&L3_CA55_1>; + enable-method = "psci"; + }; + + a55_3: cpu@10100 { + compatible = "arm,cortex-a55"; + reg = <0x10100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; + next-level-cache = <&L3_CA55_1>; + enable-method = "psci"; + }; + + a55_4: cpu@20000 { + compatible = "arm,cortex-a55"; + reg = <0x20000>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; + next-level-cache = <&L3_CA55_2>; + enable-method = "psci"; + }; + + a55_5: cpu@20100 { + compatible = "arm,cortex-a55"; + reg = <0x20100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; + next-level-cache = <&L3_CA55_2>; + enable-method = "psci"; + }; + + a55_6: cpu@30000 { + compatible = "arm,cortex-a55"; + reg = <0x30000>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; + next-level-cache = <&L3_CA55_3>; + enable-method = "psci"; + }; + + a55_7: cpu@30100 { + compatible = "arm,cortex-a55"; + reg = <0x30100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; + next-level-cache = <&L3_CA55_3>; + enable-method = "psci"; }; L3_CA55_0: cache-controller-0 { @@ -32,6 +134,27 @@ L3_CA55_0: cache-controller-0 { cache-unified; cache-level = <3>; }; + + L3_CA55_1: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E0D1>; + cache-unified; + cache-level = <3>; + }; + + L3_CA55_2: cache-controller-2 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E1D0>; + cache-unified; + cache-level = <3>; + }; + + L3_CA55_3: cache-controller-3 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E1D1>; + cache-unified; + cache-level = <3>; + }; }; extal_clk: extal { @@ -53,6 +176,11 @@ pmu_a55 { interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; @@ -421,7 +549,7 @@ gic: interrupt-controller@f1000000 { reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; }; prr: chipid@fff00044 { @@ -432,9 +560,9 @@ prr: chipid@fff00044 { timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; }; From patchwork Wed Jun 8 15:40:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12874163 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 612CDCCA481 for ; Wed, 8 Jun 2022 15:40:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244140AbiFHPkf (ORCPT ); Wed, 8 Jun 2022 11:40:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244517AbiFHPkc (ORCPT ); Wed, 8 Jun 2022 11:40:32 -0400 Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [IPv6:2a02:1800:120:4::f00:13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E1FA1CC5E6 for ; Wed, 8 Jun 2022 08:40:26 -0700 (PDT) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed30:243a:e14b:d107:1f56]) by baptiste.telenet-ops.be with bizsmtp id gfgR270041qF9lr01fgRRD; Wed, 08 Jun 2022 17:40:25 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1nyxnE-003E0D-Jf; Wed, 08 Jun 2022 17:40:24 +0200 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1nyxnE-008kJh-6g; Wed, 08 Jun 2022 17:40:24 +0200 From: Geert Uytterhoeven To: Magnus Damm , Yoshihiro Shimoda Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tho Vu , Geert Uytterhoeven Subject: [PATCH 3/4] arm64: dts: renesas: r8a779f0: Add CPUIdle support Date: Wed, 8 Jun 2022 17:40:21 +0200 Message-Id: <5310792ce4c06515a5373ff44ceb9b925f007489.1654701480.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Tho Vu Support CPUIdle for ARM Cortex-A55 on R-Car S4-8. Signed-off-by: Tho Vu Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 197e452c8623dffb..bcee482803e888cc 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -63,6 +63,7 @@ a55_0: cpu@0 { power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; next-level-cache = <&L3_CA55_0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_1: cpu@100 { @@ -72,6 +73,7 @@ a55_1: cpu@100 { power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; next-level-cache = <&L3_CA55_0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_2: cpu@10000 { @@ -81,6 +83,7 @@ a55_2: cpu@10000 { power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; next-level-cache = <&L3_CA55_1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_3: cpu@10100 { @@ -90,6 +93,7 @@ a55_3: cpu@10100 { power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; next-level-cache = <&L3_CA55_1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_4: cpu@20000 { @@ -99,6 +103,7 @@ a55_4: cpu@20000 { power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; next-level-cache = <&L3_CA55_2>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_5: cpu@20100 { @@ -108,6 +113,7 @@ a55_5: cpu@20100 { power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; next-level-cache = <&L3_CA55_2>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_6: cpu@30000 { @@ -117,6 +123,7 @@ a55_6: cpu@30000 { power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; next-level-cache = <&L3_CA55_3>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a55_7: cpu@30100 { @@ -126,6 +133,7 @@ a55_7: cpu@30100 { power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; next-level-cache = <&L3_CA55_3>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; L3_CA55_0: cache-controller-0 { @@ -155,6 +163,19 @@ L3_CA55_3: cache-controller-3 { cache-unified; cache-level = <3>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + }; }; extal_clk: extal { From patchwork Wed Jun 8 15:40:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12874164 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A94E7C433EF for ; Wed, 8 Jun 2022 15:40:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244468AbiFHPke (ORCPT ); Wed, 8 Jun 2022 11:40:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244521AbiFHPkc (ORCPT ); Wed, 8 Jun 2022 11:40:32 -0400 Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [IPv6:2a02:1800:120:4::f00:13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F58F1CC5ED for ; Wed, 8 Jun 2022 08:40:26 -0700 (PDT) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed30:243a:e14b:d107:1f56]) by baptiste.telenet-ops.be with bizsmtp id gfgR2700G1qF9lr01fgRRE; Wed, 08 Jun 2022 17:40:25 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1nyxnE-003E0E-OF; Wed, 08 Jun 2022 17:40:24 +0200 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1nyxnE-008kJo-7J; Wed, 08 Jun 2022 17:40:24 +0200 From: Geert Uytterhoeven To: Magnus Damm , Yoshihiro Shimoda Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH 4/4] arm64: dts: renesas: r8a779f0: Add CPU core clocks Date: Wed, 8 Jun 2022 17:40:22 +0200 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Describe the clocks for the eight Cortex-A55 CPU cores. CA55 Sub-System 0 (first 2 clusters / CPU cores 0-3) is clocked by Z0φ. CA55 Sub-System 1 (last 2 clusters / CPU cores 4-7) is clocked by Z1φ. For now no operating points are defined. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index bcee482803e888cc..9ec23b46891f8d96 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -64,6 +64,7 @@ a55_0: cpu@0 { next-level-cache = <&L3_CA55_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; }; a55_1: cpu@100 { @@ -74,6 +75,7 @@ a55_1: cpu@100 { next-level-cache = <&L3_CA55_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; }; a55_2: cpu@10000 { @@ -84,6 +86,7 @@ a55_2: cpu@10000 { next-level-cache = <&L3_CA55_1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; }; a55_3: cpu@10100 { @@ -94,6 +97,7 @@ a55_3: cpu@10100 { next-level-cache = <&L3_CA55_1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; }; a55_4: cpu@20000 { @@ -104,6 +108,7 @@ a55_4: cpu@20000 { next-level-cache = <&L3_CA55_2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; }; a55_5: cpu@20100 { @@ -114,6 +119,7 @@ a55_5: cpu@20100 { next-level-cache = <&L3_CA55_2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; }; a55_6: cpu@30000 { @@ -124,6 +130,7 @@ a55_6: cpu@30000 { next-level-cache = <&L3_CA55_3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; }; a55_7: cpu@30100 { @@ -134,6 +141,7 @@ a55_7: cpu@30100 { next-level-cache = <&L3_CA55_3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; }; L3_CA55_0: cache-controller-0 {