From patchwork Wed Jun 8 16:14:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12874225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3399C433EF for ; Wed, 8 Jun 2022 16:17:14 +0000 (UTC) Received: from localhost ([::1]:52032 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyyMr-0001RM-FK for qemu-devel@archiver.kernel.org; Wed, 08 Jun 2022 12:17:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56174) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyyL8-0007AN-VM for qemu-devel@nongnu.org; Wed, 08 Jun 2022 12:15:26 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:43571) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyyKz-0002Xr-Kw for qemu-devel@nongnu.org; Wed, 08 Jun 2022 12:15:26 -0400 Received: by mail-pg1-x530.google.com with SMTP id s135so3703331pgs.10 for ; Wed, 08 Jun 2022 09:15:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MUlVMz0mT/KXtuKDaS4V/GZQ3FzUmtpDbT4gk28/bsA=; b=n8kNT8py33pCaHgsX0WGfc/MUwRGnboK+iMmEn2UiwEiV3U6MxnWPkn42Xx90qQyrz FEvkDlahVEgcpc9aU/UU38u+UPJodzB/Xxt64DpC6UhRzzZA5i4rLqTClkq28wPSSWPu CxJjoJS78krvRK86gVjlsqQaJwx8PBraaFvT1/T1w2+OWdfI2NoPebLLdcaKHytcKZdU kthycozepUh3PWxURVbghEaEeF95DPzCHbdCA7evbrPhCKCk7NWIGC/omlDSnD9qPgHU YiFmS7wqcu3AAH3uv08FKeLwDBKf36V+8irfydYSWetF3K9MSOZ3+D3euWq+GJP8yWxv mZQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MUlVMz0mT/KXtuKDaS4V/GZQ3FzUmtpDbT4gk28/bsA=; b=WeqyyY9A8TlF11+G3ji8KhPs26jCnDz4oU15UyVKv80/DcU/bua+vs8TixVoLUC0GK NLiQ0axSHvoK1WUvFcd7vRPmC2XqtluEg5f/wrvrdXoNoofd09gAcCw3nPj6PgMN5J3d 6U4xQCmET7zFF6YTghfq+uCSeYw0YQUfhnmWZ1HEGHQ/fTQH9ZyJaYiBX6Hbreh4bFXB VMAMVNw7g53HhVkj3uXUogE9Z7VdYGUP6HKX7rHRtONUnO3tyn79etUagAUe1ozsjc5I /rN9WP4FBnAU3Ff9ybZo+zNhl5Fx94mY+SeOmeCJ62U67f+ZeeEpiUxr7kNrUUM/b5UL rfEQ== X-Gm-Message-State: AOAM532i4Onz7PSbkj5J8wsr+dMUUGCfnnZJ1U+Z5Cyu3aCMBleS7lEV Cm9NHrEAbiXwM4YqBq6IU8jmtg== X-Google-Smtp-Source: ABdhPJw/yYvA/1GsUPZiQF6JRaSqlp2BuP3YmQH5ejs9jUOyZmgL1HrkXo5qg1jDi924RF5OONwSdw== X-Received: by 2002:a63:2a89:0:b0:3fa:cc62:e00f with SMTP id q131-20020a632a89000000b003facc62e00fmr30369832pgq.364.1654704916206; Wed, 08 Jun 2022 09:15:16 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([122.162.103.97]) by smtp.gmail.com with ESMTPSA id k189-20020a6384c6000000b003fcde69fea5sm13374843pgd.81.2022.06.08.09.15.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 09:15:15 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Frank Chang , Alistair Francis , Atish Patra Subject: [PATCH v4 1/4] target/riscv: Don't force update priv spec version to latest Date: Wed, 8 Jun 2022 21:44:02 +0530 Message-Id: <20220608161405.729964-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220608161405.729964-1-apatel@ventanamicro.com> References: <20220608161405.729964-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=apatel@ventanamicro.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The riscv_cpu_realize() sets priv spec verion to v1.12 when it is when "env->priv_ver == 0" (i.e. default v1.10) because the enum value of priv spec v1.10 is zero. Due to above issue, the sifive_u machine will see priv spec v1.12 instead of priv spec v1.10. To fix this issue, we set latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Atish Patra Reviewed-by: Bin Meng --- target/riscv/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0497af45cc..9f9c27a3f5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -169,6 +169,8 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } static void rv64_sifive_u_cpu_init(Object *obj) @@ -204,6 +206,8 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } static void rv32_sifive_u_cpu_init(Object *obj) @@ -509,7 +513,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); CPUClass *cc = CPU_CLASS(mcc); - int priv_version = 0; + int priv_version = -1; Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); @@ -533,10 +537,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (priv_version) { + if (priv_version >= PRIV_VERSION_1_10_0) { set_priv_version(env, priv_version); - } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_12_0); } if (cpu->cfg.mmu) { From patchwork Wed Jun 8 16:14:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12874226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7BE7C43334 for ; Wed, 8 Jun 2022 16:17:23 +0000 (UTC) Received: from localhost ([::1]:52772 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyyN0-0001xa-Q1 for qemu-devel@archiver.kernel.org; Wed, 08 Jun 2022 12:17:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56140) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyyL5-00073q-JG for qemu-devel@nongnu.org; Wed, 08 Jun 2022 12:15:23 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:37571) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyyL3-0002cD-Qv for qemu-devel@nongnu.org; Wed, 08 Jun 2022 12:15:23 -0400 Received: by mail-pj1-x102d.google.com with SMTP id 3-20020a17090a174300b001e426a02ac5so21080989pjm.2 for ; Wed, 08 Jun 2022 09:15:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w6MrD6bzN19Je1Xt3JmYim4uIDMcK9Yyrc6qTYo17mM=; b=chhzcMCF/4yPlQGichb2GHoVHQsKJh57/D9/2a1yNnJnuMDuQTRXDGyNtcss+9oemx TL+2SQUwPGiOshVrz5T4vu/H7v/RDduiFJmyl+W9cMT28IDg3ZgN+zCiLHDn+g7zuUHi l+V4cyNZH7/LyRroznvvvlMhhYk/18K7U1pwOLocy8QBjk1lcWWvItm48WKJAiEe7dTx cDX+sxpQl9+jbzG0uqjXfrQd1LlMAYm6+Fiv9MrI3HxuvGg0YB+r+gjYJUVM/uspAUKn M6srOURqvsZR3csHFS/pv5GmnFlR/6J6mDFmv/myoQ2/LvLCPYYbrFGirbKw81znCTby fIgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w6MrD6bzN19Je1Xt3JmYim4uIDMcK9Yyrc6qTYo17mM=; b=1QO82ZSLWzE/r9dD1UOWA47zh3olCe9XHxlrQJfbAucc44C/LfXRZn3lGR8OXN4GX/ hb4Spl8F129VcKaT7X3gp9fwYaqBQTrCokH43NkwakhfGJauy2O1dCiJ7TQIYyPgjQRV UMuA2U00L4nhQcWgBdZ3dY/wrvFvXjmIKQEq4XzNk2i4shz09LJx4MUQVKnvPWFqdjb7 Ej7EXS3KBc5bCojCGEnl3JIrJh8WmpZHu8vR2qQlIOpSpco/wfugIwABK1Y2VVIKef5Q 9FMaznLahF7HCGP3wkC4ipYXVPMv8AMzpkFWjzaWbt7cnE/0iTjbSiQoM6PPZYJqVBVy 7eQg== X-Gm-Message-State: AOAM532JlIVyMgKN5FKBLzm+5vp8sSr6+/hKxPk6v+rQZfBPQUF5/4VW eopnfrYsoDwENLIEIHwudDuERg== X-Google-Smtp-Source: ABdhPJxqwQCxf3fI8IygActJWkkR0dX1eYfxLcAZ8yR0Oba+S+7XXvejuzL8uzTWtcppL36dYGJfcg== X-Received: by 2002:a17:90b:1101:b0:1e8:5df5:b2ac with SMTP id gi1-20020a17090b110100b001e85df5b2acmr24183728pjb.239.1654704920478; Wed, 08 Jun 2022 09:15:20 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([122.162.103.97]) by smtp.gmail.com with ESMTPSA id k189-20020a6384c6000000b003fcde69fea5sm13374843pgd.81.2022.06.08.09.15.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 09:15:19 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Frank Chang , Alistair Francis Subject: [PATCH v4 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher Date: Wed, 8 Jun 2022 21:44:03 +0530 Message-Id: <20220608161405.729964-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220608161405.729964-1-apatel@ventanamicro.com> References: <20220608161405.729964-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.") Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4d04b20d06..4a55c6a709 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -159,6 +159,9 @@ #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 +/* Machine Counter Setup */ +#define CSR_MCOUNTINHIBIT 0x320 + /* 32-bit only */ #define CSR_MSTATUSH 0x310 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6dbe9b541f..409a209f14 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3391,6 +3391,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, + [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_zero, write_ignore, + .min_priv_ver = PRIV_VERSION_1_11_0 }, [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, From patchwork Wed Jun 8 16:14:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12874232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F3B1C43334 for ; Wed, 8 Jun 2022 16:20:56 +0000 (UTC) Received: from localhost ([::1]:59592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyyQR-0007MO-Cp for qemu-devel@archiver.kernel.org; Wed, 08 Jun 2022 12:20:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56178) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyyL9-0007Bo-M1 for qemu-devel@nongnu.org; Wed, 08 Jun 2022 12:15:27 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:34778) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyyL7-0002Xq-0Q for qemu-devel@nongnu.org; Wed, 08 Jun 2022 12:15:27 -0400 Received: by mail-pg1-x534.google.com with SMTP id g186so10458535pgc.1 for ; Wed, 08 Jun 2022 09:15:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZfVat5pYbsbGH3iRVcQ91uwUKLQ2wTtVkLROAMRLuPE=; b=IxfTl27/BARccTuXwqT4lIVEKGzVMMf9vOgPCea11PArNkdGt0s9CjJMH6Wyb4fk+7 DwiM7gNNaC/d/evtJuDlKISXtqAEBpfD+GWnpdnl9DH8m66BuF5tR84QoeNju7x7K7Xm EQcNc4gDNnhkpGt/SUHgpnB1sdvCuBpTrd5X7XvEKi7TdTHY3XbDll+ZCwK2gqRBrSN7 Pkk/pMLvXoJNda9FVsTNbm+w+ewns/fFI5UKKP/yrYcQDXfXDq3iOLdrKEwWRpVS6fNp wdgy6eRDoqi7q1O30TpRTFXFYFVjPr6ixIhnLRH43DBjhvzQuFJRkIZ0XncMGyVq53/b ovog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZfVat5pYbsbGH3iRVcQ91uwUKLQ2wTtVkLROAMRLuPE=; b=HnmNElVlvBA5OzC7aaPppnHxARL+KaCkYXBpXZigOQV6gUfo+/DtNYsJUIHQr3e0rA iK9ggap8JsfNtpqD6BGFhkgiRX7Ef9idY0MunkZ/MtHsb9tQExBAK+SFoJvFg8GFRZDo nAl5CQGSwchS69NieiR2YP5WfUMYUyb1UqrOVDMgJUzOqRTtbLgcCIcXF1yGwfXajBrH hv/u7JjUT8KJfFDMbYJxx5u1C5JvwoZMqLo35YGzQgA+f2STwuqzQB2QWLZG8hw9fLWu G/GZOZ8opGjytvqnYUOtam1+OBr69Emk0LRn8XVDl9Js6D1qlmqbR17fdH8bhFcpes9t uz5A== X-Gm-Message-State: AOAM531sa4gitICZdLkkztr8Xuo/nLEYDcSc/BrTsC1JL/HruEUj7tn2 uG/WyKwh0ci1t3LIdtvHiIBGApg9gT5hFQ== X-Google-Smtp-Source: ABdhPJxWfXQ2AyNSoWqbKLXfJEj626jhSeklu9KoNehFVuhkCVedVI5k6Mux++kL9gqpjwQf8wc5LQ== X-Received: by 2002:a63:35ce:0:b0:3fd:fb5a:a1c3 with SMTP id c197-20020a6335ce000000b003fdfb5aa1c3mr8809710pga.85.1654704924171; Wed, 08 Jun 2022 09:15:24 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([122.162.103.97]) by smtp.gmail.com with ESMTPSA id k189-20020a6384c6000000b003fcde69fea5sm13374843pgd.81.2022.06.08.09.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 09:15:23 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v4 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() Date: Wed, 8 Jun 2022 21:44:04 +0530 Message-Id: <20220608161405.729964-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220608161405.729964-1-apatel@ventanamicro.com> References: <20220608161405.729964-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=apatel@ventanamicro.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel --- target/riscv/cpu.h | 3 + target/riscv/cpu_helper.c | 231 +++++++++++++++++++++++++++++++++++++- target/riscv/instmap.h | 43 +++++++ 3 files changed, 271 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 194a58d760..11726e9031 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -271,6 +271,9 @@ struct CPUArchState { /* Signals whether the current exception occurred with two-stage address translation active. */ bool two_stage_lookup; + /* Signals whether the current exception occurred while doing two-stage + address translation for the VS-stage page table walk. */ + bool two_stage_indirect_lookup; target_ulong scounteren; target_ulong mcounteren; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 16c6045459..62a6762617 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,6 +22,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/exec-all.h" +#include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" @@ -1055,7 +1056,8 @@ restart: static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type, bool pmp_violation, - bool first_stage, bool two_stage) + bool first_stage, bool two_stage, + bool two_stage_indirect) { CPUState *cs = env_cpu(env); int page_fault_exceptions, vm; @@ -1105,6 +1107,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, } env->badaddr = address; env->two_stage_lookup = two_stage; + env->two_stage_indirect_lookup = two_stage_indirect; } hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) @@ -1150,6 +1153,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, env->badaddr = addr; env->two_stage_lookup = riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_indirect_lookup = false; cpu_loop_exit_restore(cs, retaddr); } @@ -1175,6 +1179,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->badaddr = addr; env->two_stage_lookup = riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_indirect_lookup = false; cpu_loop_exit_restore(cs, retaddr); } @@ -1190,6 +1195,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool pmp_violation = false; bool first_stage_error = true; bool two_stage_lookup = false; + bool two_stage_indirect_error = false; int ret = TRANSLATE_FAIL; int mode = mmu_idx; /* default TLB page size */ @@ -1227,6 +1233,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, */ if (ret == TRANSLATE_G_STAGE_FAIL) { first_stage_error = false; + two_stage_indirect_error = true; access_type = MMU_DATA_LOAD; } @@ -1310,12 +1317,207 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error, riscv_cpu_virt_enabled(env) || - riscv_cpu_two_stage_lookup(mmu_idx)); + riscv_cpu_two_stage_lookup(mmu_idx), + two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); } return true; } + +static target_ulong riscv_transformed_insn(CPURISCVState *env, + target_ulong insn) +{ + bool xinsn_has_addr_offset = false; + target_ulong xinsn = 0; + + /* + * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to + * be uncompressed. The Quadrant 1 of RVC instruction space need + * not be transformed because these instructions won't generate + * any load/store trap. + */ + + if ((insn & 0x3) != 0x3) { + /* Transform 16bit instruction into 32bit instruction */ + switch (GET_C_OP(insn)) { + case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLD_LQ: + if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ + xinsn = OPC_RISC_FLD; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_I_IMM(xinsn, GET_C_LD_IMM(insn)); + xinsn_has_addr_offset = true; + } + break; + case OPC_RISC_C_FUNC_LW: /* C.LW */ + xinsn = OPC_RISC_LW; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_I_IMM(xinsn, GET_C_LW_IMM(insn)); + xinsn_has_addr_offset = true; + break; + case OPC_RISC_C_FUNC_FLW_LD: + if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ + xinsn = OPC_RISC_FLW; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_I_IMM(xinsn, GET_C_LW_IMM(insn)); + xinsn_has_addr_offset = true; + } else { /* C.LD (RV64/RV128) */ + xinsn = OPC_RISC_LD; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_I_IMM(xinsn, GET_C_LD_IMM(insn)); + xinsn_has_addr_offset = true; + } + break; + case OPC_RISC_C_FUNC_FSD_SQ: + if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ + xinsn = OPC_RISC_FSD; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_S_IMM(xinsn, GET_C_SD_IMM(insn)); + xinsn_has_addr_offset = true; + } + break; + case OPC_RISC_C_FUNC_SW: /* C.SW */ + xinsn = OPC_RISC_SW; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_S_IMM(xinsn, GET_C_SW_IMM(insn)); + xinsn_has_addr_offset = true; + break; + case OPC_RISC_C_FUNC_FSW_SD: + if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ + xinsn = OPC_RISC_FSW; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_S_IMM(xinsn, GET_C_SW_IMM(insn)); + xinsn_has_addr_offset = true; + } else { /* C.SD (RV64/RV128) */ + xinsn = OPC_RISC_SD; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_S_IMM(xinsn, GET_C_SD_IMM(insn)); + xinsn_has_addr_offset = true; + } + break; + default: + break; + } + break; + case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLDSP_LQSP: + if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ + xinsn = OPC_RISC_FLD; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_I_IMM(xinsn, GET_C_LDSP_IMM(insn)); + xinsn_has_addr_offset = true; + } + break; + case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ + xinsn = OPC_RISC_LW; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_I_IMM(xinsn, GET_C_LWSP_IMM(insn)); + xinsn_has_addr_offset = true; + break; + case OPC_RISC_C_FUNC_FLWSP_LDSP: + if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ + xinsn = OPC_RISC_FLW; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_I_IMM(xinsn, GET_C_LWSP_IMM(insn)); + xinsn_has_addr_offset = true; + } else { /* C.LDSP (RV64/RV128) */ + xinsn = OPC_RISC_LD; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_I_IMM(xinsn, GET_C_LDSP_IMM(insn)); + xinsn_has_addr_offset = true; + } + break; + case OPC_RISC_C_FUNC_FSDSP_SQSP: + if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ + xinsn = OPC_RISC_FSD; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_S_IMM(xinsn, GET_C_SDSP_IMM(insn)); + xinsn_has_addr_offset = true; + } + break; + case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ + xinsn = OPC_RISC_SW; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_S_IMM(xinsn, GET_C_SWSP_IMM(insn)); + xinsn_has_addr_offset = true; + break; + case 7: + if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ + xinsn = OPC_RISC_FSW; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_S_IMM(xinsn, GET_C_SWSP_IMM(insn)); + xinsn_has_addr_offset = true; + } else { /* C.SDSP (RV64/RV128) */ + xinsn = OPC_RISC_SD; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_S_IMM(xinsn, GET_C_SDSP_IMM(insn)); + xinsn_has_addr_offset = true; + } + break; + default: + break; + } + break; + default: + break; + } + + /* + * Clear Bit1 of transformed instruction to indicate that + * original insruction was a 16bit instruction + */ + xinsn &= ~((target_ulong)0x2); + } else { + /* No need to transform 32bit (or wider) instructions */ + xinsn = insn; + + /* Check for instructions which need address offset */ + switch (MASK_OP_MAJOR(insn)) { + case OPC_RISC_LOAD: + case OPC_RISC_STORE: + case OPC_RISC_ATOMIC: + case OPC_RISC_FP_LOAD: + case OPC_RISC_FP_STORE: + xinsn_has_addr_offset = true; + break; + case OPC_RISC_SYSTEM: + if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { + xinsn_has_addr_offset = true; + } + break; + } + } + + if (xinsn_has_addr_offset) { + /* + * The "Addr. Offset" field in transformed instruction is non-zero + * only for misaligned load/store traps which are very unlikely on + * QEMU so for now always set "Addr. Offset" to zero. + */ + xinsn = SET_RS1(xinsn, 0); + } + + return xinsn; +} #endif /* !CONFIG_USER_ONLY */ /* @@ -1340,6 +1542,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; uint64_t deleg = async ? env->mideleg : env->medeleg; target_ulong tval = 0; + target_ulong tinst = 0; target_ulong htval = 0; target_ulong mtval2 = 0; @@ -1355,18 +1558,31 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { - case RISCV_EXCP_INST_GUEST_PAGE_FAULT: case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_ADDR_MIS: - case RISCV_EXCP_INST_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: case RISCV_EXCP_STORE_AMO_ADDR_MIS: case RISCV_EXCP_LOAD_ACCESS_FAULT: case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: + write_gva = env->two_stage_lookup; + tval = env->badaddr; + if (env->two_stage_indirect_lookup) { + /* + * special pseudoinstruction for G-stage fault taken while + * doing VS-stage page table walk. + */ + tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; + } else { + /* transformed instruction for all other load/store faults */ + tinst = riscv_transformed_insn(env, env->bins); + } + break; + case RISCV_EXCP_INST_GUEST_PAGE_FAULT: + case RISCV_EXCP_INST_ADDR_MIS: + case RISCV_EXCP_INST_ACCESS_FAULT: + case RISCV_EXCP_INST_PAGE_FAULT: write_gva = env->two_stage_lookup; tval = env->badaddr; break; @@ -1448,6 +1664,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->sepc = env->pc; env->stval = tval; env->htval = htval; + env->htinst = tinst; env->pc = (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S); @@ -1478,6 +1695,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mepc = env->pc; env->mtval = tval; env->mtval2 = mtval2; + env->mtinst = tinst; env->pc = (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); @@ -1490,6 +1708,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) */ env->two_stage_lookup = false; + env->two_stage_indirect_lookup = false; #endif cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ } diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h index 40b6d2b64d..f564a69d90 100644 --- a/target/riscv/instmap.h +++ b/target/riscv/instmap.h @@ -184,6 +184,8 @@ enum { OPC_RISC_CSRRWI = OPC_RISC_SYSTEM | (0x5 << 12), OPC_RISC_CSRRSI = OPC_RISC_SYSTEM | (0x6 << 12), OPC_RISC_CSRRCI = OPC_RISC_SYSTEM | (0x7 << 12), + + OPC_RISC_HLVHSV = OPC_RISC_SYSTEM | (0x4 << 12), }; #define MASK_OP_FP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) @@ -316,6 +318,12 @@ enum { #define GET_RS2(inst) extract32(inst, 20, 5) #define GET_RD(inst) extract32(inst, 7, 5) #define GET_IMM(inst) sextract64(inst, 20, 12) +#define SET_RS1(inst, val) deposit32(inst, 15, 5, val) +#define SET_RS2(inst, val) deposit32(inst, 20, 5, val) +#define SET_RD(inst, val) deposit32(inst, 7, 5, val) +#define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val) +#define SET_S_IMM(inst, val) \ + deposit32(deposit32(inst, 7, 5, val), 25, 7, (val) >> 5) /* RVC decoding macros */ #define GET_C_IMM(inst) (extract32(inst, 2, 5) \ @@ -346,6 +354,8 @@ enum { | (extract32(inst, 5, 1) << 6)) #define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \ | (extract16(inst, 5, 2) << 6)) +#define GET_C_SW_IMM(inst) GET_C_LW_IMM(inst) +#define GET_C_SD_IMM(inst) GET_C_LD_IMM(inst) #define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \ | (extract32(inst, 11, 1) << 4) \ | (extract32(inst, 2, 1) << 5) \ @@ -366,4 +376,37 @@ enum { #define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3)) #define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3)) +#define GET_C_FUNC(inst) extract32(inst, 13, 3) +#define GET_C_OP(inst) extract32(inst, 0, 2) + +enum { + /* RVC Quadrants */ + OPC_RISC_C_OP_QUAD0 = 0x0, + OPC_RISC_C_OP_QUAD1 = 0x1, + OPC_RISC_C_OP_QUAD2 = 0x2 +}; + +enum { + /* RVC Quadrant 0 */ + OPC_RISC_C_FUNC_ADDI4SPN = 0x0, + OPC_RISC_C_FUNC_FLD_LQ = 0x1, + OPC_RISC_C_FUNC_LW = 0x2, + OPC_RISC_C_FUNC_FLW_LD = 0x3, + OPC_RISC_C_FUNC_FSD_SQ = 0x5, + OPC_RISC_C_FUNC_SW = 0x6, + OPC_RISC_C_FUNC_FSW_SD = 0x7 +}; + +enum { + /* RVC Quadrant 2 */ + OPC_RISC_C_FUNC_SLLI_SLLI64 = 0x0, + OPC_RISC_C_FUNC_FLDSP_LQSP = 0x1, + OPC_RISC_C_FUNC_LWSP = 0x2, + OPC_RISC_C_FUNC_FLWSP_LDSP = 0x3, + OPC_RISC_C_FUNC_JR_MV_EBREAK_JALR_ADD = 0x4, + OPC_RISC_C_FUNC_FSDSP_SQSP = 0x5, + OPC_RISC_C_FUNC_SWSP = 0x6, + OPC_RISC_C_FUNC_FSWSP_SDSP = 0x7 +}; + #endif From patchwork Wed Jun 8 16:14:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12874233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5CF6C43334 for ; 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([122.162.103.97]) by smtp.gmail.com with ESMTPSA id k189-20020a6384c6000000b003fcde69fea5sm13374843pgd.81.2022.06.08.09.15.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 09:15:27 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v4 4/4] target/riscv: Force disable extensions if priv spec version does not match Date: Wed, 8 Jun 2022 21:44:05 +0530 Message-Id: <20220608161405.729964-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220608161405.729964-1-apatel@ventanamicro.com> References: <20220608161405.729964-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We should disable extensions in riscv_cpu_realize() if minimum required priv spec version is not satisfied. This also ensures that machines with priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter extensions. Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the device tree") Signed-off-by: Anup Patel --- target/riscv/cpu.c | 57 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 52 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9f9c27a3f5..953ba2e445 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -43,9 +43,13 @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; struct isa_ext_data { const char *name; - bool enabled; + int min_version; + bool *enabled; }; +#define ISA_EDATA_ENTRY(name, prop) {#name, PRIV_VERSION_1_10_0, &cpu->cfg.prop} +#define ISA_EDATA_ENTRY2(name, min_ver, prop) {#name, min_ver, &cpu->cfg.prop} + const char * const riscv_int_regnames[] = { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -513,8 +517,42 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); CPUClass *cc = CPU_CLASS(mcc); - int priv_version = -1; + int i, priv_version = -1; Error *local_err = NULL; + struct isa_ext_data isa_edata_arr[] = { + ISA_EDATA_ENTRY2(h, PRIV_VERSION_1_12_0, ext_h), + ISA_EDATA_ENTRY2(v, PRIV_VERSION_1_12_0, ext_v), + ISA_EDATA_ENTRY2(zicsr, PRIV_VERSION_1_10_0, ext_icsr), + ISA_EDATA_ENTRY2(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EDATA_ENTRY2(zfh, PRIV_VERSION_1_12_0, ext_zfh), + ISA_EDATA_ENTRY2(zfhmin, PRIV_VERSION_1_12_0, ext_zfhmin), + ISA_EDATA_ENTRY2(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), + ISA_EDATA_ENTRY2(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), + ISA_EDATA_ENTRY2(zba, PRIV_VERSION_1_12_0, ext_zba), + ISA_EDATA_ENTRY2(zbb, PRIV_VERSION_1_12_0, ext_zbb), + ISA_EDATA_ENTRY2(zbc, PRIV_VERSION_1_12_0, ext_zbc), + ISA_EDATA_ENTRY2(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), + ISA_EDATA_ENTRY2(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), + ISA_EDATA_ENTRY2(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), + ISA_EDATA_ENTRY2(zbs, PRIV_VERSION_1_12_0, ext_zbs), + ISA_EDATA_ENTRY2(zk, PRIV_VERSION_1_12_0, ext_zk), + ISA_EDATA_ENTRY2(zkn, PRIV_VERSION_1_12_0, ext_zkn), + ISA_EDATA_ENTRY2(zknd, PRIV_VERSION_1_12_0, ext_zknd), + ISA_EDATA_ENTRY2(zkne, PRIV_VERSION_1_12_0, ext_zkne), + ISA_EDATA_ENTRY2(zknh, PRIV_VERSION_1_12_0, ext_zknh), + ISA_EDATA_ENTRY2(zkr, PRIV_VERSION_1_12_0, ext_zkr), + ISA_EDATA_ENTRY2(zks, PRIV_VERSION_1_12_0, ext_zks), + ISA_EDATA_ENTRY2(zksed, PRIV_VERSION_1_12_0, ext_zksed), + ISA_EDATA_ENTRY2(zksh, PRIV_VERSION_1_12_0, ext_zksh), + ISA_EDATA_ENTRY2(zkt, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EDATA_ENTRY2(zve32f, PRIV_VERSION_1_12_0, ext_zve32f), + ISA_EDATA_ENTRY2(zve64f, PRIV_VERSION_1_12_0, ext_zve64f), + ISA_EDATA_ENTRY2(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), + ISA_EDATA_ENTRY2(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EDATA_ENTRY2(svinval, PRIV_VERSION_1_12_0, ext_svinval), + ISA_EDATA_ENTRY2(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), + ISA_EDATA_ENTRY2(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + }; cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { @@ -541,6 +579,17 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_priv_version(env, priv_version); } + /* Force disable extensions if priv spec version does not match */ + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (*isa_edata_arr[i].enabled && + (env->priv_ver < isa_edata_arr[i].min_version)) { + *isa_edata_arr[i].enabled = false; + warn_report("disabling %s extension for hart 0x%lx because " + "privilege spec version does not match", + isa_edata_arr[i].name, (unsigned long)env->mhartid); + } + } + if (cpu->cfg.mmu) { riscv_set_feature(env, RISCV_FEATURE_MMU); } @@ -1011,8 +1060,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_props(dc, riscv_cpu_properties); } -#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop} - static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) { char *old = *isa_str; @@ -1071,7 +1118,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) }; for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].enabled) { + if (*isa_edata_arr[i].enabled) { new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old = new;