From patchwork Wed Jun 8 17:56:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 12874459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DEFBBC433EF for ; Wed, 8 Jun 2022 17:57:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id C9953C341C5; Wed, 8 Jun 2022 17:57:00 +0000 (UTC) Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 7B41AC3411E for ; Wed, 8 Jun 2022 17:56:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 7B41AC3411E Authentication-Results: smtp.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.kernel.org; spf=fail smtp.mailfrom=broadcom.com Received: by mail-pf1-f171.google.com with SMTP id w21so19028437pfc.0 for ; Wed, 08 Jun 2022 10:56:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=cmEZAD97z630F/G0m4kxLjzdOp5T/fPOtgvbnITZVtE=; b=G/HSzJMQvDqhcfDEOSs2LXuuEiRhuiXR/VJTTu3F1nvUjMw/CUmui6R4VT/FWcmP4f Mqo3S/1si8tzJ6udxtqpskiuTZkUMRfMw2auXVfZl7tJwkf01UEsAdk+XwLSXHFmqFTl ObKVfPV9eoVBd3goCtb64P3ezMVm/EHACEuxc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=cmEZAD97z630F/G0m4kxLjzdOp5T/fPOtgvbnITZVtE=; b=Euehwwim6asyImV9rExt4wfZYHscbiK9GG1TCXdexhXLCZzmcJWoaM7lAfHzFIqKCc KbJxRdd7AjxvvECig6sP3XbCnVhP9EDdpN2yoIOMFMTan81JgfHODrX6cwK4g/Pdshlg crNkHgtpcv7zKNrXtGldBYddX3FoSg4JRTgi6QYbd9nRNZ7IbfkQxaxHMM76MC++7hYF /crNcbOuCJNscng+i6D04fSU158yMgs/JhnwUP2zPC5+alLqmjCVorLTWY0O+G6skjB7 Yx0y2tRKYuW793t6N3XgTOo+WdwAdweYqO2J9WjSz/uMja2t80Yp/lDZsDAb1Sb404Is o5JA== X-Gm-Message-State: AOAM533O7PXA5RIABq49dOLWOlUc0uuguOcHtu+fgzWLAhGnNq0chzoW rP4392AnfXPuPPes2kJQwg5ANQ== X-Google-Smtp-Source: ABdhPJwhObrBL9QtqoFr2BRuLqARI1fRvLFFIRBJOWo3/OMPmz+uHrCRZfg9Tn/W9BLGVqYTPR0Prg== X-Received: by 2002:a62:c146:0:b0:51b:8c73:acad with SMTP id i67-20020a62c146000000b0051b8c73acadmr35977065pfg.22.1654711018783; Wed, 08 Jun 2022 10:56:58 -0700 (PDT) Received: from T3500-3.dhcp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id b19-20020a63d813000000b003f66a518e48sm15344762pgh.86.2022.06.08.10.56.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 10:56:58 -0700 (PDT) From: William Zhang To: Linux ARM List List-Id: Cc: tomer.yacoby@broadcom.com, Broadcom Kernel List , anand.gore@broadcom.com, dan.beygelman@broadcom.com, philippe.reynes@softathome.com, f.fainelli@gmail.com, samyon.furman@broadcom.com, kursad.oney@broadcom.com, joel.peshkin@broadcom.com, William Zhang , Arnd Bergmann , Krzysztof Kozlowski , Olof Johansson , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org Subject: [PATCH 2/3] ARM: dts: Add DTS files for bcmbca SoC BCM6756 Date: Wed, 8 Jun 2022 10:56:28 -0700 Message-Id: <20220608175629.31538-3-william.zhang@broadcom.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220608175629.31538-1-william.zhang@broadcom.com> References: <20220608175629.31538-1-william.zhang@broadcom.com> MIME-Version: 1.0 Add DTS for ARMv7 based broadband SoC BCM6756. bcm6756.dtsi is the SoC description DTS header and bcm96756.dts is a simple DTS file for Broadcom BCM96756 Reference board that only enable the UART port. Signed-off-by: William Zhang --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm6756.dtsi | 130 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm96756.dts | 30 ++++++++ 3 files changed, 161 insertions(+) create mode 100644 arch/arm/boot/dts/bcm6756.dtsi create mode 100644 arch/arm/boot/dts/bcm96756.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1d0189b867a1..28af71650567 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -184,6 +184,7 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \ dtb-$(CONFIG_ARCH_BCMBCA) += \ bcm947622.dtb \ bcm963178.dtb \ + bcm96756.dtb \ bcm96846.dtb \ bcm96855.dtb \ bcm96878.dtb diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi new file mode 100644 index 000000000000..ce1b59faf800 --- /dev/null +++ b/arch/arm/boot/dts/bcm6756.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm6756", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>, <&CA7_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm96756.dts b/arch/arm/boot/dts/bcm96756.dts new file mode 100644 index 000000000000..9a4a87ba9c8a --- /dev/null +++ b/arch/arm/boot/dts/bcm96756.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6756.dtsi" + +/ { + model = "Broadcom BCM96756 Reference Board"; + compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +};