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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: f0dpepDlFfOr7Dx2WxPi+nK57SlypF53yNyUyQM3K6KXn8opXvLPQxIHrgRQho1MKbA1UiVDyzQJQcMxtqqc9a09ovc4Mhtjaf7UxbYGXnx5rFoKXZYPkXnBmZ5aHTMMo9ASVtBVAwEzG33yW9j+zWrmOnlxCqWlku+TO2nkEM087nm/0I6vytSM1Prqki+JqyT2uG4vzAaWbmtcSInt1z4BaYBwcydnd4kebsm9uR6lefaV8RIAVbmCOwDnhF/Km+GiCni1SAb/MtAQhxfH29El/x5qpJacSsz/DEn1Q2ztPh1XdhYVYOtStJw3Z004MMVa6IAe4DL5vqlSMTaWhNGUpnxTBrJpVJfgOuNFIgMrwbP4y54oknmQ2lBCIrRxxsQSURAzSNuKpyIpgsjgonbT1mYf/B7+VlmCKwMO5tj2B0I+rPzjpRTF0sDUOAqGrRosBdPkHp/4pLQJK3eUmmHm4THzmukjX9ZRyFIj+YFORoU146bgoD3a5PhcxqQg43UnJq+/EIR0jTor34O7uRdHvao21NA0+pt2GVawcFwunAZkNfkGOC8/isgjsxcDv2lHd3WNxUHqeII/2O4qVEkU9u9kfpiYjxzFd1GJvgQ0yOYQ0NeS98449EleYYV920ykBqPE5kUtCWQw6l4rn2CyA/tF32I6+qlA/5EiuGf5GvyRrvoIl0MevV9gy7cC/H2UIGG4xIo0lNzyTmGAxx7zgvJlgsZN1Xy1eLqkapL93xCgk+quci6ERlH56okH3OTDbiSF8oIbQ+GHeDb+DymzYh6tKHWqPkdkpZwoLZfITaUlLAIiC0S7t+wN9RX7UMQukAmzFPyNFSLJ0uM6+GTwfzh5+JI2nHZdDEHA5ja/qFHZRe8Y3hDRI8l8xlFiJjetEksqxKg79BiPUdtU5f2SYpZ/w+NGbY2/3fzcoEKeYWRhcd6yoempJy7/qAg2whR1807FreGpxKnR3aP/g2MuSDGamC0VIfAzSn0vi9qktSkMIdpGvwzmyHwNg/Bk6loUbF6JYHvn3J/1iKRUPvOwQxqghFspjri4ekkH2gq9zspiSBPOYOV/O2HntB0jvpWdJvsVy/NRsIWGeKOAUIQ8c0VT9xUMpTTkdIo2NN6S2dyZLN9sSVSprZbz7mTTgIOel22Pjb9VcNSeqJNTFKvpSMGMOfyd8EpluubgOFDfP1Z8tK9D7B+81UJHr2zlwA/YLAb8FEEbqH7b8y/evRnHbHB1xBmhndEDDw66I6DTe3Tle//HYROpfJ636WjyKDnhJc+p1zWGOVNsa5/NUZbuPPWNhdkNbUtLlBakp8h0+jeyG2kyOiTzBfA+bCZ2h8vy6PcrBQ5blDwTOTncfye1Jjp4sYGqdRT9y06cYIDvpIVvChuCY7v83435a99TQ2KOTvtXpg87E8RjcP6GaOOmBgBSSrh9f+GDqo29hDNJVVe9mqwKFVFWrh97eqPPvMAJzVZIXji93egBGCxCfOxPFmPjvFDm4q1GJDeNEUbpbm0GvXJOcCvVR8coyQQJ+PD+AdtNXfH+ImT1dXcp2+8O9/s1f4YOWSwlZiGQAirHI2QUJ/OLpMzUEiuSooTauWQswuWucKcKNDbCwD2v0unQkyCR5fbvyuqDD6tv7Ih9zcs/UZK3XGwlrzfNLW6BDZF65W9O2xDkaQVXG5W4Vll4UlcvyruW+xmUJbdMX+l84Go2znOhYdInms5F7H3d1kzj7DJaExs8GQk+Gvb8Cw== X-OriginatorOrg: zenithal.me X-MS-Exchange-CrossTenant-Network-Message-Id: 91bf3cb4-e7c4-49ff-5047-08da4ca3cfe9 X-MS-Exchange-CrossTenant-AuthSource: TYCP286MB1393.JPNP286.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2022 18:46:07.8681 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 436d481c-43b1-4418-8d7f-84c1e4887cf0 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XtWgEDIh4FsCz/dVw/DW7mID4ik0XysF3WhqgeGYW4KXUcMd6rzsjA2RAgCVvZwy X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSZP286MB1063 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220612_120117_253049_EBB07182 X-CRM114-Status: GOOD ( 13.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patch parses Zb/Zk related string from DT and output them in cpuinfo One thing worth noting is that if DT provides zk, all zbkb, zbkc, zbkx and zkn, zkr, zkt would be enabled. Note that zk is a valid extension name and the current DT binding spec allows this. This patch also changes the logical id of existing multi-letter extensions and adds a statement that instead of logical id compatibility, the order is needed. There currently lacks a mechanism to merge them when producing cpuinfo. Namely if you provide a riscv,isa "rv64imafdc_zk_zks", the cpuinfo output would be "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed _zksh_zkt" Tested-by: Jiatai He Signed-off-by: Hongren (Zenithal) Zheng Tested-by: Samuel Ortiz --- arch/riscv/include/asm/hwcap.h | 20 +++++++++++++++++++- arch/riscv/kernel/cpu.c | 14 ++++++++++++++ arch/riscv/kernel/cpufeature.c | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 4e2486881840..02c454a12683 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -49,9 +49,27 @@ extern unsigned long elf_hwcap; * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter * extensions while all the multi-letter extensions should define the next * available logical extension id. + * + * The order of them should be maintained according to the riscv-isa-manual. + * As this is an internal API, changing the id of one extension does + * not affect compatibility. */ enum riscv_isa_ext_id { - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, + RISCV_ISA_EXT_ZBA = RISCV_ISA_EXT_BASE, + RISCV_ISA_EXT_ZBB, + RISCV_ISA_EXT_ZBC, + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZBKX, + RISCV_ISA_EXT_ZBS, + RISCV_ISA_EXT_ZKND, + RISCV_ISA_EXT_ZKNE, + RISCV_ISA_EXT_ZKNH, + RISCV_ISA_EXT_ZKR, + RISCV_ISA_EXT_ZKSED, + RISCV_ISA_EXT_ZKSH, + RISCV_ISA_EXT_ZKT, + RISCV_ISA_EXT_SSCOFPMF, RISCV_ISA_EXT_SVPBMT, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index fba9e9f46a8c..d9ff9bff3d45 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -87,6 +87,20 @@ int riscv_of_parent_hartid(struct device_node *node) * extensions by an underscore. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index a6f62a6d1edd..0c2638365ec2 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -199,6 +199,39 @@ void __init riscv_fill_hwcap(void) } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); + SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); + SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); + SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC); + SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); + SET_ISA_EXT_MAP("zbkb", RISCV_ISA_EXT_ZBKB); + SET_ISA_EXT_MAP("zbkc", RISCV_ISA_EXT_ZBKC); + SET_ISA_EXT_MAP("zbks", RISCV_ISA_EXT_ZBKX); + SET_ISA_EXT_MAP("zknd", RISCV_ISA_EXT_ZKND); + SET_ISA_EXT_MAP("zkne", RISCV_ISA_EXT_ZKNE); + SET_ISA_EXT_MAP("zknh", RISCV_ISA_EXT_ZKNH); + SET_ISA_EXT_MAP("zksed", RISCV_ISA_EXT_ZKSED); + SET_ISA_EXT_MAP("zksh", RISCV_ISA_EXT_ZKSH); + SET_ISA_EXT_MAP("zkr", RISCV_ISA_EXT_ZKR); + SET_ISA_EXT_MAP("zkt", RISCV_ISA_EXT_ZKT); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKB); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKC); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKX); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKND); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNE); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNH); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKB); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKC); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKX); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSED); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSH); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKB); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKC); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKX); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKND); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNE); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNH); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKR); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKT); } #undef SET_ISA_EXT_MAP } From patchwork Sun Jun 12 18:46:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongren Zheng X-Patchwork-Id: 12878778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F080C43334 for ; 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RISC-V currently still has no mature mechanism, but no matter how things in the spec changes, (no matter how "M" mode things change), the kernel still needs to offer some API to the userspace. More discussion can be found at https://github.com/openssl/openssl/pull/18197 In short, userspace currently has to use env var to detect them. This interface does not make any assumptions about the underlying hardware Tested-by: Jiatai He Signed-off-by: Hongren (Zenithal) Zheng --- arch/riscv/include/uapi/asm/hwcap.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h index 46dc3f5ee99f..bfed3e5c338c 100644 --- a/arch/riscv/include/uapi/asm/hwcap.h +++ b/arch/riscv/include/uapi/asm/hwcap.h @@ -22,4 +22,26 @@ #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +/* + * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2 + * + * As only 32 bits of elf_hwcap (in kernel) could be used + * and RISC-V has reserved 26 bits of it, other caps like + * bitmanip and crypto can not be placed in AT_HWCAP + */ +#define COMPAT_HWCAP2_ISA_ZBA (1 << 0) +#define COMPAT_HWCAP2_ISA_ZBB (1 << 1) +#define COMPAT_HWCAP2_ISA_ZBC (1 << 2) +#define COMPAT_HWCAP2_ISA_ZBS (1 << 3) +#define COMPAT_HWCAP2_ISA_ZBKB (1 << 4) +#define COMPAT_HWCAP2_ISA_ZBKC (1 << 5) +#define COMPAT_HWCAP2_ISA_ZBKX (1 << 6) +#define COMPAT_HWCAP2_ISA_ZKND (1 << 7) +#define COMPAT_HWCAP2_ISA_ZKNE (1 << 8) +#define COMPAT_HWCAP2_ISA_ZKNH (1 << 9) +#define COMPAT_HWCAP2_ISA_ZKSED (1 << 10) +#define COMPAT_HWCAP2_ISA_ZKSH (1 << 11) +#define COMPAT_HWCAP2_ISA_ZKR (1 << 12) +#define COMPAT_HWCAP2_ISA_ZKT (1 << 13) + #endif /* _UAPI_ASM_RISCV_HWCAP_H */ From patchwork Sun Jun 12 18:47:31 2022 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Dw5oQjvfr2A0p1uBKG+AVBGhi6O/MDHhztqN14loJH17sf42qVvPECXtOLxDbXBDQFMBOnrvZ/IO0BglTRzMIxr6ovYc2JXqgCENug7crq5l/EdYK/twCnPOj6Kt/RvKpfEt/LWtJ7YqDYRZYvImor2JLqRpKAAokzG0zgxzWoo3zdZokywdLDGxUYPIJXQ2p0A8yW9HhSOQl1oLiNYNFLhaiACxOjpBx89cnl+GcCKPqp8hhzBTZQVOpOsR6cKCCydmg//EToqhAaSGLS5Tkm9pBN94X/fG4O51Hrv5DH0LEJlB+MkxxhWpHUBreiD4ZH3bcp0Ji6nyDK+hMDl2YnKmihmCDvrzJcDy2QNLfb1hGuPsPyR5FWqh3JU+35VToFveRnWIi9ZVzG7K8/6HGQNzG4IQWUvMfrX/iaesEXxH83yCZiq7A14Tw8oMcQXQNuhfTt2U/1xrbBv8C4ZYuY8HYtu3sHksc1i0RLUFw315qPj5rPkGrCve81qJl0Mpc27rgHyeRdyRWReBrufRbLkp9Mi5tRLTGcxNoFnVeeEtJbLlNZJvHNr8wnGSoKHDYrG7yr1r8c9OsFciBGQTP6S2OIAbmhskYKWyfqNToTxN7QOeYUJ9HmkkJ9mRJcRA9Q2S85J2PLa52HDA60YE4TblfG9/bGAeJzVEH0yf45dvHKSN4wthQkFm3rsinPU6bPsograBMNdNEA0GugFjXGppW0CbPfo0UuklCssqVtWKjVlMH0g7fyiuRLTPhNlJlCLSvQ88VAN80ruPrkKAOLoW18hs9PPu7f237aTImqN/vuDKjiSQPZryaQMr70FsH6k7MW8lk9mwg+Wogk036CNX67VTnPlCvYnFIzY8u/WmVc5OkXhc0q3gTEaPNJSlXE0BFrKjp5uTBz9Et2exeFs/lCwAcR+ms8tJyuNHGD3Gft5e9E9/IyXshD1IMUbJDdtIdZfhD0YAyKeJ7laD9lJhCZgVYzZsQ2Uzxza0TKWZ9E6tcGqwQOXueu1BIjaCAiDfR5jWI4BdZX8se470SJZeaVMYtyrm2U87K2y+fiC2n3Pe7KyrmCKSWrx7vxuX9oFjmSBWiWpVayO6BbVKm85Lsfvp2xAXER2taQOQRnzyiAkxTOQotEX7zUMJytHObd72tl4P/ehllHWJ+CF/BhQjWzBLULovHXx1t72KDDm/uN6XMUOpCi05xTutTPxL6mrriRG0q8oXHAi3LF5+VLa8tlEPT6OBdcg4g18o0xsVx+WG0xZYzfV31G0HM98DsIIRSwlVU4ObBfU6MCfAveQ63a1/rnfilp0C3ZQRqQlxlHQ5C/7flZ4GgP1e5eh6QadswmQI8OMOtfk22jMJ5cCSvX53KfPr8o/PvYlo4X85RNrQ7lU14mYHW5kXJD868VUpBlqTNIcf7ngJBNHetwCHXHaHCI/AO6IPTidoQMadOxP869oE5Ci74wrAWQ+6bqzB7xJOkVB/WK+R+yG6Nu1Fpq+uPtYBAho88qCMIcW+Npm3Zp2LvJTOTYjqdMV7CfgjYh6r9+pXRAIiRlIrK6Gmr/TRbYbd6S09dXPjypTiHxIL7/7vHe7gke/Of5+fgHC7wCwB7p/sZZkf6iHckYVjIZiQSVH3PnckD/2k1sCCnc3GewTIUiVTKzejiiMqAXksCM2e+iWrwwJj4NhwZElGiCHQr5emdF/aEfqFOSWIN4Zj5b0d3T86W9LdoSEDeXZTKVUVJ/cPqX0PzxC3dQ== X-OriginatorOrg: zenithal.me X-MS-Exchange-CrossTenant-Network-Message-Id: 70804b8b-6f2e-46d5-0ba6-08da4ca4058f X-MS-Exchange-CrossTenant-AuthSource: TYCP286MB1393.JPNP286.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2022 18:47:37.8892 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 436d481c-43b1-4418-8d7f-84c1e4887cf0 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Wsdr9D1IPhQ+ZYmfVBfl0DOxotLJF5v4MekOgUv+erehpNEEjIeU5us9IkctBaDO X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSZP286MB1063 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220612_114746_466690_E86ADA78 X-CRM114-Status: GOOD ( 14.80 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org One viable way to detect Zb/Zk HWCAP is from the DT binding. No matter how the "M" mode things change, this way can always be an auxiliary way to detect it. Note that QEMU currently has "zba/zbb/zbc/zbs" in their device tree riscv,isa This also fixes the isa2hwcap way as using unsigned char for long extension is not viable. Note that the tolower function ensures functionality. For other no-hwcap extension (e.g. h, s, u), or ("|") with 0 has no effect on hwcap. Tested-by: Jiatai He Signed-off-by: Hongren (Zenithal) Zheng --- arch/riscv/include/asm/elf.h | 2 ++ arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 48 ++++++++++++++++++++++++++-------- 3 files changed, 41 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index 14fc7342490b..cbf70c5ac1a4 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -65,7 +65,9 @@ extern bool compat_elf_check_arch(Elf32_Ehdr *hdr); * but it's not easy, and we've already done it here. */ #define ELF_HWCAP (elf_hwcap) +#define ELF_HWCAP2 (elf_hwcap2) extern unsigned long elf_hwcap; +extern unsigned long elf_hwcap2; /* * This yields a string that ld.so will use to load implementation diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 02c454a12683..ef0349c5d303 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -17,12 +17,14 @@ * instruction set this cpu supports. */ #define ELF_HWCAP (elf_hwcap) +#define ELF_HWCAP2 (elf_hwcap2) enum { CAP_HWCAP = 1, }; extern unsigned long elf_hwcap; +extern unsigned long elf_hwcap2; #define RISCV_ISA_EXT_a ('a' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 0c2638365ec2..40a5ab3962f0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -23,6 +23,7 @@ #define NUM_ALPHA_EXTS ('z' - 'a' + 1) unsigned long elf_hwcap __read_mostly; +unsigned long elf_hwcap2 __read_mostly; /* Host ISA bitmap */ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; @@ -74,21 +75,39 @@ void __init riscv_fill_hwcap(void) const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; int i, j; - static unsigned long isa2hwcap[256] = {0}; - - isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; - isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M; - isa2hwcap['a'] = isa2hwcap['A'] = COMPAT_HWCAP_ISA_A; - isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F; - isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D; - isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C; + static unsigned long isa2hwcap[RISCV_ISA_EXT_MAX] = {0}; + + /* HWCAP */ + isa2hwcap[RISCV_ISA_EXT_i] = COMPAT_HWCAP_ISA_I; + isa2hwcap[RISCV_ISA_EXT_m] = COMPAT_HWCAP_ISA_M; + isa2hwcap[RISCV_ISA_EXT_a] = COMPAT_HWCAP_ISA_A; + isa2hwcap[RISCV_ISA_EXT_f] = COMPAT_HWCAP_ISA_F; + isa2hwcap[RISCV_ISA_EXT_d] = COMPAT_HWCAP_ISA_D; + isa2hwcap[RISCV_ISA_EXT_c] = COMPAT_HWCAP_ISA_C; + /* HWCAP2 */ + isa2hwcap[RISCV_ISA_EXT_ZBA] = COMPAT_HWCAP2_ISA_ZBA; + isa2hwcap[RISCV_ISA_EXT_ZBB] = COMPAT_HWCAP2_ISA_ZBB; + isa2hwcap[RISCV_ISA_EXT_ZBC] = COMPAT_HWCAP2_ISA_ZBC; + isa2hwcap[RISCV_ISA_EXT_ZBS] = COMPAT_HWCAP2_ISA_ZBS; + isa2hwcap[RISCV_ISA_EXT_ZBKB] = COMPAT_HWCAP2_ISA_ZBKB; + isa2hwcap[RISCV_ISA_EXT_ZBKC] = COMPAT_HWCAP2_ISA_ZBKC; + isa2hwcap[RISCV_ISA_EXT_ZBKX] = COMPAT_HWCAP2_ISA_ZBKX; + isa2hwcap[RISCV_ISA_EXT_ZKNE] = COMPAT_HWCAP2_ISA_ZKND; + isa2hwcap[RISCV_ISA_EXT_ZKND] = COMPAT_HWCAP2_ISA_ZKNE; + isa2hwcap[RISCV_ISA_EXT_ZKNH] = COMPAT_HWCAP2_ISA_ZKNH; + isa2hwcap[RISCV_ISA_EXT_ZKSED] = COMPAT_HWCAP2_ISA_ZKSED; + isa2hwcap[RISCV_ISA_EXT_ZKSH] = COMPAT_HWCAP2_ISA_ZKSH; + isa2hwcap[RISCV_ISA_EXT_ZKR] = COMPAT_HWCAP2_ISA_ZKR; + isa2hwcap[RISCV_ISA_EXT_ZKT] = COMPAT_HWCAP2_ISA_ZKT; elf_hwcap = 0; + elf_hwcap2 = 0; bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); for_each_of_cpu_node(node) { unsigned long this_hwcap = 0; + unsigned long this_hwcap2 = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; @@ -187,15 +206,17 @@ void __init riscv_fill_hwcap(void) #define SET_ISA_EXT_MAP(name, bit) \ do { \ if ((ext_end - ext == sizeof(name) - 1) && \ - !memcmp(ext, name, sizeof(name) - 1)) \ + !memcmp(ext, name, sizeof(name) - 1)) { \ + this_hwcap2 |= isa2hwcap[bit]; \ set_bit(bit, this_isa); \ + } \ } while (false) \ if (unlikely(ext_err)) continue; if (!ext_long) { - this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; - set_bit(*ext - 'a', this_isa); + this_hwcap |= isa2hwcap[tolower(*ext) - 'a']; + set_bit(tolower(*ext) - 'a', this_isa); } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); @@ -246,6 +267,11 @@ void __init riscv_fill_hwcap(void) else elf_hwcap = this_hwcap; + if (elf_hwcap2) + elf_hwcap2 &= this_hwcap2; + else + elf_hwcap2 = this_hwcap2; + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); else