From patchwork Mon Jun 13 19:56:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12879998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 803B7C433EF for ; Mon, 13 Jun 2022 19:58:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VjeXvrocVflqDKeeQ/hz8+ka/X1Q6zKdfW4U/JNE3N0=; b=B1jdKqfZiufzDk rcYI+8tS1eigybWoHghQCbsFOtM1l9on35UB7piJnWHKVFqbrJCa2g1ZR26zqOmAXKGg8E0X1n44r SZBztL0iSTBrDaGPlZpaMA7QD4HtZ5695NM/WnwTnMf9G+rMpUAsTE8hwLlZZwelwzQC+3zn0MnLv Xit8tYYtmWGm+fGxMf7598uno8XQRWlK3ro51SzpAVHvljZ0tKBybimnJl+dRp09umJ/KHzvap2R9 HlvDe0Cq3hKt9sVjoRScC3m0tGGw9h6KFOHlOeBQRi3cPuBj+IFkgC72Ar1lDIS5/Z6JZ4fP7hVUi +Sfgc5sbmi3XZmkqEyJA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qBk-005QMA-2U; Mon, 13 Jun 2022 19:57:28 +0000 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qBf-005QL7-Kb for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:25 +0000 Received: by mail-pg1-x536.google.com with SMTP id g186so6520362pgc.1 for ; Mon, 13 Jun 2022 12:57:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JHEBqvjkXFtcJ+qUBNW7+1Xm1a5ZEnXcUDy9oMekAWQ=; b=XcS6UQmDf+C8m9YKYGOusnFCVffgrQStj//J+T4vtRpb8VgAsfxoTf7T3GaDso06eH X95kIF4IKwG/8S1JhVbbu1qsZ3G9zyJTb/zdPBrNw3e3u+BsafMvCjumd1H2HqBLF6sR vo5PIEn0Ap5GtqoJ/NomU+CELebXQIrQn0n2C4cFLCMrUu5MjFj33yt1uLkiNNMLY0Sz WG4+Pal6iFcZuCcYFuVLCJ4D8uGDiCXrROR+P1liCdgg0xVZthTk9ga0rBKF1byxNBQp mHgbrxODTBw7F49GcKmx80eRrSHJkNeSYWxOGbrGIt2oP4Xw3sss5OM9tn9bXFGZTI+y w3lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JHEBqvjkXFtcJ+qUBNW7+1Xm1a5ZEnXcUDy9oMekAWQ=; b=Wi6x7Z0uuI6shWFwdtau4dQ/K1vCr8oy803wjrBG5rNFSI7KBrhsXTMO0WqKhzs2b8 i+9EkyWy/7ER7JIDWMKXtQk0Cz0dzp2rhwW95bfmjIKjMOZVCso1oNGUbwCSQRrWjlhK m0Kyq0iVgffFiDhL00Jm/6BwBLyElJneHmoUGQVx+gv1h0BU/vNJwfeTnmLQDdUUx6F6 RngjAou0N9n1ApGpg20h2LNEPCmcFRK1zQSLe+9ekwYVi657NysBSgB/WgYxl1sZvPRp 3IcunRXrSBHbNfFrhYmA7mh/dNqMhmiSF+Ivo5eJrCFLZj+Fwe+7B5AKejKy7kJ4gXI1 a8bQ== X-Gm-Message-State: AOAM5336r+0spLe6K082bCJjvzvXZ7lsW/0109fnsMlpNxvvh5hsFwhE BVZuR+2arBJDpAEEiVnXjnRVzgCcS/wwtw== X-Google-Smtp-Source: ABdhPJxL8blns0CtPDB1nVU68TFXxXGjE2/ANBGPsJZvdFrheK2PZLnGISiJk46IluCp/UaTXYGycg== X-Received: by 2002:a63:5723:0:b0:3fd:d8b4:c19f with SMTP id l35-20020a635723000000b003fdd8b4c19fmr1081427pgb.137.1655150242909; Mon, 13 Jun 2022 12:57:22 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:22 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 01/15] dt-bindings: arm: add AMD Pensando boards Date: Mon, 13 Jun 2022 12:56:44 -0700 Message-Id: <20220613195658.5607-2-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_125723_717750_9212BB03 X-CRM114-Status: GOOD ( 12.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson Document the compatible for AMD Pensando Elba SoC boards. Signed-off-by: Brad Larson Reviewed-by: Rob Herring Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/amd,pensando.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml diff --git a/Documentation/devicetree/bindings/arm/amd,pensando.yaml b/Documentation/devicetree/bindings/arm/amd,pensando.yaml new file mode 100644 index 000000000000..9f3dea681d24 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amd,pensando.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amd,pensando.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Platforms Device Tree Bindings + +maintainers: + - Brad Larson + +properties: + $nodename: + const: "/" + compatible: + oneOf: + + - description: Boards with Pensando Elba SoC + items: + - enum: + - amd,pensando-elba-ortano + - const: amd,pensando-elba + +additionalProperties: true + +... From patchwork Mon Jun 13 19:56:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12879999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3CA3CCA47B for ; Mon, 13 Jun 2022 19:58:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=btaDX42PKSE/TtWhoKUF3peoOI/1WZik6nlsfAIlg1I=; b=lD5vpVhUJQrZ9g Nd11SKd+LSAtUcgcpVr15ykRGs2/tZhD7v6+n1s+E1gn0vH6IF/e1Y3dx6Wx/FUQ48sm48bJYPfEk BwrWzLbGMOswR3JBFDoZ/lH8AT+obFUJOWbBN/bPvLR9q6SplMGckPUeprusIoOpv8bMjPBen5v6C kDTL1FtjNCLoURfhzlNxBRZ5LVjZSrVL8Mgwf9dZNc2botu0vYX0zwV6x3begALwQW8k4x/H2vkDP k0EPRrKvSlTTadh0QK2ounotzJLXPFkzN8nBxLu0mPSG/cJ+cmDalQhsklbLVkaTbR4cjRR+Nkm4H 65iFnepoF9UKeqNxMqPQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qBu-005QRi-MF; Mon, 13 Jun 2022 19:57:38 +0000 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qBk-005QM1-9x for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:29 +0000 Received: by mail-pg1-x532.google.com with SMTP id 184so6469631pga.12 for ; Mon, 13 Jun 2022 12:57:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KlpSKj9JOxZWHiDBe4+ujhnALAH7aoziqzJ/soAilmk=; b=qA9A4Fka8Wr2+BYttjs3IXzbkv10TKHVOFBIwcQb402ENC23qLAb96PDlp0HKFtHBH gDn+EHjSB7rG1NrjM3fc+UPI7M4UaryOzbZTzN9dePt5MZX8Zt8qNc/gPUU5fqPBW3ZN VAw6uNCQxKRg6aj/KdwWkJlIzXQI6o4ZpYvzgYIAAWL/+S7hygXB8d4kporCLmEXflT2 TaAmtyCZeXZHTZklEHwGuUctzGtnA/kWBeA72Wqku9EPOKs8kLdPJGW3ULmR86feFpI3 zxFMLUez4AQcauxfanrHS0k5QqGdbfh8MUPF5vICDRmYX1oxgmLcJ0twh10uuY5tEvzu j3Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KlpSKj9JOxZWHiDBe4+ujhnALAH7aoziqzJ/soAilmk=; b=Jo9Uw6Q+e2kMqJGA8AlLgU4wNhjmTs8KJlUp2Y95ZsC+REQDumyL8KbaFqDW1+lRDb ilsL0SVS1V/AdAmDUvz09C7t0+QXleXUmzvoZV+CaqAWAMfXjNhJAYGn4nd86mhr8Qxf yv3Cwwu+mnzzF4i2ow1bI5RzZdBzRcR4kGromJ9yI2+RIuLEwk2AFdQbPo67GWs3vGc/ GD14GOTnglM/q+79CkyZqqfIsgcJOUgYd7+e+SLDPSoKMWtY8SviIftba1tyog+UqRwn 4zzRWrDSBGkflwgZnmH5M8+ttQgWlSDuJcSKFIrivJwqNlbASa8exvCY4w3Qe0M9QQqM LijQ== X-Gm-Message-State: AOAM5312WLiC2JfBPYx+wtoTleaNBQ4yjaWY5VDTiOykNCjE1+4pkHS3 bd94jOodzFRel90OIAM+g/VquZn2QQWouw== X-Google-Smtp-Source: ABdhPJwbv7pRTFzk4+nbaX7oGqRi9qzhXvoemRqwa0xYJcXUwR3JB4aRyw3D7Z04QgbHW03QXG4fdw== X-Received: by 2002:a63:234f:0:b0:405:3981:be7 with SMTP id u15-20020a63234f000000b0040539810be7mr1085120pgm.15.1655150246205; Mon, 13 Jun 2022 12:57:26 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:25 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 02/15] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC binding Date: Mon, 13 Jun 2022 12:56:45 -0700 Message-Id: <20220613195658.5607-3-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_125728_394414_20D8AE4D X-CRM114-Status: UNSURE ( 9.22 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and explicitly controls byte-lane enables. Signed-off-by: Brad Larson --- .../devicetree/bindings/mmc/cdns,sdhci.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml index 4207fed62dfe..35bc4cf6f214 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -13,10 +13,24 @@ maintainers: allOf: - $ref: mmc-controller.yaml + - if: + properties: + compatible: + enum: + - amd,pensando-elba-sd4hc + then: + properties: + reg: + items: + - description: Cadence host controller registers + - description: Byte-lane control register + minItems: 2 + properties: compatible: items: - enum: + - amd,pensando-elba-sd4hc - microchip,mpfs-sd4hc - socionext,uniphier-sd4hc - const: cdns,sd4hc From patchwork Mon Jun 13 19:56:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A5F8CCA47B for ; Mon, 13 Jun 2022 19:58:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xVcuM0ad6gcdHsV4gHqBPj7lBBnfh5ARGD8YKeFojH0=; b=e+3niCi6q3R3L0 A+Of36uAiNeOi48ZC6wXPzTMh4IokyWEZ3iIN2lr44ozMy3s2DQPmvILEZDQsh/HjHwdDn9ZetLcH ZVsuijq1TnrSbuijlALGUrOAwRV1yc5bV2ZyMjpox/PmIX4nnQoezktqR9lrURhHxC/G8KdomGUzV o2GixEKaiS7wn6zcxxH0hMwMSZu/6QTZ02cTHldxoH8OaXPkqHpGurKQ3mi7SaG9ioyvWyjST6BOc YSn/y4G9mnljwO1abW2Gc7nks/t7OX5j2sZN0fSeX9qnLJ/38X1Qgyb6pUlcbvJPyao1ynRefDNUm /2N8Hjg728fsF4p2SHFA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qC4-005QW2-Jf; Mon, 13 Jun 2022 19:57:48 +0000 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qBk-005QMf-SY for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:30 +0000 Received: by mail-pg1-x536.google.com with SMTP id 123so6498390pgb.5 for ; Mon, 13 Jun 2022 12:57:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=M1UYg7GTMwR8QvyF4WdR5Vji0u2SBVcigVMf7Zaauyw=; b=EFASMhPxpi6FpSPPbhA4uIbL4jXzSRVgwCZf55APSkj+/eWAdAy8zvth5EBe2WERCi cDGiWOtOniXXOIBMYlZXBGOhh09bhJWtLzz03ZX+6JmHSdzd1T/MlQGnem73/WOdTT+v ALYzBwhbtHI9GDakDwasxjMQV3KLjZzE1f84EBn9oYaedpyFKb09rruVziY96M9e3Arg tkfD2u8e1HkkbaSXwA1Atuva5Im7G6tJYq72sqiTRNzjOCe8UDRnawXFQ3uInBmpEoLZ /49q91RgMJfoxOeMozLo4SpDinJna4mxoqvs687H+ikEiUHR2xU1+PXsepQJO79Pdd/s XM6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=M1UYg7GTMwR8QvyF4WdR5Vji0u2SBVcigVMf7Zaauyw=; b=1/xznBAdiSJhU9M+ULtT6wUIYJZvZKhCJh8elgYi4LTjcyny2GFfJrF68QM1kpz6F0 OVafrop9LaruvvfoVhw/im8xYu7rocbiVoQuExlhd/dlny2KhP5vIhXAPeaA+fsfk5ez 4uOdRnr4HraIOPzZc1j/0E1wSsxNG/RaCpkUbbNwvNqN6kmFwuMw2xw5KJ1q5Tk0bbja IfXA4H7qyLhVpZH1AkB6Q1CCSi+Ift6e8XiQ/RC9M1TX23Q7pGleKGR0iXXMeEq7Nw6J OzE3DJzKBP+1Vz31P34Opd2BJNiLZwcjwofXgugzTRrz65ijQRdvIwhTTZ7QyyYpYEeF c/IA== X-Gm-Message-State: AOAM533PJR12Elh35F2SQgqAFCvtFiLIX79UCyad+Gj+2iz7wXy6cn4N XWoS8GB41RQyJAPfI+y8dN1K1GgAcvt3hQ== X-Google-Smtp-Source: ABdhPJxZ2q40smO9yqIlwfspIo8/tXk9SfFuRqNdL0nhnFvTOu8EKTI+j14CKPw8n+7CXVPu4OrTgA== X-Received: by 2002:a63:b55:0:b0:3fd:a384:bd10 with SMTP id a21-20020a630b55000000b003fda384bd10mr1102840pgl.534.1655150248432; Mon, 13 Jun 2022 12:57:28 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:28 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 03/15] dt-bindings: spi: cdns: Add compatible for AMD Pensando Elba SoC Date: Mon, 13 Jun 2022 12:56:46 -0700 Message-Id: <20220613195658.5607-4-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_125728_949095_902A8407 X-CRM114-Status: UNSURE ( 8.80 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson Document the cadence qspi controller compatible for AMD Pensando Elba SoC boards. The Elba qspi fifo size is 1024. Signed-off-by: Brad Larson Reviewed-by: Rob Herring Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 0a537fa3a641..9268a4882bfd 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -20,11 +20,23 @@ allOf: required: - power-domains + - if: + properties: + compatible: + enum: + - amd,pensando-elba-qspi + then: + properties: + cdns,fifo-depth: + enum: [ 128, 256, 1024 ] + default: 1024 + properties: compatible: oneOf: - items: - enum: + - amd,pensando-elba-qspi - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi From patchwork Mon Jun 13 19:56:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2ED25C43334 for ; Mon, 13 Jun 2022 19:59:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6k+6sxdnLS/ORJPB7JCYrqFxvYOFgY2wLnA83izbM/w=; b=KkfPhu9pFcy1jA 5xnkGlGWPeP0oQjBLhV7saLlp3l8XHHaNLHtoe7ced5QbxPtyHykBXXV1xxnayn88dFTfTeKhuiSQ KE7r3RV8Cms/TGbpORTztHIFF1+iXoTpekepDg9kzbBLeemYkiWpiWKK4gzmfzV8lMJo3wvO/iDH7 dks8l3wSaO6/xqTHVd7oJF62Gjt82nxG2XWFizqxYJTVEdID+3QPrKd2+01TOgf8Hfkhac0KduUd6 4q8/xBpY2eOOnBvgkqoB6ZRyXEZfq8OmD8J9vdD97sbWr8kzqi9ChNAaKheuWwdkqVd4veF70qQzo 3i81wEl2/GJ8btKUJwPw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qCE-005QZe-Tt; Mon, 13 Jun 2022 19:57:59 +0000 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qBq-005QOS-DD for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:35 +0000 Received: by mail-pg1-x52d.google.com with SMTP id h192so6502009pgc.4 for ; Mon, 13 Jun 2022 12:57:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kwsOcdJyzi4VFYxBCTzUn3k4YPAv5NziRQo39dPYRYw=; b=5NouKk1RoKP/ZQdfEFImqZI4UVH4ulIfQu/RBQ68QxbQya7CB9JPSw0aNH+o1fq806 9Sny1eWhk68b1G2UCx3qq9RDcyqT/iQZOS+wVocsBAjJNdkEKEKkQ9QEfajVu/nZuZcP Q27VQ8Wqg4sVFMsVqoChZyJoM6cxO2O53LT4vDw9yQOYKoH3CgSVOfdSHTZYySRQa2HX Z1AwUEhBLaCS6yvw/BmRCgxqFqomZShiZ4XhPClTyO0TV0SMkdA2xyCI2aHMR1amQEsS rc9aFy8tF0ggmONtwpXl5JZyNq3gsgDOnoHwGy5qY7RPE2U0S1SabobXj9Zn5JnIlRbH zb6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kwsOcdJyzi4VFYxBCTzUn3k4YPAv5NziRQo39dPYRYw=; b=ONwjk21p89roYemeKyyW2g1sP5KU/uEZRpeCZIn52dVs3vElZvLWyH5bIo5K66z71r UfdruUJ0WYvlLJ7cdvHoh9pqxQjYAZ2FTcJN3BzvcoGOA+xImJ9Qn1zUTxVllY5u7xge CnUAb0QZXACiTDswuITjeMh/DEYPw5n/q7Tte1yUyNPUJ23gwJA886l119bVoQJ91eZa KzzaYrDIfcv73nxt+kNTPYfQuIL/yvNZqvWP07TcLv2mlzivVrh2O+09qXasHYUrbvF8 RhDVMusAawwKVV4uH0OWXxnItAXGwJ4PbAps0MimtvpeBNMr2i70srXXu31/O+Tvw4K0 LMqw== X-Gm-Message-State: AOAM5319tnoBdnZvQb4lC0IRywISmoipiR4ObtEWQ/9wxrzjvixG+fm+ Ka15SCJaEtU/X1MoUTIUvo6XgL2XLjiM7A== X-Google-Smtp-Source: ABdhPJwJjQXg4744yK1h6U80q2hA9yxTnOTwO3ZYxn9H8X5O7gLQQxaJwrsWn3XeabNgcM5kMe0KHg== X-Received: by 2002:aa7:88c6:0:b0:51c:6e36:fad7 with SMTP id k6-20020aa788c6000000b0051c6e36fad7mr1005972pff.2.1655150250573; Mon, 13 Jun 2022 12:57:30 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:30 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller bindings Date: Mon, 13 Jun 2022 12:56:47 -0700 Message-Id: <20220613195658.5607-5-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_125734_475318_DAA8F859 X-CRM114-Status: UNSURE ( 9.31 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson The AMD Pensando Elba SoC has integrated the DW APB SPI Controller Signed-off-by: Brad Larson Acked-by: Rob Herring --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index e25d44c218f2..2a55b947cffc 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -73,6 +73,8 @@ properties: - renesas,r9a06g032-spi # RZ/N1D - renesas,r9a06g033-spi # RZ/N1S - const: renesas,rzn1-spi # RZ/N1 + - description: AMD Pensando Elba SoC SPI Controller + const: amd,pensando-elba-spi reg: minItems: 1 From patchwork Mon Jun 13 19:56:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7DE06C43334 for ; Mon, 13 Jun 2022 19:59:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NZc2oXR2bpkZq31ZuJ0IssnDxDVoLXG6objVgGLPG2I=; b=BQDM/TvfM1voLp qdmB/eEPxHzNw1fHUotQBPWyXKYCcWuLd1cJkYAGz+oT3b5Sas+ROgFSo29woNOTNukReDV6QZSvS 4FKZK2XYWRl7IgNy3eWiH+CxDUWyC+VrAMIh8XKpup4PaWrwhOp58eCYv8vZf7cKFtv9E15nrN3jH CNRAmgkrBZ/4qnNnLD0+6cA3U7kOwX7tzUBImZZGC3Mnky1XfzIM0D6CrpF0rqW0azF4VyTGOPwo7 a+MKSJLngkDQN7y2UwODcS/d+xYqZMGnnDYlJwQ4XUxH9o/AB6k3qzsdAqTkakX7g6p6dE69Ioav2 QbCxTsYupU4SYo3lDs5A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qCQ-005QfQ-Om; Mon, 13 Jun 2022 19:58:10 +0000 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qBq-005QP2-NW for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:36 +0000 Received: by mail-pj1-x102a.google.com with SMTP id y13-20020a17090a154d00b001eaaa3b9b8dso4129631pja.2 for ; Mon, 13 Jun 2022 12:57:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9KwEdpp4EHLmLSRu+DnyxFCT3lhc8K5jJavvVNa3rlA=; b=zSwz8WVMIHQg4oW9WeNDAAG5c28m66VAZlfBU6xtkU745PQiZZKb0NcxZvtV6OdkA6 jUmkiKU8oM8vJK4s/n2KFz6UJAj1iDwZUD8xAOzILfe3tgYLzMuvnpcJThY+AbQ7YXi3 Ynh+4YuX0oQL0e53nznCoFck6OFTtO7NpTtjRzEXj2n2woXhWgaJnILc1UDimQklqLRD Hkw2Uu/hmWIoe9DNuZIw7PPhaGlRGq2mPhevdDdQeXGKjxjnwPk7hFdTd4UoRVmOoKBl jxtcDBq7meFjO12gTG+DmzvVoN0VtNZWTLr/yJlpdHGc8myRpgahFhOzdF9jc4M5qV+k uN3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9KwEdpp4EHLmLSRu+DnyxFCT3lhc8K5jJavvVNa3rlA=; b=WsugZuLJpBcooaNI4fGZhc1S43h0wnGD1YsfUrEpTT9Fe+vQnG4/b3rBQ+XgtxbsrT fG7vtSCUQKxGeNSgK/f3l9MbyHtOCpJTD/m6VyNPsTWfNCTI/IoTa4pudcZXTXnfH6kq Bhvd2pno8pmLEueY4EdilurfexoIP+6+W/GXANVq1VsBPFY6BpoJONGWMfNNxDYJmTgc ncg6NjksNx0kg2/PJRU/cxak/tjZbyLvYQGj7N2/O7GKSa+vRhmcug1036DYO0RL8xs6 M1xxqRB8Y3G0bcSWLuzVQAg2GG6Vnrskp9/h9WxvmoN9nExHKZDIgvei/S23s1x3tBX+ HzJg== X-Gm-Message-State: AJIora9/IbjwHMU1KaLeNX0j9Mm6DjQVi3zi/6hXgUt1tpU61LB3GQcZ 27lxN3hIlxnU96lRe9WeOLgM0+TeZ8a4GQ== X-Google-Smtp-Source: AGRyM1tKqZ68i4YqpSOiqrY85fOOj1ouN0z23ZiBd+JkShEORj/QXiO7j6X0hHfdYvo6dAeKagS/FA== X-Received: by 2002:a17:90a:9481:b0:1e8:7bbf:fa9a with SMTP id s1-20020a17090a948100b001e87bbffa9amr417565pjo.164.1655150252722; Mon, 13 Jun 2022 12:57:32 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:32 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 05/15] dt-bindings: mfd: syscon: Add amd,pensando-elba-syscon compatible Date: Mon, 13 Jun 2022 12:56:48 -0700 Message-Id: <20220613195658.5607-6-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_125734_808353_F1CF30C0 X-CRM114-Status: UNSURE ( 9.35 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson Add the AMD Pensando Elba SoC system registers compatible. Signed-off-by: Brad Larson Acked-by: Rob Herring --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index fb784045013f..2267f8828e9e 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -38,6 +38,7 @@ properties: - allwinner,sun8i-h3-system-controller - allwinner,sun8i-v3s-system-controller - allwinner,sun50i-a64-system-controller + - amd,pensando-elba-syscon - brcm,cru-clkset - freecom,fsg-cs2-system-controller - hisilicon,dsa-subctrl From patchwork Mon Jun 13 19:56:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4150FC43334 for ; Mon, 13 Jun 2022 19:59:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+tFoE97xoXFOkr20xga2AWB0SHjkck7ox8lHkR85iM0=; b=gJ4QbEcCnR4tst CwYyrBUbXT/lzwy1cPIz483E9YpkHkQXn97e9Qgh9vy2VehTiRGLs5xYTgKQ0fkKyFeOJoqb1vdbV 5EbwGUdwBgr4BDBM2H25jm+IhduAP3FQ9WA/OSwevARJWLf1qXDb+z0P9JAgXWnWNBbWIMhZqOE3J +JbSb9yyTIPO4Oclzo5mxJevZCD4D7flTvF53L9uiuRyRxQFrBSwoG24/Bzo9INjcowcUL/jrjcdU wr2qD0IIrmp943Tm9+qfPlMQglu4883pC0+ir7ZLWcIq45auoRNpFlGtXDk8mIlWWKXR93DuvCevT mrkzQ/95JIpx017Pk9fQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qCf-005QlN-CI; Mon, 13 Jun 2022 19:58:25 +0000 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qBr-005QPh-LB for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:37 +0000 Received: by mail-pj1-x1029.google.com with SMTP id k12-20020a17090a404c00b001eaabc1fe5dso3937856pjg.1 for ; Mon, 13 Jun 2022 12:57:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CxeTCAcTP8AUI8T+Y1RRaiE90Utk4Y2UEreNjJtF518=; b=K/v2jO5IdTe/h76LE2Jxy/tvRZn9AmCccVf1AkXLWlMIzbkmxYm/ZwgFbNO6+3O/Kt 4V9MpxjJroIQakw44BkG+KTieiewz5bO7dRHXDEYbW2tFWdQITQLEFjkVgAgZ++w3zb3 yQ+q0XcGD9QYgULfH+JLrJSAajGFvEvYoFa98mhY72p+MamwyB57K4GpYYQK7hqwOIWw GxxplsF/k6yXLLYJLUdbfWE7FYArvAyiFDSlvX3GjiDAqFHAQUD9anUbzfRM7jJ3VuHK rRt50hbqOH9hhJjNwcJWT8Nait8EO2Mt3MiqE6MXiqHbK1X2Lj1c0ICx66Z5Xo82ZRC5 ysjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CxeTCAcTP8AUI8T+Y1RRaiE90Utk4Y2UEreNjJtF518=; b=slLb8EWYLMcV0HlWkOiQTD0Gw3EFEyjlHaArMPeTiGory5KUm4DtDoivs3LSn090qv f54I/8djk1C/9Nk9ex3DD9l2yt+yl6csnoZb0WWG3Amhq5jix1nSonMJBp5KcB+yymLR /87wEt0/sgCF+aeoMmpKc25nB+h2Z40vporkkJ6nxRAKWCbxlyrW8CNuokLkyyR8meRi W0/MeRkVIoIYDL0h+ZrqmPBEpBVOSCOq1xcKbB3ThrEL4YenvCKsSn/mmjQ38wRdYk6r mg5RrxDsBltvOX6oNr8MlqW3Nwq1lSrrDSywpRh0gAA9AQu9Thij1nKpy2gPM2dB9uat 0Cpg== X-Gm-Message-State: AJIora+We9sCfPnGXL8V2cafkYw+87w4LEE0JanAcXMiOvwtL5sy3Lvk OstGzmRLyKwXALAJY5D01YGTnM98txUi9Q== X-Google-Smtp-Source: AGRyM1uaxRjzT8MWjnK6bWvdvwkw+v6UKaPUZDECQDILWdwJMIHOst5z4ufQem0zzfJHU5KaXms+Sw== X-Received: by 2002:a17:902:a613:b0:168:a216:f3ff with SMTP id u19-20020a170902a61300b00168a216f3ffmr584840plq.21.1655150254961; Mon, 13 Jun 2022 12:57:34 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:34 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 06/15] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando Elba System Resource chip Date: Mon, 13 Jun 2022 12:56:49 -0700 Message-Id: <20220613195658.5607-7-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_125735_914113_12CC3E87 X-CRM114-Status: GOOD ( 14.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson Add support for the AMD Pensando Elba SoC System Resource chip using the SPI interface. The Elba SR is a Multi-function Device supporting device register access using CS0, smbus interface for FRU and board peripherals using CS1, dual Lattice I2C masters for transceiver management using CS2, and CS3 for flash access. Signed-off-by: Brad Larson --- .../bindings/mfd/amd,pensando-elbasr.yaml | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml diff --git a/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml new file mode 100644 index 000000000000..13356800b1cf --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/amd,pensando-elbasr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando Elba SoC Resource Controller bindings + +description: | + AMD Pensando Elba SoC Resource Controller bindings attached to a SPI bus. + +maintainers: + - Brad Larson + +properties: + compatible: + items: + - enum: + - amd,pensando-elbasr + - const: simple-mfd + + spi-max-frequency: + description: Maximum SPI frequency of the device in Hz. + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - spi-max-frequency + +patternProperties: + '^reset-controller@[a-f0-9]+$': + $ref: ../reset/amd,pensando-elbasr-reset.yaml + +additionalProperties: false + +examples: + - | + #include + #include + + spi0 { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <4>; + + spi@0 { + compatible = "amd,pensando-elbasr", "simple-mfd"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <12000000>; + + rstc: reset-controller@0 { + compatible = "amd,pensando-elbasr-reset"; + reg = <0>; + #reset-cells = <1>; + }; + }; + + spi@1 { + compatible = "amd,pensando-elbasr", "simple-mfd"; + reg = <1>; + spi-max-frequency = <12000000>; + }; + + spi@2 { + compatible = "amd,pensando-elbasr", "simple-mfd"; + reg = <2>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; + + spi@3 { + compatible = "amd,pensando-elbasr", "simple-mfd"; + reg = <3>; + spi-max-frequency = <12000000>; + }; + }; + +... From patchwork Mon Jun 13 19:56:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0A0AC433EF for ; Mon, 13 Jun 2022 19:59:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dcD6sLDGHQ/iNSpKl1Qe2u3dUMDHaeL0wQGOHS1FqAQ=; b=iyE6OQT9ml8fpB OAtBn58jzijFpCKTr4kQisn/0shqNbAB0diet46jBghWwOuiO75o9rjer9yMM4TTsh5cO8fPW4MT6 8mRsgZ6kctp6CJEbXSjKW55vnSTKjfo83GoQwKJPP2FfNLLJAfM/xkw3gRm5/vgJNXsdYXJVPWSZa j9CrD8VqNZShcAMGIcnzr/q7WLWBHZ5tRHXuHVcUYGCw+5DZLVoLpvXHXHrqu4k9c9jXOyNkmPm86 96Gr33JaFhSlth/KoJE+9Mjlvbo6/Xj4vMXbQHme961+9J1+rjG/QjbItnnfxmVwLmMhpKspMyk1+ 8/kv0S+6147MHgJ79tlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qD0-005R4H-GY; Mon, 13 Jun 2022 19:58:47 +0000 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qBw-005QRI-23 for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:41 +0000 Received: by mail-pl1-x631.google.com with SMTP id d5so3364717plo.12 for ; Mon, 13 Jun 2022 12:57:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9XPhK7Tm81pQe79Pw/2MjwDbiQKz3NoZ1HTS8NF7C1c=; b=F2qUogG4H3Jjl3npZp4G8zxj5VwYoGiLao3dgfGymTrX/oAPiQGn3mOFB8Aa+UMNwu v5Z6W9i6W2Ot5rqZv1adfZJvS9wJeIJRXo0fLayHSnF3cdRyizVd1eLWixP1qNIGAgvo 9FLcJJNs7V8bAmdG1+/ecJnhty4JBvUL7BpTNgGuOzjg1TjtbBBdwKIC4Ntc2rq7i4wr 07z7+uOBedF97bHLPZMM3Cvf3yill2Qqzzw9K4W9d/uMKsboEDcDYKfRx8wBv9a3Zfso rpkToSmUyp7c+W9K4ELOXeHFnqufW+HuupcJ2eCtpXsaP9qXCKdZtijdplpw3jtk3J3V hZIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9XPhK7Tm81pQe79Pw/2MjwDbiQKz3NoZ1HTS8NF7C1c=; b=dsfkOHu62Q9TfSJ5WWQgzvihlhLBZwWzB80ZzvXxkvd0VIcCA+jOUO57LlW39j3Dgk 7jOGoovz9s2sHJCXZmy1c3hGGauXEsCdA+uVnH4DCCAxiPOgB1tkNbO7CmDStUl2XI1k c6hNhOMergwj1JsL4joAAJkYixct1/r9vNoqIwRKTKZRe/y8PAhtrknzk2sumLVmwzHt beT6pS7tkMk3MXDTpDhlx1DyG+QJijhL2dnyINtFK5ntTJ8qZ++vd6oTXu8J4+GEWxxb H4HNrbdoaDHkUhw4WhYyyCByNClj1pYgsU7lf/xiLEIQzzK2F/kyQxTwiPidI5gFZB0c leyw== X-Gm-Message-State: AJIora+bQyrc0gwgd3jSRAy3JLDJOkBcv7Ce0wPK3lmXyUdd8MhSN2vG AQqC+QtPTIcj7wQzu047Zq50pVlF2mljxA== X-Google-Smtp-Source: ABdhPJw44rPeyDOXLR9BU2JaWMAaNNQFCALOuvD6GgvfqdGFiGEthYrxts1XE7vjVSLg0hMvvDsPQg== X-Received: by 2002:a17:902:e54a:b0:166:50b6:a08b with SMTP id n10-20020a170902e54a00b0016650b6a08bmr689960plf.90.1655150257089; Mon, 13 Jun 2022 12:57:37 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:36 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 07/15] dt-bindings: reset: amd,pensando-elbasr-reset: Add AMD Pensando SR Reset Controller bindings Date: Mon, 13 Jun 2022 12:56:50 -0700 Message-Id: <20220613195658.5607-8-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_125740_161637_6098D61A X-CRM114-Status: GOOD ( 14.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson Document bindings for AMD Pensando Elba SR Reset Controller Signed-off-by: Brad Larson --- .../reset/amd,pensando-elbasr-reset.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/amd,pensando-elbasr-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/amd,pensando-elbasr-reset.yaml b/Documentation/devicetree/bindings/reset/amd,pensando-elbasr-reset.yaml new file mode 100644 index 000000000000..03bb86ebcfd3 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/amd,pensando-elbasr-reset.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/amd,pensando-elbasr-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando Elba SoC Reset Controller Device Tree Bindings + +maintainers: + - Brad Larson + +description: | + AMD Pensando Elba SoC reset controller driver which supports a resource + controller connected to the Elba SoC over a SPI bus. The Elba reset + controller must be defined as a child node of the Elba SPI bus + chip-select 0 node. + + See also: + - dt-bindings/reset/amd,pensando-elba-reset.h + +properties: + $nodename: + pattern: "^reset-controller@[0-9a-f]+$" + + compatible: + const: amd,pensando-elbasr-reset + + reg: + const: 0 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + spi0 { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <4>; + + spi@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rstc: reset-controller@0 { + compatible = "amd,pensando-elbasr-reset"; + reg = <0>; + #reset-cells = <1>; + }; + }; + }; + +... From patchwork Mon Jun 13 19:56:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BB62C433EF for ; Mon, 13 Jun 2022 20:00:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xf1+P4xzrFAfi/TWPt5y5/PCPjrNMVwkkeIJcoAJF9Y=; b=M1EO7NlwFDQuh2 HFYZYtGhJOwJUQr1xar6YF1uIfpnPU340nZ58AQmo9UDA6LEySwVi+KpbsNnGEWp1VTKY9IPFTq4V EGAXcwrA0xG+IxKVwDvI7gA9odFm3RxPn0bhyP90WNpqzmU1SzU6EA2kKC62Hd/b74Jk61lJSCSo4 rUWjXph8+yc6kpZbnowJMc+KsZYRo06rSnpv3jUfgX8yC8bvOBimtGbBPULTXEXoA/4wVdKP2/FyE z+tus/iF2bOWt4910UQZFBo6r+iOglTCG9KrTZXtkPXR7P0yBIgpkzGRqnD1UnD3UxsN6NMMCiDE9 aG0BeHoKErwSf007Dc5g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qDI-005RH9-BH; Mon, 13 Jun 2022 19:59:04 +0000 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qBx-005QSC-AI for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:43 +0000 Received: by mail-pf1-x42c.google.com with SMTP id s37so3979382pfg.11 for ; Mon, 13 Jun 2022 12:57:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nT549qJtxV1BDDwSTKGaAnqRktoPUt/jLCJWLyiPvHw=; b=BInp8cPtPQ4tK/ffMW4nn4lxciVcZ+ZvBkzgyySFAs7iefoJqIbAP4xFkGqyL37X/X QXxWt6GI9d6ccwv4X1BmqqGN+EIjbOPH6WwQ5WlLMlG2QMiBmuXx1Z+Hd/ksSeG2H1Um EqkeLB+Is+HjMnDt1Jq7FjCJwXZ3l/fMEOB3PVymJpLF3U5H9nXzGGlSLX+ES3uq+p64 Fu2xBZEMgvKz96+lkBo2JKQYbzaRb/J+0MH+oTebasIzixN9dGFlHzQaNlnvlk0KJZsw IE1cdzkeDvtADYoexzp8jNInIheVq9nsosRQh+4FMBoDw0+EHy21vycjqA22JqJ8VBL2 Mdyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nT549qJtxV1BDDwSTKGaAnqRktoPUt/jLCJWLyiPvHw=; b=sOWlDM9Buzy/aGQay2YJQ9Q793+KrmNSYukOYO4MAso+D8pKyiP03BL16zJ1yiW42p htPInJ1RPZrnoTCExmpsszaDGYgRIabCO44a/CvaKTrsHn5nMEnjv8sCyR82aaPQebhO 517AcuRc136xUCK2ZRd81r6TqqV7ZoIT04982CnW762ZjLt0iqyCR9EayD6SddwcClp0 tnG2S2RyYijaP4NPnxWcYmGbxHAf1d8t1GeQ/2ui7574K1MXcAyMocItCtVfj1LBYFh9 WskeT9rPr9dDKvJMybJzQy//JJ8k+g4Wek0B61ymlemr4rFqofcFvgcBmFU2zoH+AIZ5 HCUA== X-Gm-Message-State: AOAM533S/aevvvPZ4NgI+penj+T42S0EerRUgUbv1yMsXkCUbas7flDg uzvP2vDYsknMdvEdLeaqKX1emqLt9piJGg== X-Google-Smtp-Source: AGRyM1sHNrT6EA1vne9zoqSs4Kj6VT7gGBwneqiLiE6fypf57czAytG3WSUZqOvsMu1OwLx726vyPQ== X-Received: by 2002:a05:6a00:338e:b0:51b:c452:4210 with SMTP id cm14-20020a056a00338e00b0051bc4524210mr583717pfb.69.1655150259258; Mon, 13 Jun 2022 12:57:39 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:38 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 08/15] MAINTAINERS: Add entry for AMD PENSANDO Date: Mon, 13 Jun 2022 12:56:51 -0700 Message-Id: <20220613195658.5607-9-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_125741_428367_700A95D9 X-CRM114-Status: UNSURE ( 9.81 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson Add entry for AMD PENSANDO maintainer and files Signed-off-by: Brad Larson --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 91e9cd30326d..09828169c7c5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1777,6 +1777,16 @@ N: allwinner N: sun[x456789]i N: sun50i +ARM/AMD PENSANDO ARM64 ARCHITECTURE +M: Brad Larson +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/*/amd,pensando* +F: arch/arm64/boot/dts/amd/elba* +F: drivers/mfd/pensando* +F: drivers/reset/reset-elbasr.c +F: include/dt-bindings/reset/amd,pensando* + ARM/Amlogic Meson SoC CLOCK FRAMEWORK M: Neil Armstrong M: Jerome Brunet From patchwork Mon Jun 13 19:56:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52DC2C433EF for ; Mon, 13 Jun 2022 20:17:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7zaO3IPLG+aOffRpKwL07QjKVzr2nJwbaa2If9vX730=; b=t27Ixt6D2nyD2g VLRzVmzn2vHV64SRpscfeyQgDpw+jjcJFTwuXzOdOpZo0jD31KG5981P1tiTOcUQoWURAlbMjwRWi jwQWluO1yXrpOQxpCIAdmTQPDgHTbeb+EguY+pw3bm5Z8D3Bulsu+cfVjXbWuIgLM5ZsYyOSjSkVk gEs90CT/5+IFoAc50+gyDPqPEe1NSlkIWhOXVtna4mihz8qOQ3RaW4w6Dt/rlkKDXvfrzDkO86zWJ lvkFlh57t49Zlljg8j9J8gNHZjwTxTSsPnx1f8mBHePbV9SzEMe/Dfm9V8BZuUPWyj5neOApSFsv4 dH4QWII5VwZEp9ek/nGg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qTy-005Yco-2Y; Mon, 13 Jun 2022 20:16:18 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qSQ-005Xqe-N2 for linux-arm-kernel@bombadil.infradead.org; Mon, 13 Jun 2022 20:14:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=References:In-Reply-To:Message-Id:Date :Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=Cz4B4vTiwX5UFau4AlWKqfaChYjGtYceKsM8SbFuknE=; b=A8+zd9DnCK2ZAyWB7kAt9m9Lin ODBzL4lsZCfgjWaQguZ+NFZ/FQFin1UIGJLfTyoU1nY3sD6uqnJH+oWBQPiDagSGehjZyxWr0tdDS Xv6W66vfE85SRbsohwz7eLjXYObx3uezoWQ9spOV+DIIkc+kSVFtmfGDOmxm6u1+UEyNOolf7S3VO joa30rZrI3E9d2csK5CVXMsQKoV/fwECOgsV4Iv3nSDUnDSroXfi1x/ryhWGjfnfdtnvmISEag/F6 N/IPy2izqx8brPvFO/Egfs1YLkhpxC+Lz4EmFp0RkgTaAIt+4YjTKBwPiObWX7Za86XwwxgV2hnAQ NNIQbpjA==; Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qC5-007etJ-9F for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:52 +0000 Received: by mail-pf1-x430.google.com with SMTP id bo5so6679586pfb.4 for ; Mon, 13 Jun 2022 12:57:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cz4B4vTiwX5UFau4AlWKqfaChYjGtYceKsM8SbFuknE=; b=xjwz6pVR2JDlnJi8TjlC8OitJtEVZVJPyMn8cHS3OQlIO2PADiAOLWzb05pnZ6YcX4 Fb9Kob2xPXQ4rqY0Pdo2651kMwz3skiiO+5CdNp27D7oef/3TBvYFUDPcq7umJ32lJ09 zmr8KgDWWAxwESoI8LMVx8GAToSFf8OFvO0JlTTDs+Dr1IOh+4eWA1Rn5yfaccqq4Fth sOIocGaremFfwfoeFGncg9LSakyM0QXXswP65KJtlYs/sVAmuj6hv3+zQD2H7RptdtqO ccXPrS7rpidsTXeE/FG/0LygFLfgHRpvUxtJgjpEQmGBQGJAE57Cbrpz37woyZZ9AjKQ +99w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cz4B4vTiwX5UFau4AlWKqfaChYjGtYceKsM8SbFuknE=; b=S869cBsmw7zBHLUU9AbeBlQnk2SeJKs7CAYMEBTohE+6HaDT/lcYdZvzl/hCNQ1yQ9 Uvel2H0rPE+ePDKpWz+gqL5pORORqXQbDnILhobVqStWevkoWzPVo5GvfAJrYjg35b7z zrUDvqNMPPJ6AiOpC/wfUMfhlPXd8pJVpfCWo833BHjV7W7aRt0u8lMjuC0GWp9drPkc SD8T1MBYM3iAbDx9NxEXn/LynjOMIWma+NS3Kl1+ZCFzdNQ42IOt8s2Je5koopnLgiD+ sTgogrfMwCVmjrcSKQ0HEJlr/7AWFMzBOfRGloMUHnR5tsDRtjcnExbc4E0sgnp7+zBY hGxQ== X-Gm-Message-State: AOAM5300/bwqOccZpbtDYw2X4dl6ouOJqWIp7JBUSf+9Wa/BhJz2TIo2 iQUIItlC0YqVhl2ZSCjahMovjnn2KzYX2w== X-Google-Smtp-Source: ABdhPJwTorzgmVtvoHEfYfDX2UNle7UxXE4lSi2QpJ1e4qxBfNkkySveTDtLUH7tmdCIQ7155hzAtg== X-Received: by 2002:a05:6a00:1481:b0:51c:4e9a:f618 with SMTP id v1-20020a056a00148100b0051c4e9af618mr971562pfu.43.1655150261438; Mon, 13 Jun 2022 12:57:41 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:41 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 09/15] arm64: Add config for AMD Pensando SoC platforms Date: Mon, 13 Jun 2022 12:56:52 -0700 Message-Id: <20220613195658.5607-10-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_205750_639071_F1D2705C X-CRM114-Status: GOOD ( 10.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson Add ARCH_PENSANDO configuration option for AMD Pensando SoC based platforms. Signed-off-by: Brad Larson --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 4e6d635a1731..c650a89d8452 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -202,6 +202,18 @@ config ARCH_MXC This enables support for the ARMv8 based SoCs in the NXP i.MX family. +config ARCH_PENSANDO + bool "AMD Pensando Platforms" + help + This enables support for the ARMv8 based AMD Pensando SoC + family to include the Elba SoC. + + AMD Pensando SoCs support a range of Distributed Services + Cards in PCIe format installed into servers. The Elba + SoC includes 16 A-72 CPU cores, 144 programmable P4 + cores for a minimal latency/jitter datapath, and network + interfaces up to 200 Gb/s. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB From patchwork Mon Jun 13 19:56:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD4D5C43334 for ; Mon, 13 Jun 2022 20:16:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2jhop8QLmNgupGcHzAkpls/lsA6tTiHD8sE3PsRmi/Y=; b=dnXzWHiIHhmMvJ k9TtU8jxv76VwDN9ed1l3uRF5ZD5gGcblMfDTOMxUgEFo9Web6RevqvENhR4z72jvB1+ZwGfKnqeI exbJzrxu+xODZcsoOyS/n0su0ncV9+e4T9Ngmh4hEK3eRm3IxP8uH1BXkPHKhk5VCxojPOURDrXXk TknunzlJfKoeql6hKsjkVbOqM5KkqBRbSqvoLbEsY92rPEHjDaa1weLKvtFIH9Tes49v8gtTetvCT aqmVd8KwrP5vfxGzXqRc2gUWQYTDd/DE2PsqeAZbRvGrP2MS1KlqFxD2txOnEh99jppH1YA+HM2uy LLJ59A9mZPVvwsFqAIow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qSo-005Y2V-9H; Mon, 13 Jun 2022 20:15:06 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qSL-005Xqe-2i for linux-arm-kernel@bombadil.infradead.org; Mon, 13 Jun 2022 20:14:37 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=References:In-Reply-To:Message-Id:Date :Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=VXJlE60TzLimhLd0tty5b77lTGeJKh95VUak2wi/XUs=; b=enCW+yVX/o1gSSWhzDCfFTqnq3 FrneGJQL5Jz7jImRavfKwXgHsQB22JG4DY6d7znPrhHH/q2lYmHMwHUDTg83cZoC4HnfLqtG0qze0 UZIk/c4L+ssW9r7XszyVERty7fpSbcHq+amrvGTyYERek97CmnTrBJkC1We5R7FdICsoikCGiuwLe wvcA3sNu+5O9yeY8TB04wkQsB0F2G6751aa6zEGXNo7+/r+6UEQlFSR3artXdguhjCpRUNLGkpf9M TRH5wsb5VB7oDIP0u/1z7Q3VzgodcMJUnMHxi3y72NgW9+5m7dK/G88erCq4qIuwa1XpK4UkVZEBX cr06NA/w==; Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qC5-007etN-LW for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:54 +0000 Received: by mail-pj1-x102b.google.com with SMTP id k5-20020a17090a404500b001e8875e6242so6981352pjg.5 for ; Mon, 13 Jun 2022 12:57:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VXJlE60TzLimhLd0tty5b77lTGeJKh95VUak2wi/XUs=; b=kJ/ii4vt0i1PlUZnRuxuIbTopuOA6qa1kPMQkaaNSw6tHmADzY3d9Xcp+QHdBfWdvv wlzOWbRZ0d5ax1glSh1rNg87HTO4PEzLWy1FpDdrfNtFDAWKYqsnfwzPGb5zUKADw/DU 8t+IiihnEh7fN3qidCCppubFYHQ76N5fPGYoTqAo/MnBi1BP8vJdj4z19PszdEYCfj8K dJ1eiA/693YKj3+FsLYUzdikQw6ZpupAY0PDhxobrQVraw+4BxWuihnZwVFYTorMtl1+ Gy53/SyV2SyzAtE8At/6J8epCxDI8iC9v0dmViKXcw40Zw44+XQgqAo3RV9e3QLezLWS kErg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VXJlE60TzLimhLd0tty5b77lTGeJKh95VUak2wi/XUs=; b=CSI4/JJ24DLB5dvpDKm4UuEmA8sTLZjXVilqiYubdnNQqQWql14yt3ZSODZqIHQm7t pWHtqUyDXx2qda5+lkkkVaSCW3226hgAAHlqJwILMTQLgCwoZBIKj7aT/I65iE2k7fE+ 0dx50XfrRuWJO5rCM1wrhuhEs9Pzs30cM/YFP7F0p6sMoAuNs32jltSlic6dS1GVHI6v xbr6H1Lp3D39cyxHE+92jL5J8fLevF+ZVOnKBLfdBA7DXLcYy3jgdHATllQjGyzz/CFn dKdjRLkbKucs5a8sInINvLDBzLt8vFCJwQGvJWGP3MkffvDzAPvuoCPf/GiLig/HfBwA LUHQ== X-Gm-Message-State: AJIora/6jdE3RxkTb7KAMcDL8w5VP3ewWjzjZ0mEImVEuf6OQHdZsRSm /fMEqglxZqJI8rcLTu0s98lqZ2d1P+2Tew== X-Google-Smtp-Source: AGRyM1vWzTcTfsDd3FUtm2X7cnh++7uLWXt1vnagtQkS1evXyeHkVS2PXMEznsn7tpK0KWpGZ+WXxg== X-Received: by 2002:a17:90b:1b05:b0:1e2:a053:2fad with SMTP id nu5-20020a17090b1b0500b001e2a0532fadmr378048pjb.209.1655150263687; Mon, 13 Jun 2022 12:57:43 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:43 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 10/15] arm64: dts: Add AMD Pensando Elba SoC support Date: Mon, 13 Jun 2022 12:56:53 -0700 Message-Id: <20220613195658.5607-11-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_205751_309131_17C5597D X-CRM114-Status: GOOD ( 15.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson Add AMD Pensando common and Elba SoC specific device nodes Signed-off-by: Brad Larson --- arch/arm64/boot/dts/amd/Makefile | 1 + arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++++++++++ arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 103 ++++++++++ arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++ arch/arm64/boot/dts/amd/elba.dtsi | 191 ++++++++++++++++++ 6 files changed, 618 insertions(+) create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile index 68103a8b0ef5..9bba020fa880 100644 --- a/arch/arm64/boot/dts/amd/Makefile +++ b/arch/arm64/boot/dts/amd/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi new file mode 100644 index 000000000000..274dd80de1a4 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020-2022 AMD Pensando + */ + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; + }; + + cluster1 { + core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; + }; + + cluster2 { + core0 { cpu = <&cpu8>; }; + core1 { cpu = <&cpu9>; }; + core2 { cpu = <&cpu10>; }; + core3 { cpu = <&cpu11>; }; + }; + + cluster3 { + core0 { cpu = <&cpu12>; }; + core1 { cpu = <&cpu13>; }; + core2 { cpu = <&cpu14>; }; + core3 { cpu = <&cpu15>; }; + }; + }; + + /* CLUSTER 0 */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x0>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x1>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x2>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x3>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + }; + + /* CLUSTER 1 */ + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x100>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x101>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x102>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x103>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + }; + + /* CLUSTER 2 */ + cpu8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x200>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x201>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x202>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x203>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + l2_2: l2-cache2 { + compatible = "cache"; + }; + + /* CLUSTER 3 */ + cpu12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x300>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x301>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x302>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x303>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + l2_3: l2-cache3 { + compatible = "cache"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi new file mode 100644 index 000000000000..155d35b8459f --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020-2022, AMD Pensando + */ + +#include + +&ahb_clk { + clock-frequency = <400000000>; +}; + +&emmc_clk { + clock-frequency = <200000000>; +}; + +&flash_clk { + clock-frequency = <400000000>; +}; + +&ref_clk { + clock-frequency = <156250000>; +}; + +&qspi { + status = "okay"; + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + cdns,read-delay = <0>; + cdns,tshsl-ns = <0>; + cdns,tsd2d-ns = <0>; + cdns,tchsh-ns = <0>; + cdns,tslch-ns = <0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-hw-reset; + reset-names = "hw"; + resets = <&rstc EMMC_HW_RESET>; + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&spi0 { + num-cs = <4>; + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, + <&porta 7 GPIO_ACTIVE_LOW>; + status = "okay"; + spi@0 { + compatible = "amd,pensando-elbasr", "simple-mfd"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <12000000>; + + rstc: reset-controller@0 { + compatible = "amd,pensando-elbasr-reset"; + reg = <0>; + #reset-cells = <1>; + }; + }; + + spi@1 { + compatible = "amd,pensando-elbasr", "simple-mfd"; + reg = <1>; + spi-max-frequency = <12000000>; + }; + + spi@2 { + compatible = "amd,pensando-elbasr", "simple-mfd"; + reg = <2>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; + + spi@3 { + compatible = "amd,pensando-elbasr", "simple-mfd"; + reg = <3>; + spi-max-frequency = <12000000>; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts new file mode 100644 index 000000000000..bb64fd042b63 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for AMD Pensando Elba Board. + * + * Copyright (c) 2020-2022 AMD Pensando + */ + +/dts-v1/; + +#include "elba.dtsi" +#include "elba-16core.dtsi" +#include "elba-asic-common.dtsi" +#include "elba-flash-parts.dtsi" + +/ { + model = "AMD Pensando Elba Board"; + compatible = "amd,pensando-elba-ortano", "amd,pensando-elba"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + spi1 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi new file mode 100644 index 000000000000..2599d1b22026 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020-2022 AMD Pensando + */ + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "flash"; + reg = <0x10000 0xfff0000>; + }; + + partition@f0000 { + label = "golduenv"; + reg = <0xf0000 0x10000>; + }; + + partition@100000 { + label = "boot0"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "golduboot"; + reg = <0x180000 0x200000>; + }; + + partition@380000 { + label = "brdcfg0"; + reg = <0x380000 0x10000>; + }; + + partition@390000 { + label = "brdcfg1"; + reg = <0x390000 0x10000>; + }; + + partition@400000 { + label = "goldfw"; + reg = <0x400000 0x3c00000>; + }; + + partition@4010000 { + label = "fwmap"; + reg = <0x4010000 0x20000>; + }; + + partition@4030000 { + label = "fwsel"; + reg = <0x4030000 0x20000>; + }; + + partition@4090000 { + label = "bootlog"; + reg = <0x4090000 0x20000>; + }; + + partition@40b0000 { + label = "panicbuf"; + reg = <0x40b0000 0x20000>; + }; + + partition@40d0000 { + label = "uservars"; + reg = <0x40d0000 0x20000>; + }; + + partition@4200000 { + label = "uboota"; + reg = <0x4200000 0x400000>; + }; + + partition@4600000 { + label = "ubootb"; + reg = <0x4600000 0x400000>; + }; + + partition@4a00000 { + label = "mainfwa"; + reg = <0x4a00000 0x1000000>; + }; + + partition@5a00000 { + label = "mainfwb"; + reg = <0x5a00000 0x1000000>; + }; + + partition@6a00000 { + label = "diaguboot"; + reg = <0x6a00000 0x400000>; + }; + + partition@8000000 { + label = "diagfw"; + reg = <0x8000000 0x7fe0000>; + }; + + partition@ffe0000 { + label = "ubootenv"; + reg = <0xffe0000 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi new file mode 100644 index 000000000000..9739641261c3 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba.dtsi @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020-2022, AMD Pensando + */ + +#include +#include "dt-bindings/interrupt-controller/arm-gic.h" + +/ { + model = "Elba ASIC Board"; + compatible = "amd,pensando-elba"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + dma-coherent; + + ahb_clk: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + emmc_clk: oscillator2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + flash_clk: oscillator3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + ref_clk: oscillator4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@400 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x400 0x0 0x100>; + clocks = <&ahb_clk>; + #address-cells = <1>; + #size-cells = <0>; + i2c-sda-hold-time-ns = <480>; + snps,sda-timeout-ms = <750>; + interrupts = ; + status = "disabled"; + }; + + wdt0: watchdog@1400 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x1400 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + + qspi: spi@2400 { + compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor"; + reg = <0x0 0x2400 0x0 0x400>, + <0x0 0x7fff0000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&flash_clk>; + cdns,fifo-depth = <1024>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x7fff0000>; + status = "disabled"; + }; + + spi0: spi@2800 { + compatible = "amd,pensando-elba-spi"; + reg = <0x0 0x2800 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ahb_clk>; + interrupts = ; + num-cs = <2>; + status = "disabled"; + }; + + gpio0: gpio@4000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x4000 0x0 0x78>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; + + uart0: serial@4800 { + compatible = "ns16550a"; + reg = <0x0 0x4800 0x0 0x100>; + clocks = <&ref_clk>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + gic: interrupt-controller@800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ + <0x0 0xa00000 0x0 0x200000>, /* GICR */ + <0x0 0x60000000 0x0 0x2000>, /* GICC */ + <0x0 0x60010000 0x0 0x1000>, /* GICH */ + <0x0 0x60020000 0x0 0x2000>; /* GICV */ + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + ranges; + interrupt-controller; + interrupts = ; + + /* + * Elba specific pre-ITS is enabled using the + * existing property socionext,synquacer-pre-its + */ + gic_its: msi-controller@820000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x820000 0x0 0x10000>; + msi-controller; + #msi-cells = <1>; + socionext,synquacer-pre-its = + <0xc00000 0x1000000>; + }; + }; + + emmc: mmc@30440000 { + compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc"; + reg = <0x0 0x30440000 0x0 0x10000>, + <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */ + clocks = <&emmc_clk>; + interrupts = ; + cdns,phy-input-delay-sd-highspeed = <0x4>; + cdns,phy-input-delay-legacy = <0x4>; + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>; + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>; + mmc-ddr-1_8v; + status = "disabled"; + }; + + syscon: syscon@307c0000 { + compatible = "amd,pensando-elba-syscon", "syscon"; + reg = <0x0 0x307c0000 0x0 0x3000>; + }; + }; +}; From patchwork Mon Jun 13 19:56:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C2FA2C43334 for ; Mon, 13 Jun 2022 20:17:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KLea4ZQUKCsaqFc6nX1vipdGoeKGrKDzz4inDc51I5g=; b=wZ/8RDp3C09GkY rTKCFC7sMx+/3owmjaOHGTltfJeSaRSmdqQRldc8KmOTORGcOVSBiIilSRr2NcIuB9TlszVJxoTAq 2vr9uKXNbwfIyDR3j6ThMT9kZrSTIOQjyFT1Xj9hqj4UuBocCqPX5DmgximurechpK8CwGLPh8c2V Xhofcwn4oyJVk8G/tc9kRG6wSAZwhv7dszsnbV5GijjMn6s/wlog6umeL5CiBxSCWJ0E3VMqrKjMj etSNfE7fBAp84d4BilrJAx5g5CeVIkHN7Bu9SAVlu9mhxJDScvxqHjn0F/HOiMYq2sw2im+pxMOcb lrLp5Gnt/cVyPRdLnSmw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qTg-005YTi-EF; Mon, 13 Jun 2022 20:16:00 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qSQ-005Xqe-3h for linux-arm-kernel@bombadil.infradead.org; Mon, 13 Jun 2022 20:14:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=References:In-Reply-To:Message-Id:Date :Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=1ctYV5CtpweQWwhemRH689WvsToB4VjKXh88G2Mf0xQ=; b=VNC53ouhPZ2F4C44ylcj2TTPFb daZCrHMptbMyTKANfjcMWrDkb8hsd45tQMa3PfTVvQPOgSRHqUj7xH/xukgrDVn2C9cNZVgznu9G2 fI7BEEaEcbN4m/q6Zq1fEriF9fF0gv0DxFkrSdRWBK4vo/nLTQO38AW/hZ7WIst2Q/RI/snOaw4cR nosraZ9rBLWTsM5uEun+vL2JmdFRkx2rcKELtxW279tH/exWhzeiWZmC2JqKlpTB4XYu2vn890/EL BurHaauS6mbT9gCV5KBO5l+bbQkRl9gdjY8gqpPlupuK0VSMNTgAQgsjZwYMzgxE+BfTA3OoEoBdg l2W/N2LQ==; Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qC5-007etn-LW for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:54 +0000 Received: by mail-pj1-x1036.google.com with SMTP id z14so1815268pjb.4 for ; Mon, 13 Jun 2022 12:57:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1ctYV5CtpweQWwhemRH689WvsToB4VjKXh88G2Mf0xQ=; b=KU4bwCyM432Sc7bUoksU95EBphe6ApddgD25OxO1uN7LgceYRVOSvwXLw2SxXYpDIn TCv9dD+ytgIhPrt1yUCgwwurS5WM5wy14NAeS5J71F83Blm3Y5S+kDuihn2JaYme1jug fSRv+qTWMz3yb6wcvxPz/UBxpUT/kpU4ScKYp1PARfEHAt6khFEBxavh/nXHM/slPzxk a4rYIjwN3vk+y328sZiAfBxb5ILwNpASm7Ssx0lQ9q2MxteA08/8G2ipKk91524cU4IL EI4kfJ6z2ANrjVhx6PKo0hed6/EEZcGkxE88A514wqlU9PRsciL0rY6her3vWu+e/rIK DTng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1ctYV5CtpweQWwhemRH689WvsToB4VjKXh88G2Mf0xQ=; b=sspsZUodFDmyoJZ3YlaNPpW5K9fhkQgt1BfSx8KXTx7BWrkgSD1seMLuvaGMAthVpY ebh5SrUox0HMoAOOnpSRHZhWnwYV9eKPYpZawmHgmOjHfRXKev9I+eW8z06vJCwZMg8f 9NMH8n7PKN1HrOAHsyONS1Rq2BDJNeSj2inYVOFcboAqpeAa3a0UpKaolPXB/4OJuow6 ryAjQsBa5j2rZ5a55DMQvIlzANhEtvJamYF2pMJNakb/8ukNISSMEUOPr70Bl/C1ZC81 WmkiVybQuFKunaheNOTnz57l7ddpogGw4s9DFZpqoygvGujkcoEd1n9lwgxvuxLNXXlM Ousg== X-Gm-Message-State: AJIora/THxPwknv9iHf6mf7xoeOVtXG+wvOcomHJ6BEoSCBq1JTrhBgD oSp9wR8LoyLodcwMCTIYiCIJNkOusHAXbA== X-Google-Smtp-Source: AGRyM1srdQbNwx41tXUnvYf3A9njwwFcL6cYLU2K1BmNaGiywHkukGrpzW0Jj2DIkNtoJHT5mf0eaQ== X-Received: by 2002:a17:902:eccc:b0:167:5c6e:31e4 with SMTP id a12-20020a170902eccc00b001675c6e31e4mr753614plh.90.1655150265894; Mon, 13 Jun 2022 12:57:45 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:45 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 11/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Mon, 13 Jun 2022 12:56:54 -0700 Message-Id: <20220613195658.5607-12-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_205751_298603_2C2BA543 X-CRM114-Status: GOOD ( 16.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 72b1a5a2298c..ebb77ea8e6ba 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -39,6 +39,7 @@ #define CQSPI_DISABLE_DAC_MODE BIT(1) #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(4) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -87,6 +88,7 @@ struct cqspi_st { bool use_dma_read; u32 pd_dev_id; bool wr_completion; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -952,6 +954,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + (void)readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1667,6 +1676,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->use_dma_read = true; if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) cqspi->wr_completion = false; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1789,6 +1800,10 @@ static const struct cqspi_driver_platdata versal_ospi = { .get_dma_status = cqspi_get_versal_dma_status, }; +static const struct cqspi_driver_platdata pen_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1814,6 +1829,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,socfpga-qspi", .data = &socfpga_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pen_cdns_qspi, + }, { /* end of table */ } }; From patchwork Mon Jun 13 19:56:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 960D1C43334 for ; Mon, 13 Jun 2022 20:16:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SGx4OU7bx9f1oo/CxmOoYpp4t9X1SGVClgLJRsDYNSU=; b=OTV8un3zFMGWZI x1tg4Yndm3+Esm/Rwo/qFlw55Em2l8iK+2hCnplkNwyTdBIqAOybM6AicGh7lNmC4yjaNWt1F9eqj 85jbe97BCqF1CLA3f8M644JLyk4/iWOaPsswpXUWSXiUPdEnmzKyUS3tZLhusIKWFEwLU4B6pnRB4 Omr95al3TJoPCyX8iupB8g+Qa/23cLQH8eS82pcfNXygjr8a9rqsrCTVNd4dujmnfwPyTA10gibh8 so/PjpwT45Lho55lsryNXj0iBIo0PtP72zQvh84PsYTiyFHw/mHaJyZQm12T39uS7/Cuk+rC+EAtg XDgoBN4bOIwbhI0Ics7w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qT8-005YAb-0A; Mon, 13 Jun 2022 20:15:26 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qSP-005Xqe-9t for linux-arm-kernel@bombadil.infradead.org; Mon, 13 Jun 2022 20:14:41 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=References:In-Reply-To:Message-Id:Date :Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=J8i7pxRlATiJaJBMzj2+HHtob8Vj/qK6ZZPtSwIgoXA=; b=l1/M73bRvBcbXvqXszfgh7PijI yQwe2hndvoFpZe11QqGZlP6k1uci1UcXqXoWyJ22LCj8PAqwqJCR0s/VNqKEbJ0hl1J/X9sbqZWuu YqH/a/PKj2DrPbUcDSHNYC8TfkWG3v0/DDObRO6VC+JP0YoPq9toZmL585e7Hibi/AZUM+KOlNXIq OetzaHPTskOksdGuyGuFFp+WQfYbtxFqWDEwoEtdCLcKFGg1pY04AhWHTAlRLuUZ7dduiV/IfYt9P CazFrr230LqxyO1zLxJGQYeKnioCkO4vwsHq/SPKbyIOLpgQSlAvi1lRYBJhqt4zISbX49DmbpURj 7ka4DHDw==; Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qC5-007ett-W5 for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:54 +0000 Received: by mail-pf1-x42e.google.com with SMTP id y6so1021562pfr.13 for ; Mon, 13 Jun 2022 12:57:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=J8i7pxRlATiJaJBMzj2+HHtob8Vj/qK6ZZPtSwIgoXA=; b=4qrarwpvCbsYDA44xLBUmDZl3kMBPWrb+F1ZrdAepjnpLQDfe+RK2X+Qb1qy2HapQj 4451teUpU/58Miy4Ynx46DefK0t5OD4nXXCM25B11//M6G0FmbHeFYSzhL9MJuF6Zd83 UGxn9A6rgvd1Wj1l+x0C4pKUcBryFEJIHgp62bC/EKjCI9hr1mxOjIN/zggt56yOIu1L sanCt6I/aOxlK/r1yTsCMVKWZYtDSeCE67NyH42occfi4WX9xoGOB5b5X/UxVbc/NtFu 1apJZ9JVsNYbZunD+od5wCTrHxE9G2NblKyZknT/uhu1qv1qW6L/3DnXsFrwncbu7gu9 zInA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=J8i7pxRlATiJaJBMzj2+HHtob8Vj/qK6ZZPtSwIgoXA=; b=ir7KTocOA2hjHcnMMWP2pKsqIQXBmOpaHT0KyMd8DyHe65IPEkOlq7s1QfTVX7wYRv n0gFU3b0rQrznRFobubfFkwlWvuuGnqq9aR3cGbbiiPHF0S3WZWxx7tReHNFmJ/p9W0c +dkoA+je19jwbRNg+8uV+1z13fYg7o1cBGJfh9NbPVOnfj1Y4Qzhbq+uA26eKKzQO5Nt NPFtkipFnfiX8wp5ET3DpS0h+ou0zZsn2lRpQS+m7LDvsT1VmNGTDrRKjsRiKZ+5YzLo xu6qyihOJUb4l9JhDiFEZ+zzQYn3fRRAVZr5zK6xy3c5BBQMbRsrAO8UNMWfIUS7/PS7 s5XA== X-Gm-Message-State: AOAM532hjYq+8pKLV0voxFh9TJXZ5TnFphFIvlBbaYppfAFV8bPcg2J4 LuH/U0Ni4JGMQ+4V+I0ymbMRuZAgTsNtNA== X-Google-Smtp-Source: ABdhPJyVrR6Wo8rj+rowp622HlFPPwHbw9lplrBcYIho2FBEyOY5wXti9Sz89w7Ii5CZaDeZigAAEw== X-Received: by 2002:a62:a50c:0:b0:510:6b52:cd87 with SMTP id v12-20020a62a50c000000b005106b52cd87mr985088pfm.30.1655150268035; Mon, 13 Jun 2022 12:57:48 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:47 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 12/15] spi: dw: Add support for AMD Pensando Elba SoC Date: Mon, 13 Jun 2022 12:56:55 -0700 Message-Id: <20220613195658.5607-13-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_205751_302505_669F1E2E X-CRM114-Status: GOOD ( 19.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson The AMD Pensando Elba SoC includes a DW apb_ssi v4 controller with device specific chip-select control. The Elba SoC provides four chip-selects where the native DW IP supports two chip-selects. The Elba DW_SPI instance has two native CS signals that are always overridden. Signed-off-by: Brad Larson --- drivers/spi/spi-dw-mmio.c | 66 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 5101c4c6017b..6b7a557759bd 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -53,6 +53,24 @@ struct dw_spi_mscc { void __iomem *spi_mst; /* Not sparx5 */ }; +struct dw_spi_elba { + struct regmap *syscon; +}; + +/* + * Elba SoC does not use ssi, pin override is used for cs 0,1 and + * gpios for cs 2,3 as defined in the device tree. + * + * cs: | 1 0 + * bit: |---3-------2-------1-------0 + * | cs1 cs1_ovr cs0 cs0_ovr + */ +#define ELBA_SPICS_REG 0x2468 +#define ELBA_SPICS_SHIFT(cs) (2 * (cs)) +#define ELBA_SPICS_MASK(cs) (0x3 << ELBA_SPICS_SHIFT(cs)) +#define ELBA_SPICS_SET(cs, val) \ + ((((val) << 1) | 0x1) << ELBA_SPICS_SHIFT(cs)) + /* * The Designware SPI controller (referred to as master in the documentation) * automatically deasserts chip select when the tx fifo is empty. The chip @@ -238,6 +256,53 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev, return 0; } +static void dw_spi_elba_override_cs(struct dw_spi_elba *dwselba, int cs, int enable) +{ + regmap_update_bits(dwselba->syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs), + ELBA_SPICS_SET(cs, enable)); +} + +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws = spi_master_get_devdata(spi->master); + struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); + struct dw_spi_elba *dwselba = dwsmmio->priv; + u8 cs; + + cs = spi->chip_select; + if (cs < 2) + dw_spi_elba_override_cs(dwselba, spi->chip_select, enable); + + /* + * The DW SPI controller needs a native CS bit selected to start + * the serial engine. + */ + spi->chip_select = 0; + dw_spi_set_cs(spi, enable); + spi->chip_select = cs; +} + +static int dw_spi_elba_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + struct dw_spi_elba *dwselba; + struct regmap *regmap; + + regmap = syscon_regmap_lookup_by_compatible("amd,pensando-elba-syscon"); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + dwselba = devm_kzalloc(&pdev->dev, sizeof(*dwselba), GFP_KERNEL); + if (!dwselba) + return -ENOMEM; + dwselba->syscon = regmap; + + dwsmmio->priv = dwselba; + dwsmmio->dws.set_cs = dw_spi_elba_set_cs; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -352,6 +417,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); From patchwork Mon Jun 13 19:56:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0D11C433EF for ; Mon, 13 Jun 2022 20:16:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=g2LqFbJ+ZPwburZgIb30VJGn6cBrQ7K1So8tOfEjI3k=; b=PwiPUt2Ahr4FjJ BbkI3/F79aRNjRTA8r61GJzHVQOT6YepEMSa0UEBMcxPw0B5LeZnj82NZUIXXPp1D8DiSX7+QrPRB R3Rt68Dmi21+QbPHU8+ObGYxeX9V1K/riVVl3i0Xmaga/90+4NIwM1xfrm1p0hkIrtfl+XLcCDlVN yzNFlrG03RTHXQ6vOp/Y8C/gU2Rmg3auFbwm0zBKSTgbdRySyxCXQcK+Alxnm+SvUc1joR/HPq3eO cNDP2Sv3Ir9J8CEBCvSReAAmLiz8DP32QKAVQUCUBeYdYJNihzYWDr//Um7qFJFvr0Zj6fsKjsd64 QV5/FWQct/3wJTKIDcAg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qSa-005XxB-T7; Mon, 13 Jun 2022 20:14:53 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qSH-005Xqe-Cy for linux-arm-kernel@bombadil.infradead.org; Mon, 13 Jun 2022 20:14:33 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=References:In-Reply-To:Message-Id:Date :Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=NyzDSLiO0lq4BsA02jWF6/uTinB+6H1C7pCNp978chk=; b=IMBF8sKyv8iVare78W9t/HYfsA l2nnDb2/Mgs2oTJjN9KAdgp9kFKe4w26N6Vbyh0ebu7MoLvJ++K7c+0gWNQUN00Ou81L3kfhXWm3Y 312mJYGPlKqtGYd2sbOQ5Dft/LX5u2A/htwjj2XocSPt9vqSPGXJh7BRYDrq9shCKR1rNx1DNbUfB 68GxORI3FjIbOmIx71Xa6mqmFqZUSQhbx8XQ6fCIZ/naBhH4V5wUuFbTQoVA8+ip1b8U0B6AVjFlA NuukEsIMJJ0pIsFaSRwKXhpeKU+uhgxYIk6xEi5EiSI30VRTnREan+AkEMZIsCk03GaZtx/gT4kuw BzMqYDxw==; Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qC8-007euB-1w for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:56 +0000 Received: by mail-pj1-x102c.google.com with SMTP id z14so1815413pjb.4 for ; Mon, 13 Jun 2022 12:57:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NyzDSLiO0lq4BsA02jWF6/uTinB+6H1C7pCNp978chk=; b=ZmIcykGkPOVNDIZYaCnElS3kYgIFKxs4S+qJ/poIE9evHsNexrAS3suynT0z0YORse KC5NqMHUfpSgKp1XO9Meg7G2JDHXqN+nT4uTTsGqKhNuA8q8TFPVXYXDgeaa49MowTXM cAqglgnT3ywDffzXS+3/Q+DlsGZCwMLANFe+y0spMlW21AvMiz6LMs9PAlAiTsgJ5F7r n7HMxdTjtajX4dGUuaM3iwNhHyRRSeWuImKjcY9e5wIaJxE70LcTokQfZTbTSjgK4nvQ 2JDDpZ91PSam7PRoWV97Dz1RySV6ZaNd95cqSjkJw6d3cT0+TU8YpkoIjw94JX+Fem06 TEYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NyzDSLiO0lq4BsA02jWF6/uTinB+6H1C7pCNp978chk=; b=7skx+5VJaQryQUyIoJf7cDQOo1o+twShsjhLvTbUgu4D+SQbiGBy4m2vGPmy7X08Xx jxYWVO093JfVq6WJUntwtU8zgUNISNMeVd9kgFT4bn9G0EwkLQ7/hUD8SGQ1qo6/vxAW lUgh4Yg0BdDSzaOTjMcgPQ/aaRZ6gsdGE/r2cBq1+Lj82/F07bCf0MAFc4/5G+Can5ln mnO97xbineLqnZrpT9OCARBrq5A+LOCtY9OeYr5OHZLadSqWVSiYTS5J1ExXa6XxI23u C3FSIf8bx8ABEAdfOd7hL7/5cLTy8IdiAyi9IiwzIwgoT5LqEtD9EADMRssTJyekvMTj E7BQ== X-Gm-Message-State: AJIora/k3LTugZi5qZkccQwtiYcR2jvwJ4CKVy0srGe+F1M0GePlaIaU /modDqm0g4XpHCPWGzoGIlT20f6UVOwIIw== X-Google-Smtp-Source: AGRyM1tJRB1G+7kpXPt5023UTrEaqvVR4vazG7LXSR8ND5eTFK0xKuaEvvCrSvRqmxqYaTDrCGEb+Q== X-Received: by 2002:a17:90a:fd92:b0:1e2:d731:9ad5 with SMTP id cx18-20020a17090afd9200b001e2d7319ad5mr386886pjb.199.1655150270023; Mon, 13 Jun 2022 12:57:50 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:49 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Date: Mon, 13 Jun 2022 12:56:56 -0700 Message-Id: <20220613195658.5607-14-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_205752_391590_857D838F X-CRM114-Status: GOOD ( 25.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson Add support for AMD Pensando Elba SoC which explicitly controls byte-lane enables on writes. Add priv_write_l() which is used on Elba platforms for byte-lane control. Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which allows Elba SoC sdhci_elba_ops to overwrite the SDHCI IO memory accessors. Signed-off-by: Brad Larson --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-cadence.c | 179 ++++++++++++++++++++++++++++--- 2 files changed, 166 insertions(+), 14 deletions(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index d6144978e32d..d0a66a74532e 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -243,6 +243,7 @@ config MMC_SDHCI_CADENCE tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" depends on MMC_SDHCI_PLTFM depends on OF + select MMC_SDHCI_IO_ACCESSORS help This selects the Cadence SD/SDIO/eMMC driver. diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 6f2de54a5987..08253357535a 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "sdhci-pltfm.h" @@ -66,7 +67,12 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; + void __iomem *ctl_addr; /* write control */ + spinlock_t wrlock; /* write lock */ bool enhanced_strobe; + void (*priv_write_l)(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg); + struct reset_control *rst_hw; unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -76,6 +82,11 @@ struct sdhci_cdns_phy_cfg { u8 addr; }; +struct sdhci_cdns_drv_data { + int (*init)(struct platform_device *pdev); + const struct sdhci_pltfm_data pltfm_data; +}; + static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, @@ -90,6 +101,15 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, }; +static inline void sdhci_cdns_priv_writel(struct sdhci_cdns_priv *priv, + u32 val, void __iomem *reg) +{ + if (unlikely(priv->priv_write_l)) + priv->priv_write_l(priv, val, reg); + else + writel(val, reg); +} + static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, u8 addr, u8 data) { @@ -104,17 +124,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); - writel(tmp, reg); + sdhci_cdns_priv_writel(priv, tmp, reg); tmp |= SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + sdhci_cdns_priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); if (ret) return ret; tmp &= ~SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + sdhci_cdns_priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), 0, 10); @@ -191,7 +211,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode) tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); tmp &= ~SDHCI_CDNS_HRS06_MODE; tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); + sdhci_cdns_priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); } static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) @@ -223,7 +243,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) */ for (i = 0; i < 2; i++) { tmp |= SDHCI_CDNS_HRS06_TUNE_UP; - writel(tmp, reg); + sdhci_cdns_priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), @@ -309,6 +329,89 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, sdhci_set_uhs_signaling(host, timing); } +/* + * The Pensando Elba SoC explicitly controls byte-lane enables on writes + * which includes writes to the HRS registers. + */ +static void elba_priv_write_l(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + unsigned long flags; + + spin_lock_irqsave(&priv->wrlock, flags); + writel(0x78, priv->ctl_addr); + writel(val, reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_l(struct sdhci_host *host, u32 val, int reg) +{ + elba_priv_write_l(sdhci_cdns_priv(host), val, host->ioaddr + reg); +} + +static void elba_write_w(struct sdhci_host *host, u16 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + unsigned long flags; + u32 m = (reg & 0x3); + u32 msk = (0x3 << (m)); + + spin_lock_irqsave(&priv->wrlock, flags); + writel(msk << 3, priv->ctl_addr); + writew(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_b(struct sdhci_host *host, u8 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + unsigned long flags; + u32 m = (reg & 0x3); + u32 msk = (0x1 << (m)); + + spin_lock_irqsave(&priv->wrlock, flags); + writel(msk << 3, priv->ctl_addr); + writeb(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static const struct sdhci_ops sdhci_elba_ops = { + .write_l = elba_write_l, + .write_w = elba_write_w, + .write_b = elba_write_b, + .set_clock = sdhci_set_clock, + .get_timeout_clock = sdhci_cdns_get_timeout_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, +}; + +static int elba_drv_init(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + struct resource *iomem; + void __iomem *ioaddr; + + host->mmc->caps |= (MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA); + + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!iomem) + return -ENOMEM; + + /* Byte-lane control register */ + ioaddr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ioaddr)) + return PTR_ERR(ioaddr); + + priv->ctl_addr = ioaddr; + priv->priv_write_l = elba_priv_write_l; + spin_lock_init(&priv->wrlock); + writel(0x78, priv->ctl_addr); + + return 0; +} + static const struct sdhci_ops sdhci_cdns_ops = { .set_clock = sdhci_set_clock, .get_timeout_clock = sdhci_cdns_get_timeout_clock, @@ -318,15 +421,27 @@ static const struct sdhci_ops sdhci_cdns_ops = { .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, }; -static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = { - .ops = &sdhci_cdns_ops, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { + .pltfm_data = { + .ops = &sdhci_cdns_ops, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, }; -static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { - .ops = &sdhci_cdns_ops, +static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = { + .init = elba_drv_init, + .pltfm_data = { + .ops = &sdhci_elba_ops, + }, }; +static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = { + .pltfm_data = { + .ops = &sdhci_cdns_ops, + }, +}; + + static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) { @@ -347,10 +462,26 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, SDHCI_CDNS_HRS06_MODE_MMC_HS400); } +static void sdhci_mmc_hw_reset(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + + dev_info(mmc_dev(host->mmc), "emmc hardware reset\n"); + + reset_control_assert(priv->rst_hw); + /* For eMMC, minimum is 1us but give it 9us for good measure */ + udelay(9); + + reset_control_deassert(priv->rst_hw); + /* For eMMC, minimum is 200us but give it 300us for good measure */ + usleep_range(300, 1000); +} + static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; - const struct sdhci_pltfm_data *data; + const struct sdhci_cdns_drv_data *data; struct sdhci_pltfm_host *pltfm_host; struct sdhci_cdns_priv *priv; struct clk *clk; @@ -369,10 +500,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev) data = of_device_get_match_data(dev); if (!data) - data = &sdhci_cdns_pltfm_data; + data = &sdhci_cdns_drv_data; nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node); - host = sdhci_pltfm_init(pdev, data, + host = sdhci_pltfm_init(pdev, &data->pltfm_data, struct_size(priv, phy_params, nr_phy_params)); if (IS_ERR(host)) { ret = PTR_ERR(host); @@ -389,6 +520,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev) host->ioaddr += SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe = sdhci_cdns_hs400_enhanced_strobe; + if (data->init) { + ret = data->init(pdev); + if (ret) + goto free; + } sdhci_enable_v4_mode(host); __sdhci_read_caps(host, &version, NULL, NULL); @@ -404,6 +540,17 @@ static int sdhci_cdns_probe(struct platform_device *pdev) if (ret) goto free; + if (host->mmc->caps & MMC_CAP_HW_RESET) { + priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, "hw"); + if (IS_ERR(priv->rst_hw)) { + ret = PTR_ERR(priv->rst_hw); + if (ret == -ENOENT) + priv->rst_hw = NULL; + } else { + host->mmc_host_ops.card_hw_reset = sdhci_mmc_hw_reset; + } + } + ret = sdhci_add_host(host); if (ret) goto free; @@ -453,7 +600,11 @@ static const struct dev_pm_ops sdhci_cdns_pm_ops = { static const struct of_device_id sdhci_cdns_match[] = { { .compatible = "socionext,uniphier-sd4hc", - .data = &sdhci_cdns_uniphier_pltfm_data, + .data = &sdhci_cdns_uniphier_drv_data, + }, + { + .compatible = "amd,pensando-elba-sd4hc", + .data = &sdhci_elba_drv_data }, { .compatible = "cdns,sd4hc" }, { /* sentinel */ } From patchwork Mon Jun 13 19:56:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2BA99C43334 for ; Mon, 13 Jun 2022 20:16:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xaAN2FibK7boysHA38p4BERqoYpQWaTzUvEzDs8mxi4=; b=e32uOeUXCEkYnP Bt8szFn83OfB0tR/TS+Wot+cXAR11BOf1F5u8WKPlnR/UZuyKBJRK+Hy90z5NLsPhHbKc8x7MYeay w979OUVYdLaulfZaVtXZkWuTvyFIluoGUS3N5yBkHkFObuOWlUGK5NsWg2QkSwBr4/yI+4zbriMx7 tBqoUiSwg2+R9ojrAYnL4pngz/68stLmKsOJlzpulMC7sizFpJPQBLcQF6543m4lML8wtl5fXE3XF 2Y7KwtmkhVytV3FUwqMkSwaW1WVSs2oPlrgePrVbkfoZCI/DRqXDS99zGgXkTtU8Df712jHBh9gxc 74DrW7dLpGNEhGC/tS2w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qSP-005XtR-No; Mon, 13 Jun 2022 20:14:41 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qSG-005Xqe-Et for linux-arm-kernel@bombadil.infradead.org; Mon, 13 Jun 2022 20:14:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=References:In-Reply-To:Message-Id:Date :Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description; bh=oiy8pmLKd5jLwE+dzBEk9banUh3DFbG1WFtGbkSfj/I=; b=ong/BFvqLSpOYOkgGapXvJ+RTu 9tOstWv0dUg5DspTe2B0UxVZtvicUO5DlxI871865mwEs+hBRM5v2jWWhV1TAfIg+NpQ6e87vDSEi CKPLCwFQ/V48VNi7NP1YYjvPIuca7vOl/o5I4M6zK1Au9gsq7RzoLG8usP7UK4vpN8BQmwRVmIDKj 3VSuWSo37FjHXyoHiXrTkx4x80LrJUONHryO1LGkcMineWE6pP75mY4tH85ba/mCFOlx3SEK7sMIt vo0IVmGSSrispGRDkDKXcD5TO8fzzDCmDpBi+RvytTNtp25ouC/E7b9DU/SVk5MDCxqrxPGlGsmF9 qm66bQRg==; Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qC9-007evt-Mi for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:57 +0000 Received: by mail-pj1-x102c.google.com with SMTP id v11-20020a17090a4ecb00b001e2c5b837ccso9801738pjl.3 for ; Mon, 13 Jun 2022 12:57:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oiy8pmLKd5jLwE+dzBEk9banUh3DFbG1WFtGbkSfj/I=; b=c6+KlRIbw7dOeJumIROHC3kDB5jhqjzQbZfzsMSGfzSozKqt5aS/Wa3QLHl4p5BfJX w6gdZ6G6uRq/1JG2TNKNopgLzXSG0jKQF/20mbk8ciaYMCJcf7uwJZqmmIvXwkaoJV1M GhY/r6UzywFAbQqmlMTEJEhLE0DxLy3mJuY8RuirFSavzCjd81lmXDJLEN2Sg40rIRg5 4dsmhb5Z+GDfUHHTP2T9cQJuCXhcQdvMCOUgiPvhqWvFz+79cYlrTjV5R1ADkwh4yUqX 63Cd84XuN1HIXEh2IvRcsvuyO4TTnZMx9d98DVMmOVakA0MK5t9FVV7Q6qO/wa2WFEYh T4AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oiy8pmLKd5jLwE+dzBEk9banUh3DFbG1WFtGbkSfj/I=; b=3tQU8xWLYb19OxdQeO6S7uLZTppeonOcDuRHtn67Gfm2+cib0bvoid6ServQa5zO0O wIzL8eUCgFwGrxihsXe/8yDLGwOV9vGyO8bwvlBvVWGg3GHiv/fcgAb3JpgMUlyfEkWd FWISTT9kuvreH126WaDLGUKDRg3sTyqTJOLD90qvFcwdINoHDTAbWVxf7KK5urxRgC0d IA2mHEIyBdMiYvIPo9xZALQLpa6yDFh0KjgScxfBBy2eGcXcYHya9+O5NkX9Pit8iiog Lqw5Gd/rW/e7rKqgcZ1ajhHdhdBdf9DUs79DEoAaKa+NGZiFSjiIJG3na7Vn9Se0/wPR NXCw== X-Gm-Message-State: AJIora8nd8vWI4jIpKB02kCWAry8/y6J5LDunAA+sp+7DbyLnJHf0rEx SDIYcfxpVLFqkHheqssDmlz/pAHVfwX07A== X-Google-Smtp-Source: AGRyM1vcP+VOqsciXePe4Tq2ODUrI3S9zkRdb52odHxzTYFvBLU2YV+KgZUAphyN/P2Kp3HucqLGGQ== X-Received: by 2002:a17:90b:1e44:b0:1e2:e772:5f08 with SMTP id pi4-20020a17090b1e4400b001e2e7725f08mr394531pjb.129.1655150272137; Mon, 13 Jun 2022 12:57:52 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:51 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 14/15] mfd: pensando-elbasr: Add AMD Pensando Elba System Resource chip Date: Mon, 13 Jun 2022 12:56:57 -0700 Message-Id: <20220613195658.5607-15-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_205754_355325_346D2284 X-CRM114-Status: GOOD ( 35.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson Add support for the AMD Pensando Elba SoC System Resource chip using the SPI interface. The Elba SR is a Multi-function Device supporting device register access using CS0, smbus interface for FRU and board peripherals using CS1, dual Lattice I2C masters for transceiver management using CS2, and CS3 for flash access. Signed-off-by: Brad Larson --- drivers/mfd/Kconfig | 14 + drivers/mfd/Makefile | 1 + drivers/mfd/pensando-elbasr.c | 862 ++++++++++++++++++++++++++++ include/linux/mfd/pensando-elbasr.h | 78 +++ 4 files changed, 955 insertions(+) create mode 100644 drivers/mfd/pensando-elbasr.c create mode 100644 include/linux/mfd/pensando-elbasr.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 3b59456f5545..c5e10d302586 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1050,6 +1050,20 @@ config UCB1400_CORE To compile this driver as a module, choose M here: the module will be called ucb1400_core. +config MFD_PENSANDO_ELBASR + bool "AMD Pensando Elba System Resource chip" + depends on SPI_MASTER=y + depends on (ARCH_PENSANDO && OF) || COMPILE_TEST + select REGMAP_SPI + select MFD_CORE + select MFD_SYSCON + help + Support for the AMD Pensando Elba SoC System Resource chip using the + SPI interface. This driver provides userspace access to four device + functions to include CS0 device registers, CS1 smbus interface for + FRU and board peripherals, CS2 dual Lattice I2C masters for + transceiver management, and CS3 flash for firmware update. + config MFD_PM8XXX tristate "Qualcomm PM8xxx PMIC chips driver" depends on (ARM || HEXAGON || COMPILE_TEST) diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 858cacf659d6..917b128abe5b 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -212,6 +212,7 @@ obj-$(CONFIG_MFD_INTEL_LPSS_PCI) += intel-lpss-pci.o obj-$(CONFIG_MFD_INTEL_LPSS_ACPI) += intel-lpss-acpi.o obj-$(CONFIG_MFD_INTEL_PMC_BXT) += intel_pmc_bxt.o obj-$(CONFIG_MFD_PALMAS) += palmas.o +obj-$(CONFIG_MFD_PENSANDO_ELBASR) += pensando-elbasr.o obj-$(CONFIG_MFD_VIPERBOARD) += viperboard.o obj-$(CONFIG_MFD_NTXEC) += ntxec.o obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o diff --git a/drivers/mfd/pensando-elbasr.c b/drivers/mfd/pensando-elbasr.c new file mode 100644 index 000000000000..f689f68f5377 --- /dev/null +++ b/drivers/mfd/pensando-elbasr.c @@ -0,0 +1,862 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * AMD Pensando Elba System Resource MFD Driver + * + * Userspace interface and reset driver support for SPI connected + * Pensando Elba System Resource Chip. + * + * Adapted from spidev.c + * + * Copyright (C) 2006 SWAPP + * Andrea Paterniani + * Copyright (C) 2007 David Brownell (simplification, cleanup) + * Copyright (C) 2022 AMD Pensando + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ELBASR_SPI_CMD_REGRD 0x0b +#define ELBASR_SPI_CMD_REGWR 0x02 +#define ELBASR_MAX_DEVS 4 + +/* The main reason to have this class is to make mdev/udev create the + * /dev/pensrB.C character device nodes exposing our userspace API. + * It also simplifies memory management. The device nodes + * /dev/pensrB.C are common across Pensando boards. + */ +static struct class *elbasr_class; + +static dev_t elbasr_devt; +static DECLARE_BITMAP(minors, ELBASR_MAX_DEVS); +static unsigned int bufsiz = 4096; + +static LIST_HEAD(device_list); +static DEFINE_MUTEX(device_list_lock); + +static const struct mfd_cell pensando_elbasr_subdev_info[] = { + { + .name = "pensando_elbasr_reset", + .of_compatible = "amd,pensando-elbasr-reset", + }, +}; + +/* Bit masks for spi_device.mode management. Note that incorrect + * settings for some settings can cause *lots* of trouble for other + * devices on a shared bus: + * + * - CS_HIGH ... this device will be active when it shouldn't be + * - 3WIRE ... when active, it won't behave as it should + * - NO_CS ... there will be no explicit message boundaries; this + * is completely incompatible with the shared bus model + * - READY ... transfers may proceed when they shouldn't. + */ +#define SPI_MODE_MASK (SPI_CPHA | SPI_CPOL | SPI_CS_HIGH \ + | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP \ + | SPI_NO_CS | SPI_READY | SPI_TX_DUAL \ + | SPI_TX_QUAD | SPI_TX_OCTAL | SPI_RX_DUAL \ + | SPI_RX_QUAD | SPI_RX_OCTAL) + +static ssize_t +elbasr_spi_sync(struct elbasr_data *elbasr_spi, struct spi_message *message) +{ + int status; + struct spi_device *spi; + + spin_lock_irq(&elbasr_spi->spi_lock); + spi = elbasr_spi->spi; + spin_unlock_irq(&elbasr_spi->spi_lock); + + if (spi == NULL) + status = -ESHUTDOWN; + else + status = spi_sync(spi, message); + + if (status == 0) + status = message->actual_length; + + return status; +} + +static inline ssize_t +elbasr_spi_sync_write(struct elbasr_data *elbasr, size_t len) +{ + struct spi_transfer t = { + .tx_buf = elbasr->tx_buffer, + .len = len, + .speed_hz = elbasr->speed_hz, + }; + struct spi_message m; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + return elbasr_spi_sync(elbasr, &m); +} + +static inline ssize_t +elbasr_spi_sync_read(struct elbasr_data *elbasr, size_t len) +{ + struct spi_transfer t = { + .rx_buf = elbasr->rx_buffer, + .len = len, + .speed_hz = elbasr->speed_hz, + }; + struct spi_message m; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + return elbasr_spi_sync(elbasr, &m); +} + +/* Read-only message with current device setup */ +static ssize_t +elbasr_spi_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos) +{ + struct elbasr_data *elbasr; + ssize_t status; + + /* chipselect only toggles at start or end of operation */ + if (count > bufsiz) + return -EMSGSIZE; + + elbasr = filp->private_data; + + mutex_lock(&elbasr->buf_lock); + status = elbasr_spi_sync_read(elbasr, count); + if (status > 0) { + unsigned long missing; + + missing = copy_to_user(buf, elbasr->rx_buffer, status); + if (missing == status) + status = -EFAULT; + else + status = status - missing; + } + mutex_unlock(&elbasr->buf_lock); + + return status; +} + +/* Write-only message with current device setup */ +static ssize_t +elbasr_spi_write(struct file *filp, const char __user *buf, + size_t count, loff_t *f_pos) +{ + struct elbasr_data *elbasr; + ssize_t status; + unsigned long missing; + + /* chipselect only toggles at start or end of operation */ + if (count > bufsiz) + return -EMSGSIZE; + + elbasr = filp->private_data; + + mutex_lock(&elbasr->buf_lock); + missing = copy_from_user(elbasr->tx_buffer, buf, count); + if (missing == 0) + status = elbasr_spi_sync_write(elbasr, count); + else + status = -EFAULT; + mutex_unlock(&elbasr->buf_lock); + + return status; +} + +static int elbasr_spi_message(struct elbasr_data *elbasr, + struct spi_ioc_transfer *u_xfers, + unsigned int n_xfers) +{ + struct spi_message msg; + struct spi_transfer *k_xfers; + struct spi_transfer *k_tmp; + struct spi_ioc_transfer *u_tmp; + unsigned int n, total, tx_total, rx_total; + u8 *tx_buf, *rx_buf; + int status = -EFAULT; + + spi_message_init(&msg); + k_xfers = kcalloc(n_xfers, sizeof(*k_tmp), GFP_KERNEL); + if (k_xfers == NULL) + return -ENOMEM; + + /* Construct spi_message, copying any tx data to bounce buffer. + * We walk the array of user-provided transfers, using each one + * to initialize a kernel version of the same transfer. + */ + tx_buf = elbasr->tx_buffer; + rx_buf = elbasr->rx_buffer; + total = 0; + tx_total = 0; + rx_total = 0; + for (n = n_xfers, k_tmp = k_xfers, u_tmp = u_xfers; + n; + n--, k_tmp++, u_tmp++) { + /* Ensure that also following allocations from rx_buf/tx_buf will meet + * DMA alignment requirements. + */ + unsigned int len_aligned = ALIGN(u_tmp->len, + ARCH_KMALLOC_MINALIGN); + + k_tmp->len = u_tmp->len; + + total += k_tmp->len; + /* Since the function returns the total length of transfers + * on success, restrict the total to positive int values to + * avoid the return value looking like an error. Also check + * each transfer length to avoid arithmetic overflow. + */ + if (total > INT_MAX || k_tmp->len > INT_MAX) { + status = -EMSGSIZE; + goto done; + } + + if (u_tmp->rx_buf) { + /* this transfer needs space in RX bounce buffer */ + rx_total += len_aligned; + if (rx_total > bufsiz) { + status = -EMSGSIZE; + goto done; + } + k_tmp->rx_buf = rx_buf; + rx_buf += len_aligned; + } + if (u_tmp->tx_buf) { + /* this transfer needs space in TX bounce buffer */ + tx_total += len_aligned; + if (tx_total > bufsiz) { + status = -EMSGSIZE; + goto done; + } + k_tmp->tx_buf = tx_buf; + if (copy_from_user(tx_buf, (const u8 __user *) + (uintptr_t) u_tmp->tx_buf, + u_tmp->len)) + goto done; + tx_buf += len_aligned; + } + + k_tmp->cs_change = !!u_tmp->cs_change; + k_tmp->tx_nbits = u_tmp->tx_nbits; + k_tmp->rx_nbits = u_tmp->rx_nbits; + k_tmp->bits_per_word = u_tmp->bits_per_word; + k_tmp->delay.value = u_tmp->delay_usecs; + k_tmp->delay.unit = SPI_DELAY_UNIT_USECS; + k_tmp->speed_hz = u_tmp->speed_hz; + k_tmp->word_delay.value = u_tmp->word_delay_usecs; + k_tmp->word_delay.unit = SPI_DELAY_UNIT_USECS; + if (!k_tmp->speed_hz) + k_tmp->speed_hz = elbasr->speed_hz; +#ifdef VERBOSE + dev_dbg(&elbasr->spi->dev, + " xfer len %u %s%s%s%dbits %u usec %u usec %uHz (%u)\n", + k_tmp->len, + k_tmp->rx_buf ? "rx " : "", + k_tmp->tx_buf ? "tx " : "", + k_tmp->cs_change ? "cs " : "", + k_tmp->bits_per_word ? : elbasr->spi->bits_per_word, + k_tmp->delay.value, + k_tmp->word_delay.value, + k_tmp->speed_hz ? : elbasr->spi->max_speed_hz); +#endif + spi_message_add_tail(k_tmp, &msg); + } + + status = elbasr_spi_sync(elbasr, &msg); + if (status < 0) + goto done; + + /* copy any rx data out of bounce buffer */ + for (n = n_xfers, k_tmp = k_xfers, u_tmp = u_xfers; + n; + n--, k_tmp++, u_tmp++) { + if (u_tmp->rx_buf) { + if (copy_to_user((u8 __user *) + (uintptr_t) u_tmp->rx_buf, k_tmp->rx_buf, + u_tmp->len)) { + status = -EFAULT; + goto done; + } + } + } + status = total; + +done: + kfree(k_xfers); + return status; +} + +static struct spi_ioc_transfer * +elbasr_spi_get_ioc_message(unsigned int cmd, + struct spi_ioc_transfer __user *u_ioc, + unsigned int *n_ioc) +{ + u32 tmp; + + /* Check type, command number and direction */ + if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC + || _IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0)) + || _IOC_DIR(cmd) != _IOC_WRITE) + return ERR_PTR(-ENOTTY); + + tmp = _IOC_SIZE(cmd); + if ((tmp % sizeof(struct spi_ioc_transfer)) != 0) + return ERR_PTR(-EINVAL); + *n_ioc = tmp / sizeof(struct spi_ioc_transfer); + if (*n_ioc == 0) + return NULL; + + /* copy into scratch area */ + return memdup_user(u_ioc, tmp); +} + +static long +elbasr_spi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + int retval = 0; + struct elbasr_data *elbasr; + struct spi_device *spi; + u32 tmp; + unsigned int n_ioc; + struct spi_ioc_transfer *ioc; + + /* Check type and command number */ + if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC) + return -ENOTTY; + + /* guard against device removal before, or while, + * we issue this ioctl. + */ + elbasr = filp->private_data; + spin_lock_irq(&elbasr->spi_lock); + spi = spi_dev_get(elbasr->spi); + spin_unlock_irq(&elbasr->spi_lock); + + if (spi == NULL) + return -ESHUTDOWN; + + /* use the buffer lock here for triple duty: + * - prevent I/O (from us) so calling spi_setup() is safe; + * - prevent concurrent SPI_IOC_WR_* from morphing + * data fields while SPI_IOC_RD_* reads them; + * - SPI_IOC_MESSAGE needs the buffer locked "normally". + */ + mutex_lock(&elbasr->buf_lock); + + switch (cmd) { + /* read requests */ + case SPI_IOC_RD_MODE: + retval = put_user(spi->mode & SPI_MODE_MASK, + (__u8 __user *)arg); + break; + case SPI_IOC_RD_MODE32: + retval = put_user(spi->mode & SPI_MODE_MASK, + (__u32 __user *)arg); + break; + case SPI_IOC_RD_LSB_FIRST: + retval = put_user((spi->mode & SPI_LSB_FIRST) ? 1 : 0, + (__u8 __user *)arg); + break; + case SPI_IOC_RD_BITS_PER_WORD: + retval = put_user(spi->bits_per_word, (__u8 __user *)arg); + break; + case SPI_IOC_RD_MAX_SPEED_HZ: + retval = put_user(elbasr->speed_hz, (__u32 __user *)arg); + break; + + /* write requests */ + case SPI_IOC_WR_MODE: + case SPI_IOC_WR_MODE32: + if (cmd == SPI_IOC_WR_MODE) + retval = get_user(tmp, (u8 __user *)arg); + else + retval = get_user(tmp, (u32 __user *)arg); + if (retval == 0) { + struct spi_controller *ctlr = spi->controller; + u32 save = spi->mode; + + if (tmp & ~SPI_MODE_MASK) { + retval = -EINVAL; + break; + } + + if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods && + ctlr->cs_gpiods[spi->chip_select]) + tmp |= SPI_CS_HIGH; + + tmp |= spi->mode & ~SPI_MODE_MASK; + spi->mode = (u16)tmp; + retval = spi_setup(spi); + if (retval < 0) + spi->mode = save; + else + dev_dbg(&spi->dev, "spi mode %x\n", tmp); + } + break; + case SPI_IOC_WR_LSB_FIRST: + retval = get_user(tmp, (__u8 __user *)arg); + if (retval == 0) { + u32 save = spi->mode; + + if (tmp) + spi->mode |= SPI_LSB_FIRST; + else + spi->mode &= ~SPI_LSB_FIRST; + retval = spi_setup(spi); + if (retval < 0) + spi->mode = save; + else + dev_dbg(&spi->dev, "%csb first\n", + tmp ? 'l' : 'm'); + } + break; + case SPI_IOC_WR_BITS_PER_WORD: + retval = get_user(tmp, (__u8 __user *)arg); + if (retval == 0) { + u8 save = spi->bits_per_word; + + spi->bits_per_word = tmp; + retval = spi_setup(spi); + if (retval < 0) + spi->bits_per_word = save; + else + dev_dbg(&spi->dev, "%d bits per word\n", tmp); + } + break; + case SPI_IOC_WR_MAX_SPEED_HZ: + retval = get_user(tmp, (__u32 __user *)arg); + if (retval == 0) { + u32 save = spi->max_speed_hz; + + spi->max_speed_hz = tmp; + retval = spi_setup(spi); + if (retval == 0) { + elbasr->speed_hz = tmp; + dev_dbg(&spi->dev, "%d Hz (max)\n", + elbasr->speed_hz); + } + spi->max_speed_hz = save; + } + break; + + default: + /* segmented and/or full-duplex I/O request */ + /* Check message and copy into scratch area */ + ioc = elbasr_spi_get_ioc_message(cmd, + (struct spi_ioc_transfer __user *)arg, &n_ioc); + if (IS_ERR(ioc)) { + retval = PTR_ERR(ioc); + break; + } + if (!ioc) + break; /* n_ioc is also 0 */ + + /* translate to spi_message, execute */ + retval = elbasr_spi_message(elbasr, ioc, n_ioc); + kfree(ioc); + break; + } + + mutex_unlock(&elbasr->buf_lock); + spi_dev_put(spi); + return retval; +} + +#ifdef CONFIG_COMPAT +static long +elbasr_spi_compat_ioc_message(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + struct spi_ioc_transfer __user *u_ioc; + int retval = 0; + struct elbasr_data *elbasr; + struct spi_device *spi; + unsigned int n_ioc, n; + struct spi_ioc_transfer *ioc; + + u_ioc = (struct spi_ioc_transfer __user *) compat_ptr(arg); + + /* guard against device removal before, or while, + * we issue this ioctl. + */ + elbasr = filp->private_data; + spin_lock_irq(&elbasr->spi_lock); + spi = spi_dev_get(elbasr->spi); + spin_unlock_irq(&elbasr->spi_lock); + + if (spi == NULL) + return -ESHUTDOWN; + + /* SPI_IOC_MESSAGE needs the buffer locked "normally" */ + mutex_lock(&elbasr->buf_lock); + + /* Check message and copy into scratch area */ + ioc = elbasr_spi_get_ioc_message(cmd, u_ioc, &n_ioc); + if (IS_ERR(ioc)) { + retval = PTR_ERR(ioc); + goto done; + } + if (!ioc) + goto done; /* n_ioc is also 0 */ + + /* Convert buffer pointers */ + for (n = 0; n < n_ioc; n++) { + ioc[n].rx_buf = (uintptr_t) compat_ptr(ioc[n].rx_buf); + ioc[n].tx_buf = (uintptr_t) compat_ptr(ioc[n].tx_buf); + } + + /* translate to spi_message, execute */ + retval = elbasr_spi_message(elbasr, ioc, n_ioc); + kfree(ioc); + +done: + mutex_unlock(&elbasr->buf_lock); + spi_dev_put(spi); + return retval; +} + +static long +elbasr_spi_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + if (_IOC_TYPE(cmd) == SPI_IOC_MAGIC + && _IOC_NR(cmd) == _IOC_NR(SPI_IOC_MESSAGE(0)) + && _IOC_DIR(cmd) == _IOC_WRITE) + return elbasr_spi_compat_ioc_message(filp, cmd, arg); + + return elbasr_spi_ioctl(filp, cmd, (unsigned long)compat_ptr(arg)); +} +#else +#define elbasr_spi_compat_ioctl NULL +#endif /* CONFIG_COMPAT */ + +static int elbasr_spi_open(struct inode *inode, struct file *filp) +{ + struct elbasr_data *elbasr; + int status = -ENXIO; + + mutex_lock(&device_list_lock); + + list_for_each_entry(elbasr, &device_list, device_entry) { + if (elbasr->devt == inode->i_rdev) { + status = 0; + break; + } + } + + if (status) { + pr_debug("elbasr_spi: nothing for minor %d\n", iminor(inode)); + goto err_find_dev; + } + + if (!elbasr->tx_buffer) { + elbasr->tx_buffer = kmalloc(bufsiz, GFP_KERNEL); + if (!elbasr->tx_buffer) { + status = -ENOMEM; + goto err_find_dev; + } + } + + if (!elbasr->rx_buffer) { + elbasr->rx_buffer = kmalloc(bufsiz, GFP_KERNEL); + if (!elbasr->rx_buffer) { + status = -ENOMEM; + goto err_alloc_rx_buf; + } + } + + elbasr->users++; + filp->private_data = elbasr; + stream_open(inode, filp); + + mutex_unlock(&device_list_lock); + return 0; + +err_alloc_rx_buf: + kfree(elbasr->tx_buffer); + elbasr->tx_buffer = NULL; +err_find_dev: + mutex_unlock(&device_list_lock); + return status; +} + +static int elbasr_spi_release(struct inode *inode, struct file *filp) +{ + struct elbasr_data *elbasr; + int dofree; + + mutex_lock(&device_list_lock); + elbasr = filp->private_data; + filp->private_data = NULL; + + spin_lock_irq(&elbasr->spi_lock); + /* ... after we unbound from the underlying device? */ + dofree = (elbasr->spi == NULL); + spin_unlock_irq(&elbasr->spi_lock); + + /* last close? */ + elbasr->users--; + if (!elbasr->users) { + + kfree(elbasr->tx_buffer); + elbasr->tx_buffer = NULL; + + kfree(elbasr->rx_buffer); + elbasr->rx_buffer = NULL; + + if (dofree) + kfree(elbasr); + else + elbasr->speed_hz = elbasr->spi->max_speed_hz; + } +#ifdef CONFIG_SPI_SLAVE + if (!dofree) + spi_slave_abort(elbasr->spi); +#endif + mutex_unlock(&device_list_lock); + + return 0; +} + +static const struct file_operations elbasr_spi_fops = { + .owner = THIS_MODULE, + .write = elbasr_spi_write, + .read = elbasr_spi_read, + .unlocked_ioctl = elbasr_spi_ioctl, + .compat_ioctl = elbasr_spi_compat_ioctl, + .open = elbasr_spi_open, + .release = elbasr_spi_release, + .llseek = no_llseek, +}; + +static bool +elbasr_reg_readable(struct device *dev, unsigned int reg) +{ + return reg <= ELBASR_MAX_REG; +} + +static bool +elbasr_reg_writeable(struct device *dev, unsigned int reg) +{ + return reg <= ELBASR_MAX_REG; +} + +static int +elbasr_regs_read(void *ctx, u32 reg, u32 *val) +{ + struct elbasr_data *elbasr = dev_get_drvdata(ctx); + struct spi_message m; + struct spi_transfer t[2] = { { 0 } }; + int ret; + u8 txbuf[3]; + u8 rxbuf[1]; + + spi_message_init(&m); + + txbuf[0] = ELBASR_SPI_CMD_REGRD; + txbuf[1] = reg; + txbuf[2] = 0x0; + t[0].tx_buf = (u8 *)txbuf; + t[0].len = 3; + + rxbuf[0] = 0x0; + t[1].rx_buf = rxbuf; + t[1].len = 1; + + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + + ret = elbasr_spi_sync(elbasr, &m); + if (ret == 4) { + // 3 Tx + 1 Rx = 4 + *val = rxbuf[0]; + return 0; + } + return -EIO; +} + +static int +elbasr_regs_write(void *ctx, u32 reg, u32 val) +{ + struct elbasr_data *elbasr = dev_get_drvdata(ctx); + struct spi_message m; + struct spi_transfer t[1] = { { 0 } }; + u8 txbuf[4]; + + spi_message_init(&m); + txbuf[0] = ELBASR_SPI_CMD_REGWR; + txbuf[1] = reg; + txbuf[2] = val; + txbuf[3] = 0; + + t[0].tx_buf = txbuf; + t[0].len = 4; + + spi_message_add_tail(&t[0], &m); + + return elbasr_spi_sync(elbasr, &m); +} + +static const struct regmap_config pensando_elbasr_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_NONE, + .readable_reg = elbasr_reg_readable, + .writeable_reg = elbasr_reg_writeable, + .reg_read = elbasr_regs_read, + .reg_write = elbasr_regs_write, + .max_register = ELBASR_MAX_REG +}; + +/* + * Setup Elba SPI access to System Resource Chip registers on CS0 + */ +static int +elbasr_regs_setup(struct spi_device *spi, struct elbasr_data *elbasr) +{ + int ret; + + spi->bits_per_word = 8; + spi_setup(spi); + elbasr->elbasr_regs = devm_regmap_init(&spi->dev, NULL, spi, + &pensando_elbasr_regmap_config); + if (IS_ERR(elbasr->elbasr_regs)) { + ret = PTR_ERR(elbasr->elbasr_regs); + dev_err(&spi->dev, "Failed to allocate register map: %d\n", ret); + return ret; + } + + ret = devm_mfd_add_devices(&spi->dev, PLATFORM_DEVID_NONE, + pensando_elbasr_subdev_info, + ARRAY_SIZE(pensando_elbasr_subdev_info), + NULL, 0, NULL); + if (ret) + dev_err(&spi->dev, "Failed to register sub-devices: %d\n", ret); + + return ret; +} + +static int elbasr_spi_probe(struct spi_device *spi) +{ + struct elbasr_data *elbasr; + unsigned long minor; + int status; + + if (spi->chip_select == 0) { + status = alloc_chrdev_region(&elbasr_devt, 0, ELBASR_MAX_DEVS, + "elbasr"); + if (status < 0) + return status; + + elbasr_class = class_create(THIS_MODULE, "elbasr"); + if (IS_ERR(elbasr_class)) { + unregister_chrdev(MAJOR(elbasr_devt), "elbasr"); + return PTR_ERR(elbasr_class); + } + } + + /* Allocate driver data */ + elbasr = kzalloc(sizeof(*elbasr), GFP_KERNEL); + if (!elbasr) + return -ENOMEM; + + /* Initialize the driver data */ + elbasr->spi = spi; + elbasr->speed_hz = spi->max_speed_hz; + spin_lock_init(&elbasr->spi_lock); + mutex_init(&elbasr->buf_lock); + + INIT_LIST_HEAD(&elbasr->device_entry); + + mutex_lock(&device_list_lock); + minor = find_first_zero_bit(minors, ELBASR_MAX_DEVS); + if (minor < ELBASR_MAX_DEVS) { + struct device *dev; + + elbasr->devt = MKDEV(MAJOR(elbasr_devt), minor); + dev = device_create(elbasr_class, + &spi->dev, + elbasr->devt, + elbasr, + "pensr%d.%d", + spi->master->bus_num, + spi->chip_select); + + status = PTR_ERR_OR_ZERO(dev); + } else { + dev_dbg(&spi->dev, "no minor number available\n"); + status = -ENODEV; + goto minor_failed; + } + + set_bit(minor, minors); + list_add(&elbasr->device_entry, &device_list); + dev_dbg(&spi->dev, + "created device for major %d, minor %lu\n", + MAJOR(elbasr_devt), minor); + mutex_unlock(&device_list_lock); + + /* Create cdev */ + elbasr->cdev = cdev_alloc(); + if (!elbasr->cdev) { + dev_err(elbasr->dev, "allocation of cdev failed"); + status = -ENOMEM; + goto cdev_failed; + } + elbasr->cdev->owner = THIS_MODULE; + cdev_init(elbasr->cdev, &elbasr_spi_fops); + + status = cdev_add(elbasr->cdev, elbasr->devt, 1); + if (status) { + dev_err(elbasr->dev, "register of cdev failed"); + goto cdev_delete; + } + spi_set_drvdata(spi, elbasr); + + /* Add Elba reset driver sub-device */ + if (spi->chip_select == 0) + elbasr_regs_setup(spi, elbasr); + + return 0; + +cdev_delete: + if (spi->chip_select == 0) + cdev_del(elbasr->cdev); +cdev_failed: + if (spi->chip_select == 0) + device_destroy(elbasr_class, elbasr->devt); +minor_failed: + kfree(elbasr); + + return status; +} + +static const struct of_device_id elbasr_spi_of_match[] = { + { .compatible = "amd,pensando-elbasr" }, + { /* sentinel */ }, +}; + +static struct spi_driver elbasr_spi_driver = { + .probe = elbasr_spi_probe, + .driver = { + .name = "elbasr", + .of_match_table = of_match_ptr(elbasr_spi_of_match), + }, +}; +builtin_driver(elbasr_spi_driver, spi_register_driver) diff --git a/include/linux/mfd/pensando-elbasr.h b/include/linux/mfd/pensando-elbasr.h new file mode 100644 index 000000000000..2b794218dca5 --- /dev/null +++ b/include/linux/mfd/pensando-elbasr.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2022 AMD Pensando + * + * Declarations for AMD Pensando Elba System Resource Chip + */ + +#ifndef __MFD_AMD_PENSANDO_ELBA_H +#define __MFD_AMD_PENSANDO_ELBA_H + +#include +#include + +#define ELBASR_REVISION_REG 0x00 +#define ELBASR_CTRL_REG 0x01 +#define ELBASR_QSFP_CTRL_REG 0x02 +#define ELBASR_INTERRUPT_ENABLE_REG 0x03 +#define ELBASR_INTERRUPT_STATUS_REG 0x04 +#define ELBASR_QSFP_LED_REG 0x05 +#define ELBASR_QSFP_LED_FREQUENCY_REG 0x0F +#define ELBASR_CTRL0_REG 0x10 +#define ELBASR_CTRL1_REG 0x11 +#define ELBASR_CTRL2_REG 0x12 +#define ELBASR_SYSTEM_LED_REG 0x15 +#define ELBASR_CORE_TEMP_REG 0x16 +#define ELBASR_HBM_TEMP_REG 0x17 +#define ELBASR_BOARD_TEMP_REG 0x18 +#define ELBASR_QSFP_PORT1_TEMP_REG 0x19 +#define ELBASR_QSFP_PORT2_TEMP_REG 0x1a +#define ELBASR_HBM_WARNING_TEMP_REG 0x1b +#define ELBASR_HBM_CRITICAL_TEMP_REG 0x1c +#define ELBASR_HBM_FATAL_TEMP_REG 0x1d +#define ELBASR_ROT_REG0_CNTL_REG 0x23 +#define ELBASR_PUF_ERROR_LIMITS_REG 0x29 +#define ELBASR_PUF_ERROR_COUNT_REG 0x2a +#define ELBASR_QSFP_PORT1_ALARM_TEMP_REG 0x34 +#define ELBASR_QSFP_PORT1_WARNING_TEMP_REG 0x35 +#define ELBASR_QSFP_PORT2_ALARM_TEMP_REG 0x36 +#define ELBASR_QSFP_PORT2_WARNING_TEMP_REG 0x37 +#define ELBASR_SYSTEM_HEALTH0_REG 0x38 +#define ELBASR_SYSTEM_HEALTH1_REG 0x39 +#define ELBASR_MAJOR_FW_VER_REG 0x3a +#define ELBASR_MINOR_FW_VER_REG 0x3b +#define ELBASR_MAINTANENCE_FW_VER_REG 0x3c +#define ELBASR_PIPELINE_FW_REG 0x3d +#define ELBASR_QSFP_PRESENT_REG 0x40 +#define ELBASR_OCP_SLOTID_REG 0x42 +#define ELBASR_OCP_SC_DATA0_REG 0x43 +#define ELBASR_OCP_SC_DATA1_REG 0x44 +#define ELBASR_ID 0x80 + +#define ELBASR_MAX_REG 0x80 +#define ELBASR_NR_RESETS 1 + +/* + * Pensando Elba System Resource MFD device private data structure + */ +struct elbasr_data { + dev_t devt; + int minor; + struct device *dev; + struct cdev *cdev; + struct spi_device *spi; + struct list_head device_entry; + spinlock_t spi_lock; + + /* TX/RX buffers are NULL unless this device is open (users > 0) */ + struct mutex buf_lock; + unsigned int users; + u8 *tx_buffer; + u8 *rx_buffer; + u32 speed_hz; + + /* System Resource Chip CS0 register access */ + struct regmap *elbasr_regs; +}; + +#endif /* __MFD_AMD_PENSANDO_ELBA_H */ From patchwork Mon Jun 13 19:56:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 12880006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CB0CC433EF for ; Mon, 13 Jun 2022 20:00:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=z9rpLDqtPFAI3sM5SnmIpujYwGHzgpI0r9WTahFAwNY=; b=3EWn5Oo+ocep5/ xVE+hzJ23D+LV6nBQ5oZwm+ITry11g2DXrLD0qRbYEgoprkA2BUySkLyMXzNXMzyvwxLBqyiuLhEl P7kRH2QSsTVUNy89xfgxjopKzllrC/kE9llALPuNgk7wXHPEL3wmCs0KxQv+nGAtK0TpZNPuikIqr jSFyVvxcP5x8cr7BdNSOJUuvqygbhXeDPSolLaLXqVc845MKupY2d9ZcDsRtc0R8gKcQiCTcBubbz 09ix8VVG3DEcRWjqCKlWAdbw0QiOR44j96qjJ5xFEA9q25zzGYC10EEf8ZKP7bk2qXcD4rBR/RAVJ B26dZb36T6Dcp2hOP8Tw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qDh-005RW9-BY; Mon, 13 Jun 2022 19:59:30 +0000 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0qCA-005QM1-GN for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2022 19:57:56 +0000 Received: by mail-pg1-x532.google.com with SMTP id 184so6469631pga.12 for ; Mon, 13 Jun 2022 12:57:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G5AngU4fQLL9tjwfd3M8P7vnWfa9NLIJ0sasw1HKwk0=; b=mu1MQUUbKSIWTjXFuH9p5fRtMkj/uh3ZnxEfSrme86jAyFfjIy8octcKZ3zNAX4x9c wUnkb7Pm31XhRwRRyE6LbmkkeaxcoeBZLDkixXYqfV794DjWNfiz/mGlQTvWSqTEWWtv GqC866XldQ6zuRlUQUd+E5wwXlgg7da2ICjTbSTrIUNFOls4Cp/NjO1QggHYfg77Vqmv IOItahUEcwJuZw6gpYbkDj2XO+1nM5uvTzeN/Dupw9QpUJ/TRJOBFLDZ2IoP3JOosR4g GHdndKKc4nnSC2cdovhjFcFaV5s1rSJBMKihXZMEouUOTHk2CEILhcxWgL9eChYN+kBi bBZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G5AngU4fQLL9tjwfd3M8P7vnWfa9NLIJ0sasw1HKwk0=; b=WR57/KdbBDxYMQS6y2jybybntdYuTkWtqJ6OzAq9hOXgQkkASaz1H5CRZHTcyoJgyu OzJcicykzpfkm5WGlIX9xN+1pKiZPz6qMvNDCa46PCXrhZNmnEdWrZOq9gEXYDhdrHSd xGSK5oXkx4MUYq4ZcemMy42NfEzZ82rHVeCZywpxK51W43Nq4H/dOaS6n1LfYc5WTGAL bUZVFbyPUiCR+AnNSYlUAEe+soEJ3C8aFbEZsLdDoB1t6lgtpSGAi1zm0n5s0wCoAR3O osURsz9/FojPHErAoYeyoGK/6CoWlHXRkzZlpfvjVeyyym1d0SuzakF80wqNsIXtRqTy No0Q== X-Gm-Message-State: AOAM530pxpDrg77I9dQ628WCXdYqobP/Z3qv44jAIVYVNkBOft22+ZXt PvngmqxcTEzARDxQmSVPckt5SIf/bj2sUw== X-Google-Smtp-Source: ABdhPJxT9PVmJkPQk+jDaeQ8grX7yokwcmvdH5gzlVI7dBpN2UU5iRmzY3Wcu+fC+042xx6yhf2Z3A== X-Received: by 2002:a63:2cd7:0:b0:3fe:1c0a:75ce with SMTP id s206-20020a632cd7000000b003fe1c0a75cemr1128278pgs.602.1655150274127; Mon, 13 Jun 2022 12:57:54 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id q21-20020a170902edd500b0016797c33b6csm5509357plk.116.2022.06.13.12.57.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 12:57:53 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 15/15] reset: elbasr: Add AMD Pensando Elba SR Reset Controller Date: Mon, 13 Jun 2022 12:56:58 -0700 Message-Id: <20220613195658.5607-16-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220613195658.5607-1-brad@pensando.io> References: <20220613195658.5607-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220613_125754_585792_ACBF1353 X-CRM114-Status: GOOD ( 21.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Brad Larson This patch adds the reset controller functionality for the AMD Pensando Elba System Resource Chip. Signed-off-by: Brad Larson --- drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-elbasr.c | 94 +++++++++++++++++++ .../reset/amd,pensando-elba-reset.h | 11 +++ 4 files changed, 115 insertions(+) create mode 100644 drivers/reset/reset-elbasr.c create mode 100644 include/dt-bindings/reset/amd,pensando-elba-reset.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 93c8d07ee328..13f5a8ca0f03 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -66,6 +66,15 @@ config RESET_BRCMSTB_RESCAL This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on BCM7216. +config RESET_ELBASR + tristate "Pensando Elba System Resource reset controller" + depends on MFD_PENSANDO_ELBASR || COMPILE_TEST + help + This option enables support for the external reset functions + on the Pensando Elba System Resource Chip. Reset control + of peripherals is accessed over SPI to the system resource + chip device registers using CS0. + config RESET_HSDK bool "Synopsys HSDK Reset Driver" depends on HAS_IOMEM diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index a80a9c4008a7..c0fe12b9950e 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o +obj-$(CONFIG_RESET_ELBASR) += reset-elbasr.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o diff --git a/drivers/reset/reset-elbasr.c b/drivers/reset/reset-elbasr.c new file mode 100644 index 000000000000..6e429cb11466 --- /dev/null +++ b/drivers/reset/reset-elbasr.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 AMD Pensando + */ + +#include +#include +#include +#include +#include +#include + +#include + +struct elbasr_reset { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +static inline struct elbasr_reset *to_elbasr_rst(struct reset_controller_dev *rc) +{ + return container_of(rc, struct elbasr_reset, rcdev); +} + +static inline int elbasr_reset_shift(unsigned long id) +{ + switch (id) { + case EMMC_HW_RESET: + return 6; + default: + return -EINVAL; + } +} + +static int elbasr_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct elbasr_reset *elbar = to_elbasr_rst(rcdev); + u32 mask = 1 << elbasr_reset_shift(id); + + return regmap_update_bits(elbar->regmap, ELBASR_CTRL0_REG, mask, mask); +} + +static int elbasr_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct elbasr_reset *elbar = to_elbasr_rst(rcdev); + u32 mask = 1 << elbasr_reset_shift(id); + + return regmap_update_bits(elbar->regmap, ELBASR_CTRL0_REG, mask, 0); +} + +static const struct reset_control_ops elbasr_reset_ops = { + .assert = elbasr_reset_assert, + .deassert = elbasr_reset_deassert, +}; + +static int elbasr_reset_probe(struct platform_device *pdev) +{ + struct elbasr_data *elbasr = dev_get_drvdata(pdev->dev.parent); + struct elbasr_reset *elbar; + int ret; + + elbar = devm_kzalloc(&pdev->dev, sizeof(struct elbasr_reset), + GFP_KERNEL); + if (!elbar) + return -ENOMEM; + + elbar->rcdev.owner = THIS_MODULE; + elbar->rcdev.nr_resets = ELBASR_NR_RESETS; + elbar->rcdev.ops = &elbasr_reset_ops; + elbar->rcdev.of_node = pdev->dev.of_node; + elbar->regmap = elbasr->elbasr_regs; + + platform_set_drvdata(pdev, elbar); + + ret = devm_reset_controller_register(&pdev->dev, &elbar->rcdev); + + return ret; +} + +static const struct of_device_id elba_reset_dt_match[] = { + { .compatible = "amd,pensando-elbasr-reset", }, + { /* sentinel */ }, +}; + +static struct platform_driver elbasr_reset_driver = { + .probe = elbasr_reset_probe, + .driver = { + .name = "pensando_elbasr_reset", + .of_match_table = elba_reset_dt_match, + }, +}; +builtin_platform_driver(elbasr_reset_driver); diff --git a/include/dt-bindings/reset/amd,pensando-elba-reset.h b/include/dt-bindings/reset/amd,pensando-elba-reset.h new file mode 100644 index 000000000000..68d69a98e750 --- /dev/null +++ b/include/dt-bindings/reset/amd,pensando-elba-reset.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2022, AMD Pensando + */ + +#ifndef _DT_BINDINGS_RESET_AMD_PENSANDO_ELBA_RESET_H +#define _DT_BINDINGS_RESET_AMD_PENSANDO_ELBA_RESET_H + +#define EMMC_HW_RESET 0 + +#endif