From patchwork Tue Jun 14 12:29:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "yekai (A)" X-Patchwork-Id: 12881142 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 095FACCA47A for ; Tue, 14 Jun 2022 12:40:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245236AbiFNMj4 (ORCPT ); Tue, 14 Jun 2022 08:39:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357749AbiFNMjW (ORCPT ); Tue, 14 Jun 2022 08:39:22 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83A614B411; Tue, 14 Jun 2022 05:37:01 -0700 (PDT) Received: from dggpeml500025.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4LMnvR6TFFzjY3m; Tue, 14 Jun 2022 20:34:59 +0800 (CST) Received: from dggpeml100012.china.huawei.com (7.185.36.121) by dggpeml500025.china.huawei.com (7.185.36.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 14 Jun 2022 20:36:04 +0800 Received: from huawei.com (10.67.165.24) by dggpeml100012.china.huawei.com (7.185.36.121) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 14 Jun 2022 20:36:03 +0800 From: Kai Ye To: , CC: , , , , , , Subject: [PATCH 1/3] uacce: supports device isolation feature Date: Tue, 14 Jun 2022 20:29:41 +0800 Message-ID: <20220614122943.1406-5-yekai13@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220614122943.1406-1-yekai13@huawei.com> References: <20220614122943.1406-1-yekai13@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml100012.china.huawei.com (7.185.36.121) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org UACCE add the hardware error isolation API. Users can configure the error frequency threshold by this vfs node. This API interface certainly supports the configuration of user protocol strategy. Then parse it inside the device driver. UACCE only reports the device isolate state. When the error frequency is exceeded, the device will be isolated. The isolation strategy should be defined in each driver module. Signed-off-by: Kai Ye Reviewed-by: Zhou Wang --- drivers/misc/uacce/uacce.c | 51 ++++++++++++++++++++++++++++++++++++++ include/linux/uacce.h | 15 ++++++++++- 2 files changed, 65 insertions(+), 1 deletion(-) diff --git a/drivers/misc/uacce/uacce.c b/drivers/misc/uacce/uacce.c index b6219c6bfb48..4d9d9aeb145a 100644 --- a/drivers/misc/uacce/uacce.c +++ b/drivers/misc/uacce/uacce.c @@ -12,6 +12,20 @@ static dev_t uacce_devt; static DEFINE_MUTEX(uacce_mutex); static DEFINE_XARRAY_ALLOC(uacce_xa); +static int cdev_get(struct device *dev, void *data) +{ + struct uacce_device *uacce; + struct device **t_dev = data; + + uacce = container_of(dev, struct uacce_device, dev); + if (uacce->parent == *t_dev) { + *t_dev = dev; + return 1; + } + + return 0; +} + static int uacce_start_queue(struct uacce_queue *q) { int ret = 0; @@ -346,12 +360,47 @@ static ssize_t region_dus_size_show(struct device *dev, uacce->qf_pg_num[UACCE_QFRT_DUS] << PAGE_SHIFT); } +static ssize_t isolate_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct uacce_device *uacce = to_uacce_device(dev); + + return sysfs_emit(buf, "%d\n", uacce->ops->get_isolate_state(uacce)); +} + +static ssize_t isolate_strategy_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct uacce_device *uacce = to_uacce_device(dev); + + return sysfs_emit(buf, "%s\n", uacce->isolate_strategy); +} + +static ssize_t isolate_strategy_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct uacce_device *uacce = to_uacce_device(dev); + int ret; + + if (!buf || sizeof(buf) > UACCE_MAX_ISOLATE_STRATEGY_LEN) + return -EINVAL; + + memcpy(uacce->isolate_strategy, buf, strlen(buf)); + + ret = uacce->ops->isolate_strategy_write(uacce, buf); + + return ret > 0 ? count : ret; +} + static DEVICE_ATTR_RO(api); static DEVICE_ATTR_RO(flags); static DEVICE_ATTR_RO(available_instances); static DEVICE_ATTR_RO(algorithms); static DEVICE_ATTR_RO(region_mmio_size); static DEVICE_ATTR_RO(region_dus_size); +static DEVICE_ATTR_RO(isolate); +static DEVICE_ATTR_RW(isolate_strategy); static struct attribute *uacce_dev_attrs[] = { &dev_attr_api.attr, @@ -360,6 +409,8 @@ static struct attribute *uacce_dev_attrs[] = { &dev_attr_algorithms.attr, &dev_attr_region_mmio_size.attr, &dev_attr_region_dus_size.attr, + &dev_attr_isolate.attr, + &dev_attr_isolate_strategy.attr, NULL, }; diff --git a/include/linux/uacce.h b/include/linux/uacce.h index 48e319f40275..e00a43a07e4b 100644 --- a/include/linux/uacce.h +++ b/include/linux/uacce.h @@ -8,6 +8,7 @@ #define UACCE_NAME "uacce" #define UACCE_MAX_REGION 2 #define UACCE_MAX_NAME_SIZE 64 +#define UACCE_MAX_ISOLATE_STRATEGY_LEN 256 struct uacce_queue; struct uacce_device; @@ -30,6 +31,8 @@ struct uacce_qfile_region { * @is_q_updated: check whether the task is finished * @mmap: mmap addresses of queue to user space * @ioctl: ioctl for user space users of the queue + * @get_isolate_state: get the device state after set the isolate strategy + * @isolate_strategy_store: stored the isolate strategy to the device */ struct uacce_ops { int (*get_available_instances)(struct uacce_device *uacce); @@ -43,6 +46,8 @@ struct uacce_ops { struct uacce_qfile_region *qfr); long (*ioctl)(struct uacce_queue *q, unsigned int cmd, unsigned long arg); + enum uacce_dev_state (*get_isolate_state)(struct uacce_device *uacce); + int (*isolate_strategy_write)(struct uacce_device *uacce, const char *buf); }; /** @@ -57,6 +62,12 @@ struct uacce_interface { const struct uacce_ops *ops; }; +enum uacce_dev_state { + UACCE_DEV_ERR = -1, + UACCE_DEV_NORMAL, + UACCE_DEV_ISOLATE, +}; + enum uacce_q_state { UACCE_Q_ZOMBIE = 0, UACCE_Q_INIT, @@ -99,6 +110,7 @@ struct uacce_queue { * @dev: dev of the uacce * @priv: private pointer of the uacce * @queues: list of queues + * @ref: reference of the uacce * @queues_lock: lock for queues list * @inode: core vfs */ @@ -117,6 +129,7 @@ struct uacce_device { struct list_head queues; struct mutex queues_lock; struct inode *inode; + char isolate_strategy[UACCE_MAX_ISOLATE_STRATEGY_LEN]; }; #if IS_ENABLED(CONFIG_UACCE) @@ -125,7 +138,7 @@ struct uacce_device *uacce_alloc(struct device *parent, struct uacce_interface *interface); int uacce_register(struct uacce_device *uacce); void uacce_remove(struct uacce_device *uacce); - +struct uacce_device *dev_to_uacce(struct device *dev); #else /* CONFIG_UACCE */ static inline From patchwork Tue Jun 14 12:29:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "yekai (A)" X-Patchwork-Id: 12881151 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6058EC43334 for ; Tue, 14 Jun 2022 12:53:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237851AbiFNMxj (ORCPT ); Tue, 14 Jun 2022 08:53:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235039AbiFNMxi (ORCPT ); Tue, 14 Jun 2022 08:53:38 -0400 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE94D3BFBB; Tue, 14 Jun 2022 05:53:36 -0700 (PDT) Received: from dggpeml500020.china.huawei.com (unknown [172.30.72.54]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4LMntR42tMz1K9t1; Tue, 14 Jun 2022 20:34:07 +0800 (CST) Received: from dggpeml100012.china.huawei.com (7.185.36.121) by dggpeml500020.china.huawei.com (7.185.36.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 14 Jun 2022 20:36:04 +0800 Received: from huawei.com (10.67.165.24) by dggpeml100012.china.huawei.com (7.185.36.121) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 14 Jun 2022 20:36:04 +0800 From: Kai Ye To: , CC: , , , , , , Subject: [PATCH 2/3] Documentation: add a isolation strategy vfs node for uacce Date: Tue, 14 Jun 2022 20:29:42 +0800 Message-ID: <20220614122943.1406-6-yekai13@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220614122943.1406-1-yekai13@huawei.com> References: <20220614122943.1406-1-yekai13@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml100012.china.huawei.com (7.185.36.121) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Update documentation describing DebugFS that could help to configure hard error frequency for users in th user space. Signed-off-by: Kai Ye --- Documentation/ABI/testing/sysfs-driver-uacce | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-driver-uacce b/Documentation/ABI/testing/sysfs-driver-uacce index 08f2591138af..0c4226364182 100644 --- a/Documentation/ABI/testing/sysfs-driver-uacce +++ b/Documentation/ABI/testing/sysfs-driver-uacce @@ -19,6 +19,23 @@ Contact: linux-accelerators@lists.ozlabs.org Description: Available instances left of the device Return -ENODEV if uacce_ops get_available_instances is not provided +What: /sys/class/uacce//isolate_strategy +Date: Jun 2022 +KernelVersion: 5.19 +Contact: linux-accelerators@lists.ozlabs.org +Description: A vfs node that used to configures the hardware + error frequency. This frequency is abstract. Like once an hour + or once a day. The specific isolation strategy can be defined in + each driver module. + +What: /sys/class/uacce//isolate +Date: Jun 2022 +KernelVersion: 5.19 +Contact: linux-accelerators@lists.ozlabs.org +Description: A vfs node that show the device isolated state. The value 0 + means that the device is working. The value 1 means that the + device has been isolated. + What: /sys/class/uacce//algorithms Date: Feb 2020 KernelVersion: 5.7 From patchwork Tue Jun 14 12:29:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "yekai (A)" X-Patchwork-Id: 12881141 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 026F4C43334 for ; Tue, 14 Jun 2022 12:39:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243448AbiFNMjd (ORCPT ); Tue, 14 Jun 2022 08:39:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357517AbiFNMjK (ORCPT ); Tue, 14 Jun 2022 08:39:10 -0400 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD8B74F9C8; Tue, 14 Jun 2022 05:36:40 -0700 (PDT) Received: from dggpeml500026.china.huawei.com (unknown [172.30.72.56]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4LMnty40c5zjXdC; Tue, 14 Jun 2022 20:34:34 +0800 (CST) Received: from dggpeml100012.china.huawei.com (7.185.36.121) by dggpeml500026.china.huawei.com (7.185.36.106) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 14 Jun 2022 20:36:03 +0800 Received: from huawei.com (10.67.165.24) by dggpeml100012.china.huawei.com (7.185.36.121) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 14 Jun 2022 20:36:03 +0800 From: Kai Ye To: , CC: , , , , , , Subject: [PATCH v2 3/3] crypto: hisilicon/qm - defining the device isolation strategy Date: Tue, 14 Jun 2022 20:29:40 +0800 Message-ID: <20220614122943.1406-4-yekai13@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220614122943.1406-1-yekai13@huawei.com> References: <20220614122943.1406-1-yekai13@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml100012.china.huawei.com (7.185.36.121) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Define the device isolation strategy by the device driver. if the AER error frequency exceeds the value of setting for a certain period of time, The device will not be available in user space. The VF device use the PF device isolation strategy. All the hardware errors are processed by PF driver. Signed-off-by: Kai Ye --- drivers/crypto/hisilicon/qm.c | 157 +++++++++++++++++++++++++++++++--- include/linux/hisi_acc_qm.h | 9 ++ 2 files changed, 152 insertions(+), 14 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index ad83c194d664..47c41fa52693 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -417,6 +416,16 @@ struct hisi_qm_resource { struct list_head list; }; +/** + * struct qm_hw_err - structure of describes the device err + * @list: hardware error list + * @tick_stamp: timestamp when the error occurred + */ +struct qm_hw_err { + struct list_head list; + unsigned long long tick_stamp; +}; + struct hisi_qm_hw_ops { int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number); void (*qm_db)(struct hisi_qm *qm, u16 qn, @@ -3278,6 +3287,7 @@ static int hisi_qm_uacce_get_queue(struct uacce_device *uacce, qp->event_cb = qm_qp_event_notifier; qp->pasid = arg; qp->is_in_kernel = false; + atomic_inc(&qm->uacce_ref); return 0; } @@ -3285,7 +3295,9 @@ static int hisi_qm_uacce_get_queue(struct uacce_device *uacce, static void hisi_qm_uacce_put_queue(struct uacce_queue *q) { struct hisi_qp *qp = q->priv; + struct hisi_qm *qm = qp->qm; + atomic_dec(&qm->uacce_ref); hisi_qm_cache_wb(qp->qm); hisi_qm_release_qp(qp); } @@ -3410,6 +3422,102 @@ static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd, return 0; } +/** + * qm_hw_err_isolate() - Try to isolate the uacce device with its VFs + * @qm: The qm which we want to configure. + * + * according to user's configuration of isolation strategy. Warning: this + * API should be called while there is no user on the device, or the users + * on this device are suspended by slot resetting preparation of PCI AER. + */ +static int qm_hw_err_isolate(struct hisi_qm *qm) +{ + struct qm_hw_err *err, *tmp, *hw_err; + struct qm_err_isolate *isolate; + u32 count = 0; + + isolate = &qm->isolate_data; + +#define SECONDS_PER_HOUR 3600 + + /* All the hw errs are processed by PF driver */ + if (qm->uacce->is_vf || atomic_read(&isolate->is_isolate) || + !isolate->hw_err_isolate_hz) + return 0; + + hw_err = kzalloc(sizeof(*hw_err), GFP_ATOMIC); + if (!hw_err) + return -ENOMEM; + hw_err->tick_stamp = jiffies; + list_for_each_entry_safe(err, tmp, &qm->uacce_hw_errs, list) { + if ((hw_err->tick_stamp - err->tick_stamp) / HZ > + SECONDS_PER_HOUR) { + list_del(&err->list); + kfree(err); + } else { + count++; + } + } + list_add(&hw_err->list, &qm->uacce_hw_errs); + + if (count >= isolate->hw_err_isolate_hz) + atomic_set(&isolate->is_isolate, 1); + + return 0; +} + +static void qm_hw_err_destroy(struct hisi_qm *qm) +{ + struct qm_hw_err *err, *tmp; + + list_for_each_entry_safe(err, tmp, &qm->uacce_hw_errs, list) { + list_del(&err->list); + kfree(err); + } +} + +static enum uacce_dev_state hisi_qm_get_isolate_state(struct uacce_device *uacce) +{ + struct hisi_qm *qm = uacce->priv; + struct hisi_qm *pf_qm; + + if (uacce->is_vf) { + pf_qm = pci_get_drvdata(pci_physfn(qm->pdev)); + qm->isolate_data.is_isolate = pf_qm->isolate_data.is_isolate; + } + + return atomic_read(&qm->isolate_data.is_isolate) ? + UACCE_DEV_ISOLATE : UACCE_DEV_NORMAL; +} + +static int hisi_qm_isolate_strategy_write(struct uacce_device *uacce, + const char *buf) +{ + struct hisi_qm *qm = uacce->priv; + unsigned long val = 0; + +#define MAX_ISOLATE_STRATEGY 65535 + + if (atomic_read(&qm->uacce_ref)) + return -EBUSY; + + /* must be set by PF */ + if (atomic_read(&qm->isolate_data.is_isolate) || uacce->is_vf) + return -EINVAL; + + if (kstrtoul(buf, 0, &val) < 0) + return -EINVAL; + + if (val > MAX_ISOLATE_STRATEGY) + return -EINVAL; + + qm->isolate_data.hw_err_isolate_hz = val; + dev_info(&qm->pdev->dev, + "the value of isolate_strategy is set to %lu.\n", val); + + return 0; +} + static const struct uacce_ops uacce_qm_ops = { .get_available_instances = hisi_qm_get_available_instances, .get_queue = hisi_qm_uacce_get_queue, @@ -3418,9 +3526,22 @@ static const struct uacce_ops uacce_qm_ops = { .stop_queue = hisi_qm_uacce_stop_queue, .mmap = hisi_qm_uacce_mmap, .ioctl = hisi_qm_uacce_ioctl, + .get_isolate_state = hisi_qm_get_isolate_state, .is_q_updated = hisi_qm_is_q_updated, + .isolate_strategy_write = hisi_qm_isolate_strategy_write, }; +static void qm_remove_uacce(struct hisi_qm *qm) +{ + struct uacce_device *uacce = qm->uacce; + + if (qm->use_sva) { + qm_hw_err_destroy(qm); + uacce_remove(uacce); + qm->uacce = NULL; + } +} + static int qm_alloc_uacce(struct hisi_qm *qm) { struct pci_dev *pdev = qm->pdev; @@ -3433,6 +3554,7 @@ static int qm_alloc_uacce(struct hisi_qm *qm) }; int ret; + INIT_LIST_HEAD(&qm->uacce_hw_errs); ret = strscpy(interface.name, dev_driver_string(&pdev->dev), sizeof(interface.name)); if (ret < 0) @@ -3446,8 +3568,7 @@ static int qm_alloc_uacce(struct hisi_qm *qm) qm->use_sva = true; } else { /* only consider sva case */ - uacce_remove(uacce); - qm->uacce = NULL; + qm_remove_uacce(qm); return -EINVAL; } @@ -5109,6 +5230,12 @@ static int qm_controller_reset_prepare(struct hisi_qm *qm) return ret; } + if (qm->use_sva) { + ret = qm_hw_err_isolate(qm); + if (ret) + pci_err(pdev, "failed to isolate hw err!\n"); + } + ret = qm_wait_vf_prepare_finish(qm); if (ret) pci_err(pdev, "failed to stop by vfs in soft reset!\n"); @@ -5436,19 +5563,24 @@ static int qm_controller_reset(struct hisi_qm *qm) ret = qm_soft_reset(qm); if (ret) { pci_err(pdev, "Controller reset failed (%d)\n", ret); - qm_reset_bit_clear(qm); - return ret; + goto err_reset; } ret = qm_controller_reset_done(qm); - if (ret) { - qm_reset_bit_clear(qm); - return ret; - } + if (ret) + goto err_reset; pci_info(pdev, "Controller reset complete\n"); - return 0; + +err_reset: + pci_err(pdev, "Controller reset failed (%d)\n", ret); + qm_reset_bit_clear(qm); + + /* if resetting fails, isolate the device */ + if (qm->use_sva && !qm->uacce->is_vf) + atomic_set(&qm->isolate_data.is_isolate, 1); + return ret; } /** @@ -6246,10 +6378,7 @@ int hisi_qm_init(struct hisi_qm *qm) err_free_qm_memory: hisi_qm_memory_uninit(qm); err_alloc_uacce: - if (qm->use_sva) { - uacce_remove(qm->uacce); - qm->uacce = NULL; - } + qm_remove_uacce(qm); err_irq_register: qm_irq_unregister(qm); err_pci_init: diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h index 116e8bd68c99..c17fd6de8551 100644 --- a/include/linux/hisi_acc_qm.h +++ b/include/linux/hisi_acc_qm.h @@ -8,6 +8,7 @@ #include #include #include +#include #define QM_QNUM_V1 4096 #define QM_QNUM_V2 1024 @@ -271,6 +272,11 @@ struct hisi_qm_poll_data { u16 *qp_finish_id; }; +struct qm_err_isolate { + u32 hw_err_isolate_hz; /* user cfg freq which triggers isolation */ + atomic_t is_isolate; +}; + struct hisi_qm { enum qm_hw_ver ver; enum qm_fun_type fun_type; @@ -335,6 +341,9 @@ struct hisi_qm { struct qm_shaper_factor *factor; u32 mb_qos; u32 type_rate; + struct list_head uacce_hw_errs; + atomic_t uacce_ref; /* reference of the uacce */ + struct qm_err_isolate isolate_data; }; struct hisi_qp_status {