From patchwork Wed Jun 15 13:59:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12882398 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45C33CCA47F for ; Wed, 15 Jun 2022 13:59:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 39D4210F621; Wed, 15 Jun 2022 13:59:40 +0000 (UTC) Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by gabe.freedesktop.org (Postfix) with ESMTPS id C914510F272 for ; Wed, 15 Jun 2022 13:59:38 +0000 (UTC) Received: by mail-lf1-x132.google.com with SMTP id 20so19034925lfz.8 for ; Wed, 15 Jun 2022 06:59:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=+OAoX9xa8zARnq1PmieTQqq78QxHaSY9nnSC1exfJcQ=; b=r1Kp1EfT/IMcglR2oedl5BVnI/ZlqGaUUQgE58Fl9iORFiZTb/zZZsAcen7I1kHOTl QYw3sEKJS+v/n1VlBfmWZQM06pm2vuMLqv5FLkUTgBQJMRbArgpev+sCdWp4ybE7rtHG klrJyAnqg3NzLZjgSpldafWfOHsvlOcBEow6UEHeiohk/tPLbOEUfo6bDXIfTFHrKjRm 2u+oskr6HdpYrNgOsxzWuWydZDQE8uzOJmaAROURAMRAeec7FOGkoVu9JKmYJh3Da2hv 1ZnZXRyw6e07jJ7MzLKxyL9Zw+LrzWGU/esGaH3E5V8lJR57dZ0K6TYgm23Np1SNM5Af cnTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=+OAoX9xa8zARnq1PmieTQqq78QxHaSY9nnSC1exfJcQ=; b=wUam589HHnRjqO3EHS7Eioy7CdTlCvsDlYE3z38hcKRPXT+3lphmsiLPkPF5QlpjcT fFK+ifIkXVRgfgV0ek+rFWt2/d7+tPCjnHQq03/iCm0QWZWi81o37d+nCHjJVewzTwLb kK25+tk1c9vdBtZh3ux4gWv8uzvzuk+eX6Yd8ZFYKP6jwiTdCIRXAUIn6XVNEHVCnpr9 zAFittT3PRLJZiAAuSdM0KKiMB8no08eflLIJ3x8WTtj52oGdwiZ/cM4AriqsUPth30b 7orBOMAVSCCP+dM4T3PmYhjNBsRuxynhvaTNylM72PyK2ii8oJxKlXWSmVsd5va3NIDD mJ2Q== X-Gm-Message-State: AJIora+keafwff4guBf5cNLuzlRU2z6gtBtF/wFefu9NfsXYLenWQwMI 0m7RR0tlW99WiLJCs+SJodQWwQ== X-Google-Smtp-Source: AGRyM1tv84JWj8qt4J4oF52FvEm2avqnxiVT6u4wP7riAO1GYvMdFBJsLHOyiycdrlq5lWgBSQ0Cng== X-Received: by 2002:a05:6512:2522:b0:479:a9c:42a9 with SMTP id be34-20020a056512252200b004790a9c42a9mr6107700lfb.210.1655301577020; Wed, 15 Jun 2022 06:59:37 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id z23-20020a2e8e97000000b0025530fa4edesm1694962ljk.49.2022.06.15.06.59.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 06:59:36 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Subject: [PATCH 1/5] drm/msm: less magic numbers in msm_mdss_enable Date: Wed, 15 Jun 2022 16:59:31 +0300 Message-Id: <20220615135935.87381-1-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bjorn Andersson , Stephen Boyd , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Replace magic register writes in msm_mdss_enable() with version that contains less magic and more variable names that can be traced back to the dpu_hw_catalog or the downstream dtsi files. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 80 ++++++++++++++++++++++++++++++---- 1 file changed, 72 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 0454a571adf7..b41848bfff91 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -21,6 +21,7 @@ #define HW_REV 0x0 #define HW_INTR_STATUS 0x0010 +#define UBWC_DEC_HW_VERSION 0x58 #define UBWC_STATIC 0x144 #define UBWC_CTRL_2 0x150 #define UBWC_PREDICTION_MODE 0x154 @@ -132,9 +133,63 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) return 0; } +#define UBWC_1_0 0x10000000 +#define UBWC_2_0 0x20000000 +#define UBWC_3_0 0x30000000 +#define UBWC_4_0 0x40000000 + +static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss, + u32 ubwc_static) +{ + writel_relaxed(ubwc_static, msm_mdss->mmio + UBWC_STATIC); +} + +static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss, + unsigned int ubwc_version, + u32 ubwc_swizzle, + u32 highest_bank_bit, + u32 macrotile_mode) +{ + u32 value = (ubwc_swizzle & 0x1) | + (highest_bank_bit & 0x3) << 4 | + (macrotile_mode & 0x1) << 12; + + if (ubwc_version == UBWC_3_0) + value |= BIT(10); + + if (ubwc_version == UBWC_1_0) + value |= BIT(8); + + writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); +} + +static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss, + unsigned int ubwc_version, + u32 ubwc_swizzle, + u32 ubwc_static, + u32 highest_bank_bit, + u32 macrotile_mode) +{ + u32 value = (ubwc_swizzle & 0x7) | + (ubwc_static & 0x1) << 3 | + (highest_bank_bit & 0x7) << 4 | + (macrotile_mode & 0x1) << 12; + + writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); + + if (ubwc_version == UBWC_3_0) { + writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2); + writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE); + } else { + writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); + writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); + } +} + static int msm_mdss_enable(struct msm_mdss *msm_mdss) { int ret; + u32 hw_rev; ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { @@ -149,26 +204,35 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) if (msm_mdss->is_mdp5) return 0; + hw_rev = readl_relaxed(msm_mdss->mmio + HW_REV); + dev_dbg(msm_mdss->dev, "HW_REV: 0x%x\n", hw_rev); + dev_dbg(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", + readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION)); + /* * ubwc config is part of the "mdss" region which is not accessible * from the rest of the driver. hardcode known configurations here + * + * Decoder version can be read from the UBWC_DEC_HW_VERSION reg, + * UBWC_n and the rest of params comes from hw_catalog. + * Unforunately this driver can not access hw catalog, so we have to + * hardcode them here. */ - switch (readl_relaxed(msm_mdss->mmio + HW_REV)) { + switch (hw_rev) { case DPU_HW_VER_500: case DPU_HW_VER_501: - writel_relaxed(0x420, msm_mdss->mmio + UBWC_STATIC); + msm_mdss_setup_ubwc_dec_30(msm_mdss, UBWC_3_0, 0, 2, 0); break; case DPU_HW_VER_600: - /* TODO: 0x102e for LP_DDR4 */ - writel_relaxed(0x103e, msm_mdss->mmio + UBWC_STATIC); - writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); - writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); break; case DPU_HW_VER_620: - writel_relaxed(0x1e, msm_mdss->mmio + UBWC_STATIC); + /* UBWC_2_0 */ + msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); break; case DPU_HW_VER_720: - writel_relaxed(0x101e, msm_mdss->mmio + UBWC_STATIC); + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); break; } From patchwork Wed Jun 15 13:59:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12882399 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BFA6C433EF for ; Wed, 15 Jun 2022 13:59:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 01D9E10F6AF; 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Wed, 15 Jun 2022 06:59:37 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Subject: [PATCH 2/5] drm/msm/mdss: enable optional core clock for MDP5 MDSS Date: Wed, 15 Jun 2022 16:59:32 +0300 Message-Id: <20220615135935.87381-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220615135935.87381-1-dmitry.baryshkov@linaro.org> References: <20220615135935.87381-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bjorn Andersson , Stephen Boyd , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable (optional) core (MDP_CLK) clock that allows accessing HW_REV registers during the platform init. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index b41848bfff91..f7b4628986b8 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -288,7 +288,7 @@ static int msm_mdss_reset(struct device *dev) /* * MDP5 MDSS uses at most three specified clocks. */ -#define MDP5_MDSS_NUM_CLOCKS 3 +#define MDP5_MDSS_NUM_CLOCKS 4 static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks) { struct clk_bulk_data *bulk; @@ -305,6 +305,7 @@ static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_d bulk[num_clocks++].id = "iface"; bulk[num_clocks++].id = "bus"; bulk[num_clocks++].id = "vsync"; + bulk[num_clocks++].id = "core"; /* for hw_rev access */ ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk); if (ret) From patchwork Wed Jun 15 13:59:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12882402 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED007C43334 for ; Wed, 15 Jun 2022 13:59:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 47B7C10F6B8; Wed, 15 Jun 2022 13:59:49 +0000 (UTC) Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by gabe.freedesktop.org (Postfix) with ESMTPS id C9E1D10F625 for ; Wed, 15 Jun 2022 13:59:40 +0000 (UTC) Received: by mail-lf1-x131.google.com with SMTP id y32so19065635lfa.6 for ; Wed, 15 Jun 2022 06:59:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ESJKapWNnw8tw1fCS4q6ugXslWZGCzhXQrREzvrDX9A=; b=mlHWN7WMxxt1qnpdtMUUAzh4kLmqQZlbcE3yEaIPgSq7bw+wcj2+u0KnWMG6UvXnxj SGEAmmYaINLO4Twb6oUTiKUMSkgMbQ9BY7JQvuXOK1TmirS2++Vf41hP896BGzyGt5mR 6hOPqYBYSxkQCbAdddof/6Hl/0tcIawUC1SLzEG64c8YpUzxfeq6unLEbTlT0Ciux/1H dDxSuEmptUvTIAAeCwPAtSGZJFV9fvbxzJcuW54uPsbuhoALsrup0sbiBWiGzLEIMgXv U1S7vxMgtE0Qivb7LTzSP+UdAqA08UegxZe8bweuWX67JxkoMk2DC3kX1+bJUw2w1gEK 13Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ESJKapWNnw8tw1fCS4q6ugXslWZGCzhXQrREzvrDX9A=; b=3BGNfR5EgVuIQL/VFWJTRbxk+u34PnuXMynHhS+EPRYoxL3iBaRjkoZm9hEP551Uem KouWajomL15YcbIZeeWGEYmtMupukAJykA7RHS0E+bJpSmdDM2SaXzhUSYa7C5L9pZiK aIhXFQ5mhqEZ6r4uP/KIxJoIY1180JKcUaLr1OwolQigvL4Q8Rkop7hHqu13XqhUX7P1 uC1/+yMAl/oOhevp1RqSLn4IlQZcJe4VVIx8U0d+qZqd1jUXZCpQX+EJBsYZcifQOqFF vz5mkwX3GeUpkINSpXrysITS9XhLl5QM77ETJ7UTrd7cK0A/dGVPaDySBAFyMr3GLgGb MsGg== X-Gm-Message-State: AJIora/yVQ6kWe2OFckAhMgeNPGkgl83JwqFsxru5m4J4cvrfmVNhy7O RV3lfVuyQggmUZ2NrFRyiRN6GA== X-Google-Smtp-Source: AGRyM1sZ1VgoM4AmEjYKT5MIQE/MAC9Lf8h2/BsOzxicN29oYsvzMkY3Cxb2IYT7Ds5RdmwC6UwG7g== X-Received: by 2002:a05:6512:e95:b0:479:1087:2eaf with SMTP id bi21-20020a0565120e9500b0047910872eafmr6286782lfb.274.1655301579194; Wed, 15 Jun 2022 06:59:39 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id z23-20020a2e8e97000000b0025530fa4edesm1694962ljk.49.2022.06.15.06.59.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 06:59:38 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Subject: [PATCH 3/5] drm/msm/mdss: check for core clk before accessing HW_REV Date: Wed, 15 Jun 2022 16:59:33 +0300 Message-Id: <20220615135935.87381-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220615135935.87381-1-dmitry.baryshkov@linaro.org> References: <20220615135935.87381-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bjorn Andersson , Stephen Boyd , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Rather than checking whether the platform is an mdp5 or dpu platform, check if the MDP_CLK is provided or not before trying to access HW_REV (and skip reading the registers if the clock is not provided by the DT). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index f7b4628986b8..d81d8fe3584e 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -32,7 +32,6 @@ struct msm_mdss { void __iomem *mmio; struct clk_bulk_data *clocks; size_t num_clocks; - bool is_mdp5; struct { unsigned long enabled_mask; struct irq_domain *domain; @@ -186,6 +185,19 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss, } } +static bool msm_mdss_has_clock(struct msm_mdss *msm_mdss, const char *name) +{ + unsigned int i; + + for (i = 0; i < msm_mdss->num_clocks; i++) { + if (!strcmp(msm_mdss->clocks[i].id, name) && + msm_mdss->clocks[i].clk) + return true; + } + + return false; +} + static int msm_mdss_enable(struct msm_mdss *msm_mdss) { int ret; @@ -198,10 +210,11 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) } /* - * HW_REV requires MDSS_MDP_CLK, which is not enabled by the mdss on - * mdp5 hardware. Skip reading it for now. + * HW_REV requires MDSS_MDP_CLK, which is not used for MDSS device in + * older device trees. Skip accessing registers if the clock is not + * present. */ - if (msm_mdss->is_mdp5) + if (!msm_mdss_has_clock(msm_mdss, "core")) return 0; hw_rev = readl_relaxed(msm_mdss->mmio + HW_REV); @@ -345,7 +358,6 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5 return ERR_PTR(ret); } msm_mdss->num_clocks = ret; - msm_mdss->is_mdp5 = is_mdp5; msm_mdss->dev = &pdev->dev; From patchwork Wed Jun 15 13:59:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12882403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 654FCC433EF for ; Wed, 15 Jun 2022 13:59:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6718F10F731; Wed, 15 Jun 2022 13:59:49 +0000 (UTC) Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by gabe.freedesktop.org (Postfix) with ESMTPS id BFC0710F272 for ; Wed, 15 Jun 2022 13:59:41 +0000 (UTC) Received: by mail-lf1-x12d.google.com with SMTP id s6so19011344lfo.13 for ; Wed, 15 Jun 2022 06:59:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bEZ1NYwvFdMufdWC263WCaYuMJCoQlXujRGSLpZbvcs=; b=HoEHo8nE7GLoRGEAW8WNXManvVcmOERlVef/MFIQmTjnWqI9n6KuhjFTXXyu467mCP wDh3yHjP+hfr8e5XXVLtM9JYP1iaPcbWylOLxKPlzGt/4ZN4vUsGM4wkkfqEqZgrPUJj 6XnAa9Y+TFfOkXp/XWOpWTP9A2OAC4uaAadarau8UYJkQ0zyAahzmsTeOy5sxn+qGAlz OU2WDv5hp1Et8LCqN47xtG2o1ZtZvdqbJBPwYyT7G0uMMIodTLUgFeJk7aw2tVkeGFdD Ax3Hi6obgp4xhkf1fxYH4dN7M4sWY2QfeafWwwSNRedp46CDBYOM3J8nenyAoYAL9a4M JvzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bEZ1NYwvFdMufdWC263WCaYuMJCoQlXujRGSLpZbvcs=; b=czwkDyGM9U4ukfOcLhl2THYbYs5mJveMlzBgVV6wEzHLW+tL0uth5y+G9iFUBe1/y2 duTgslC3WmUzNKIUL9FNPrDpFbcZH4qEgmusG8ia52NFa9E8m1ko5z8AnJ0QTew20V7c UXBZ9VTvZ83at0Vnuadxtx02rYBRZkaUljcrFH/OnR+jzMajFpu1/R+vi8S9GepstOsI 3rh83iz1DEOxlZsivZ1iQlzUV9w5fLdbMwsD3AhtW7LvUC3q1j3VFGZ1SNfBi39VnJUd 376CXCANToacSmu/AZz+uC/q5m6YSPDtovCu6sN9z3pyxe+1gp4hOligFGXwVMzQH4OK Z75Q== X-Gm-Message-State: AJIora+2qwYnIvqieuK44JN1zydo1ABi+kdTG8fNOQb6GNp8RsoUfjyG mqi8Vi1wE9HRy48YE7VSJ83IWw== X-Google-Smtp-Source: AGRyM1uXl2s7Akk5f7xlXiXmsBx1wbqbRqPDTlvwERbZp7pnN9o7vXDeIEsp8qtITl4tR0HL0nb1SA== X-Received: by 2002:a05:6512:3b8d:b0:478:f9f3:962b with SMTP id g13-20020a0565123b8d00b00478f9f3962bmr6579960lfv.169.1655301580074; Wed, 15 Jun 2022 06:59:40 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id z23-20020a2e8e97000000b0025530fa4edesm1694962ljk.49.2022.06.15.06.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 06:59:39 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Subject: [PATCH 4/5] drm/msm/mdss: move is_mdp5 condition to msm_mdss_init Date: Wed, 15 Jun 2022 16:59:34 +0300 Message-Id: <20220615135935.87381-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220615135935.87381-1-dmitry.baryshkov@linaro.org> References: <20220615135935.87381-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bjorn Andersson , Stephen Boyd , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Move is_mdp5 check to a more logical place, to the msm_mdss_init(), rather than getting it in the mdss_probe() and passing it then as an argument. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index d81d8fe3584e..ce8ff5bfe55a 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -329,8 +329,9 @@ static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_d return num_clocks; } -static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5) +static struct msm_mdss *msm_mdss_init(struct platform_device *pdev) { + bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss"); struct msm_mdss *msm_mdss; int ret; int irq; @@ -420,11 +421,10 @@ static const struct dev_pm_ops mdss_pm_ops = { static int mdss_probe(struct platform_device *pdev) { struct msm_mdss *mdss; - bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss"); struct device *dev = &pdev->dev; int ret; - mdss = msm_mdss_init(pdev, is_mdp5); + mdss = msm_mdss_init(pdev); if (IS_ERR(mdss)) return PTR_ERR(mdss); From patchwork Wed Jun 15 13:59:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12882404 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A06FC43334 for ; Wed, 15 Jun 2022 13:59:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 718B810F74C; Wed, 15 Jun 2022 13:59:49 +0000 (UTC) Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by gabe.freedesktop.org (Postfix) with ESMTPS id B822910F53F for ; Wed, 15 Jun 2022 13:59:42 +0000 (UTC) Received: by mail-lf1-x135.google.com with SMTP id be31so19055571lfb.10 for ; Wed, 15 Jun 2022 06:59:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hmuYPwQa1jhocO5psPDczMcPAlt9oeSQSumJCmiaYKg=; b=V0SMWQZDOrXALeVCBqwaWCFd8WspAVe46SWqzAh0uKYFL3AO2cwoYOo6q2NfimIbkm fy5YkUIoVpm8oYmkOZvm7OQ3ZEBjvcx90eP+IyjfnUfO29Xj6KSX8yILvA7s+xMCP17H XX7SQJyodlNgfTbVdAE99X8hWXTw3Z7mQW3xREz5H9qpPk1HgMyiIh+8eIhOTDRqbgv+ 0IliZuz1rzXjCjAgNEJZYfBxdbJue15Ch722prREzLoCHVX3f76cbmXvejgkTnuyAPo+ F0IBJFgr/Lw8r/K29/fD6RUoSB/bB6WOsEU2zrWiNtI+VF2zEOdgahdhx/sj3wIklgqA yXNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hmuYPwQa1jhocO5psPDczMcPAlt9oeSQSumJCmiaYKg=; b=LoybwbmTUvFAmegm0Ib6ttON2N0MxPVcqcDANaR4zIxHuZcbzA+bsjB2taEJH7/okU b1UkDuvuspRPziERaVuqo3S0RX6SnJmvT9CwpCPmasj+AnHnsKqYAxKhvNnnSLTeg6lr FnHWSdnxAZ5FwldmbmEfAZ8mcLJqzSo1o2QE0FQcXL5mJRFnrkuNYHvWjIP6x8nqpr6l +aHNBCTo1AukIbxCwwpLEBb89NRlpvOVxXyKIote0SqVDrGwAXQRkAZdO/F0XBCheIdM qjbeI9hej1TSCWKg+EE2oQ0s4uBYxRuRQ7Fu384nB5jOPpDi7buEZub/9Sjy2S1+8prQ 3cdw== X-Gm-Message-State: AJIora/R6BYnj+m9tByHSESxHurEIHqk5wsp/Cnhy4gHSMsli8nVX17M nFBKvB+T0kbcOSsml6uhb9ZpTw== X-Google-Smtp-Source: AGRyM1vkiSlaaS7HgWsdKdlvAox15z9dfhdTJCVxZj4b6ETZ4bWDKdP/yXoUuylqR7yIVkSwvpR1bA== X-Received: by 2002:a05:6512:3992:b0:47c:48fc:3c62 with SMTP id j18-20020a056512399200b0047c48fc3c62mr6374831lfu.102.1655301580930; Wed, 15 Jun 2022 06:59:40 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id z23-20020a2e8e97000000b0025530fa4edesm1694962ljk.49.2022.06.15.06.59.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 06:59:40 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar Subject: [PATCH 5/5] arm64: dts: qcom: add mdp_clk clock to the MDSS device Date: Wed, 15 Jun 2022 16:59:35 +0300 Message-Id: <20220615135935.87381-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220615135935.87381-1-dmitry.baryshkov@linaro.org> References: <20220615135935.87381-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bjorn Andersson , Stephen Boyd , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add MDP_CLK ("core") clock to the mdss device to allow MDSS driver to access HW_REV/etc registers. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index f0f81c23c16f..3d8ecfe56fb3 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -773,8 +773,9 @@ mdss: mdss@900000 { interrupt-controller; #interrupt-cells = <1>; - clocks = <&mmcc MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names = "iface", "core"; #address-cells = <1>; #size-cells = <1>;