From patchwork Thu Jun 16 12:00:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12883777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 459C6C43334 for ; Thu, 16 Jun 2022 12:01:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1F10311A4A9; Thu, 16 Jun 2022 12:01:29 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9AFF21134EC; Thu, 16 Jun 2022 12:01:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655380886; x=1686916886; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fHsDgzEnq7qjTAV60psifkAowBGHTR58dn0jlcaOlVI=; b=f4oJEm1+6BXBAIsTEoye4q4XFxcR/3whSxa0yf5sf+5/bZs6lYQcgPGR /7C6GwIK1kixAWbFRey4dI3gKTFrRU4LEyRiRYbZxV2YAWw1nBIVyULwB pluQ+80DxYLSxAFJz+crhpw17mRQACig0cjUX9bVWisIv6G28RnzZnvjQ tvwlCziq11TnzACkfqBZtPkgXXVTa4v7rSdVc4N1n2bpxzLLnT6cIdw1q ZerFJXW3TOuGRc66KvNirjOi1VgvwKAsLsHwxnQg2y/FYOZdAJYiIsEbW RiwHwtbG1Jgd4gQ0yVD+lcnUeUQaJ1CGvjjCpK51pbgrrKtPCS7GBN/e1 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10379"; a="343189548" X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="343189548" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:26 -0700 X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="713330861" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:23 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v2 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh Support Date: Thu, 16 Jun 2022 17:30:58 +0530 Message-Id: <20220616120106.24353-2-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220616120106.24353-1-anshuman.gupta@intel.com> References: <20220616120106.24353-1-anshuman.gupta@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tilak.tangudu@intel.com, tvrtko.ursulin@intel.com, Jani Nikula , Anshuman Gupta , jon.ewins@intel.com, badal.nilawar@intel.com, rodrigo.vivi@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR). DGFX VRSR can be enabled with runtime suspend D3Cold flow and with opportunistic S0ix system wide suspend flow as well. Without VRSR enablement i915 has to evict the lmem objects to system memory. Depending on some heuristics driver will evict lmem objects without VRSR. VRSR feature requires Host BIOS support, VRSR will be enable/disable by HOST BIOS using ACPI OpRegion. Adding OpRegion VRSR support in order to enable/disable VRSR on discrete cards. BSpec: 53440 Cc: Jani Nikula Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_opregion.c | 62 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_opregion.h | 11 ++++ 2 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index 6876ba30d5a9..11d8c5bb23ac 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -53,6 +53,8 @@ #define MBOX_ASLE_EXT BIT(4) /* Mailbox #5 */ #define MBOX_BACKLIGHT BIT(5) /* Mailbox #2 (valid from v3.x) */ +#define PCON_DGFX_BIOS_SUPPORTS_VRSR BIT(11) +#define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID BIT(12) #define PCON_HEADLESS_SKU BIT(13) struct opregion_header { @@ -130,7 +132,8 @@ struct opregion_asle { u64 rvda; /* Physical (2.0) or relative from opregion (2.1+) * address of raw VBT data. */ u32 rvds; /* Size of raw vbt data */ - u8 rsvd[58]; + u8 vrsr; /* DGFX Video Ram Self Refresh */ + u8 rsvd[57]; } __packed; /* OpRegion mailbox #5: ASLE ext */ @@ -201,6 +204,9 @@ struct opregion_asle_ext { #define ASLE_PHED_EDID_VALID_MASK 0x3 +/* VRAM SR */ +#define ASLE_VRSR_ENABLE BIT(0) + /* Software System Control Interrupt (SWSCI) */ #define SWSCI_SCIC_INDICATOR (1 << 0) #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT 1 @@ -921,6 +927,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) opregion->header->over.minor, opregion->header->over.revision); + drm_dbg(&dev_priv->drm, "OpRegion PCON values 0x%x\n", opregion->header->pcon); + mboxes = opregion->header->mboxes; if (mboxes & MBOX_ACPI) { drm_dbg(&dev_priv->drm, "Public ACPI methods supported\n"); @@ -1246,3 +1254,55 @@ void intel_opregion_unregister(struct drm_i915_private *i915) opregion->vbt = NULL; opregion->lid_state = NULL; } + +/** + * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self + * Refresh capability support. + * @i915: pointer to i915 device. + * + * It checks opregion pcon vram_sr fields to get HOST BIOS vram_sr + * capability support. It is only applocable to DGFX. + * + * Returns: + * true when bios supports vram_sr, or false if bios doesn't support. + */ +bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915) +{ + struct intel_opregion *opregion = &i915->opregion; + + if (!IS_DGFX(i915)) + return false; + + if (!opregion) + return false; + + if (opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID) + return opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR; + else + return false; +} + +/** + * intel_opregion_vram_sr() - enable/disable VRAM Self Refresh. + * @i915: pointer to i915 device. + * @enable: Argument to enable/disable VRSR. + * + * It enables/disables vram_sr in opregion ASLE MBOX, based upon that + * HOST BIOS will enables and disbales VRAM_SR during + * ACPI _PS3/_OFF and _PS/_ON glue method. + */ +void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable) +{ + struct intel_opregion *opregion = &i915->opregion; + + if (!opregion) + return; + + if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not available\n")) + return; + + if (enable) + opregion->asle->vrsr |= ASLE_VRSR_ENABLE; + else + opregion->asle->vrsr &= ~ASLE_VRSR_ENABLE; +} diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h index 2f261f985400..73c9d81d5ee6 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.h +++ b/drivers/gpu/drm/i915/display/intel_opregion.h @@ -75,6 +75,8 @@ int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, pci_power_t state); int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); struct edid *intel_opregion_get_edid(struct intel_connector *connector); +bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915); +void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable); bool intel_opregion_headless_sku(struct drm_i915_private *i915); @@ -134,6 +136,15 @@ static inline bool intel_opregion_headless_sku(struct drm_i915_private *i915) return false; } +static bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915) +{ + return false; +} + +static void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable) +{ +} + #endif /* CONFIG_ACPI */ #endif From patchwork Thu Jun 16 12:00:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12883778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76ABCC43334 for ; Thu, 16 Jun 2022 12:01:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D52011A4AC; Thu, 16 Jun 2022 12:01:32 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id EE88211A4AC; Thu, 16 Jun 2022 12:01:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655380890; x=1686916890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KyeKOIb9ToFUz0oO+c4cuz+Em5bBHZji6YQ4o1dfiy4=; b=HMCBPEzT3SJNhCe7rbSrMfCGz8eIvs9jq+y2Oz21w1KBH44PyobIV6A0 U+kuNzoEOCiDWWTCrRkPw3AuJPYLuvq0zVERezPqxzzD+yUpL9MqXXE2Q E43C1yF9Sl2c6mCtJSpnVKydLaNPFa4VPRae04PsAOqrH7tRm9SOIvHjc DHgHzhmqU0baz74wi63/KNnOwD9KUYmcRMTjLcF7+f20RHt6a571+9nRs nTBkWxzeHDLIQOhFmQagCBtiXS6N26+B9RdkZit9v17tjSGstr7USZjpd 9fhnYCYi1wD0azfmr44K+sGDRB473V4sGqkF6YYyqYJoB1PTUaJ2ETEKI Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10379"; a="343189568" X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="343189568" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:29 -0700 X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="713330880" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:26 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v2 2/9] drm/i915/dg1: OpRegion PCON DG1 MBD config support Date: Thu, 16 Jun 2022 17:30:59 +0530 Message-Id: <20220616120106.24353-3-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220616120106.24353-1-anshuman.gupta@intel.com> References: <20220616120106.24353-1-anshuman.gupta@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tilak.tangudu@intel.com, tvrtko.ursulin@intel.com, Jani Nikula , Anshuman Gupta , jon.ewins@intel.com, badal.nilawar@intel.com, rodrigo.vivi@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD) configs. MBD config requires HOST BIOS GPIO toggling support in order to enable/disable VRAM SR using ACPI OpRegion. i915 requires to check OpRegion PCON MBD Config bits to discover whether Gfx Card is MBD config before enabling VRSR. BSpec: 53440 Cc: Jani Nikula Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_opregion.c | 43 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_opregion.h | 6 +++ 2 files changed, 49 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index 11d8c5bb23ac..c8cdcde89dfc 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -53,6 +53,8 @@ #define MBOX_ASLE_EXT BIT(4) /* Mailbox #5 */ #define MBOX_BACKLIGHT BIT(5) /* Mailbox #2 (valid from v3.x) */ +#define PCON_DG1_MBD_CONFIG BIT(9) +#define PCON_DG1_MBD_CONFIG_FIELD_VALID BIT(10) #define PCON_DGFX_BIOS_SUPPORTS_VRSR BIT(11) #define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID BIT(12) #define PCON_HEADLESS_SKU BIT(13) @@ -1255,6 +1257,44 @@ void intel_opregion_unregister(struct drm_i915_private *i915) opregion->lid_state = NULL; } +static bool intel_opregion_dg1_mbd_config(struct drm_i915_private *i915) +{ + struct intel_opregion *opregion = &i915->opregion; + + if (!IS_DG1(i915)) + return false; + + if (!opregion) + return false; + + if (opregion->header->pcon & PCON_DG1_MBD_CONFIG_FIELD_VALID) + return opregion->header->pcon & PCON_DG1_MBD_CONFIG; + else + return false; +} + +/** + * intel_opregion_vram_sr_required(). + * @i915 i915 device priv data. + * + * It checks whether a DGFX card is Mother Board Down config depending + * on respective discrete platform. + * + * Returns: + * It returns a boolean whether opregion vram_sr support is required. + */ +bool +intel_opregion_vram_sr_required(struct drm_i915_private *i915) +{ + if (!IS_DGFX(i915)) + return false; + + if (IS_DG1(i915)) + return intel_opregion_dg1_mbd_config(i915); + + return false; +} + /** * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self * Refresh capability support. @@ -1298,6 +1338,9 @@ void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable) if (!opregion) return; + if (!intel_opregion_vram_sr_required(i915)) + return; + if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not available\n")) return; diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h index 73c9d81d5ee6..ad40c97f9565 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.h +++ b/drivers/gpu/drm/i915/display/intel_opregion.h @@ -77,6 +77,7 @@ int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); struct edid *intel_opregion_get_edid(struct intel_connector *connector); bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915); void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable); +bool intel_opregion_vram_sr_required(struct drm_i915_private *i915); bool intel_opregion_headless_sku(struct drm_i915_private *i915); @@ -145,6 +146,11 @@ static void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable) { } +static bool intel_opregion_vram_sr_required(struct drm_i915_private *i915) +{ + return false; +} + #endif /* CONFIG_ACPI */ #endif From patchwork Thu Jun 16 12:01:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12883779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82D9AC43334 for ; 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a="343189582" X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="343189582" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:32 -0700 X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="713330894" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:30 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform Date: Thu, 16 Jun 2022 17:31:00 +0530 Message-Id: <20220616120106.24353-4-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220616120106.24353-1-anshuman.gupta@intel.com> References: <20220616120106.24353-1-anshuman.gupta@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tilak.tangudu@intel.com, tvrtko.ursulin@intel.com, Anshuman Gupta , jon.ewins@intel.com, badal.nilawar@intel.com, rodrigo.vivi@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" DG2 NB SKU need to distinguish between MBD and AIC to probe the VRAM Self Refresh feature support. Adding those sub platform accordingly. Cc: Matt Roper Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/intel_device_info.c | 21 +++++++++++++++++++++ drivers/gpu/drm/i915/intel_device_info.h | 11 +++++++---- include/drm/i915_pciids.h | 23 ++++++++++++++++------- 4 files changed, 47 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a5bc6a774c5a..f1f8699eedfd 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO) #define IS_DG2_G10(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10) #define IS_DG2_G11(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11) #define IS_DG2_G12(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12) #define IS_ADLS_RPLS(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index f0bf23726ed8..93da555adc4e 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = { INTEL_RPLP_IDS(0), }; +static const u16 subplatform_g10_mb_mbd_ids[] = { + INTEL_DG2_G10_NB_MBD_IDS(0), +}; + +static const u16 subplatform_g11_mb_mbd_ids[] = { + INTEL_DG2_G11_NB_MBD_IDS(0), +}; + +static const u16 subplatform_g12_mb_mbd_ids[] = { + INTEL_DG2_G12_NB_MBD_IDS(0), +}; + static const u16 subplatform_g10_ids[] = { INTEL_DG2_G10_IDS(0), INTEL_ATS_M150_IDS(0), @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915) } else if (find_devid(devid, subplatform_rpl_ids, ARRAY_SIZE(subplatform_rpl_ids))) { mask = BIT(INTEL_SUBPLATFORM_RPL); + } else if (find_devid(devid, subplatform_g10_mb_mbd_ids, + ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) { + mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD); + } else if (find_devid(devid, subplatform_g11_mb_mbd_ids, + ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) { + mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD); + } else if (find_devid(devid, subplatform_g12_mb_mbd_ids, + ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) { + mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD); } else if (find_devid(devid, subplatform_g10_ids, ARRAY_SIZE(subplatform_g10_ids))) { mask = BIT(INTEL_SUBPLATFORM_G10); diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 08341174ee0a..c929e2d7e59c 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -97,7 +97,7 @@ enum intel_platform { * it is fine for the same bit to be used on multiple parent platforms. */ -#define INTEL_SUBPLATFORM_BITS (3) +#define INTEL_SUBPLATFORM_BITS (6) #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) /* HSW/BDW/SKL/KBL/CFL */ @@ -111,9 +111,12 @@ enum intel_platform { #define INTEL_SUBPLATFORM_UY (0) /* DG2 */ -#define INTEL_SUBPLATFORM_G10 0 -#define INTEL_SUBPLATFORM_G11 1 -#define INTEL_SUBPLATFORM_G12 2 +#define INTEL_SUBPLATFORM_G10_NB_MBD 0 +#define INTEL_SUBPLATFORM_G11_NB_MBD 1 +#define INTEL_SUBPLATFORM_G12_NB_MBD 2 +#define INTEL_SUBPLATFORM_G10 3 +#define INTEL_SUBPLATFORM_G11 4 +#define INTEL_SUBPLATFORM_G12 5 /* ADL */ #define INTEL_SUBPLATFORM_RPL 0 diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 4585fed4e41e..198be417bb2d 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -693,32 +693,41 @@ INTEL_VGA_DEVICE(0xA7A9, info) /* DG2 */ -#define INTEL_DG2_G10_IDS(info) \ +#define INTEL_DG2_G10_NB_MBD_IDS(info) \ INTEL_VGA_DEVICE(0x5690, info), \ INTEL_VGA_DEVICE(0x5691, info), \ - INTEL_VGA_DEVICE(0x5692, info), \ + INTEL_VGA_DEVICE(0x5692, info) + +#define INTEL_DG2_G11_NB_MBD_IDS(info) \ + INTEL_VGA_DEVICE(0x5693, info), \ + INTEL_VGA_DEVICE(0x5694, info), \ + INTEL_VGA_DEVICE(0x5695, info) + +#define INTEL_DG2_G12_NB_MBD_IDS(info) \ + INTEL_VGA_DEVICE(0x5696, info), \ + INTEL_VGA_DEVICE(0x5697, info) + +#define INTEL_DG2_G10_IDS(info) \ INTEL_VGA_DEVICE(0x56A0, info), \ INTEL_VGA_DEVICE(0x56A1, info), \ INTEL_VGA_DEVICE(0x56A2, info) #define INTEL_DG2_G11_IDS(info) \ - INTEL_VGA_DEVICE(0x5693, info), \ - INTEL_VGA_DEVICE(0x5694, info), \ - INTEL_VGA_DEVICE(0x5695, info), \ INTEL_VGA_DEVICE(0x56A5, info), \ INTEL_VGA_DEVICE(0x56A6, info), \ INTEL_VGA_DEVICE(0x56B0, info), \ INTEL_VGA_DEVICE(0x56B1, info) #define INTEL_DG2_G12_IDS(info) \ - INTEL_VGA_DEVICE(0x5696, info), \ - INTEL_VGA_DEVICE(0x5697, info), \ INTEL_VGA_DEVICE(0x56A3, info), \ INTEL_VGA_DEVICE(0x56A4, info), \ INTEL_VGA_DEVICE(0x56B2, info), \ INTEL_VGA_DEVICE(0x56B3, info) #define INTEL_DG2_IDS(info) \ + INTEL_DG2_G10_NB_MBD_IDS(info), \ + INTEL_DG2_G11_NB_MBD_IDS(info), \ + INTEL_DG2_G12_NB_MBD_IDS(info), \ INTEL_DG2_G10_IDS(info), \ INTEL_DG2_G11_IDS(info), \ INTEL_DG2_G12_IDS(info) From patchwork Thu Jun 16 12:01:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12883780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F229AC433EF for ; Thu, 16 Jun 2022 12:02:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 42D7111A4B9; Thu, 16 Jun 2022 12:02:02 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id A1D3611A4B9; Thu, 16 Jun 2022 12:02:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655380921; x=1686916921; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0ByjhdNE3YCvFPUu4QT9FmBy4clWJL+DcwDitYP/QQc=; b=kn/3bVVatRLlCDtz70STjHM5fAnfBtpJlQJ/+PTM+l34kyLEs1+3+0H+ krFPkS2DtME3JgqdgJ98c3rs0eQoFKRaudeBUvzv36EhbFfW6tdlO8ELi PBJmz7bHKLmsDY8gCMUV0NteIPYK4PBJ7OyoBVbjMJ3Zo65H6noWSXqPy yml8oXNUzXH+QjcYkN5fp8RJdjkKLBEQC0cFTzrS8w+UCsFfHYDcAf2hb M/ac4mROXTwxwvRpSwHdfFjcVv+odovVyegYiLlIHXA6gVr2Pi5LsIWCt weInkqf8WbavpCaXF65X6ujn8lEUvaO91qyvkPrXT3tDiFKeDw1/O3RCv g==; X-IronPort-AV: E=McAfee;i="6400,9594,10379"; a="343189598" X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="343189598" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:35 -0700 X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="713330901" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:33 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v2 4/9] drm/i915/dg2: DG2 MBD config Date: Thu, 16 Jun 2022 17:31:01 +0530 Message-Id: <20220616120106.24353-5-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220616120106.24353-1-anshuman.gupta@intel.com> References: <20220616120106.24353-1-anshuman.gupta@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tilak.tangudu@intel.com, tvrtko.ursulin@intel.com, Anshuman Gupta , jon.ewins@intel.com, badal.nilawar@intel.com, rodrigo.vivi@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add DG2 Motherboard Down Config check support. v2: - Don't use pciid to check DG2 MBD. [Jani] BSpec: 44477 Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index c8cdcde89dfc..50dcd6d3558e 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -1291,6 +1291,8 @@ intel_opregion_vram_sr_required(struct drm_i915_private *i915) if (IS_DG1(i915)) return intel_opregion_dg1_mbd_config(i915); + else if (IS_DG2_MBD(i915)) + return true; return false; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f1f8699eedfd..28eee8088822 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1006,6 +1006,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2) #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO) +#define IS_DG2_G10_NB_MBD(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) +#define IS_DG2_G11_NB_MBD(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) +#define IS_DG2_G12_NB_MBD(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) #define IS_DG2_G10(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10) @@ -1015,6 +1021,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_DG2_G12(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12) + +#define IS_DG2_MBD(dev_priv) (IS_DG2_G10_NB_MBD(dev_priv) || IS_DG2_G11_NB_MBD(dev_priv) || \ + IS_DG2_G12_NB_MBD(dev_priv)) #define IS_ADLS_RPLS(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) #define IS_ADLP_N(dev_priv) \ From patchwork Thu Jun 16 12:01:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12883781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6F9AC43334 for ; Thu, 16 Jun 2022 12:02:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0796E11A4C3; Thu, 16 Jun 2022 12:02:05 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 73B4F11A4BC; Thu, 16 Jun 2022 12:02:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655380922; x=1686916922; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VHTODF7UhDo72sATEzIwHCmUiR+gBcFlIkh9LkNvUEA=; b=MEIQuvKL56gA6CtK8OSAoonggtPDYvNuY/DJw00L4GKO1njJ9Xah+KrB Ex315cq1ggJrjEV9hFjXxbCmjjJwlyQAf6DMQdh3lKj0KmJySh2DYCwD9 SkGCC4H6y8W3v1Sqo+VAIO2dTvukzqhQnd7I+z8zzX3SRlpwoKvSLnwZU EgXppDyjxgagF/VYS9fWd4g3NaLBTXEFZAC+/qO7yaXncRxBwyBsF4nc9 6LpRmKPEqmdE/MRrsNb+mHNwyp0dMRBAb8gXdRTnIIbxQL6B3QHpsng5C 7jh06sbGZJRQN2QpHkOnoONMAednOVFMShuBnkNVDYnawqsZeV4428d1k Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10379"; a="343189607" X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="343189607" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:39 -0700 X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="713330925" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:36 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v2 5/9] drm/i915/dgfx: Add has_lmem_sr Date: Thu, 16 Jun 2022 17:31:02 +0530 Message-Id: <20220616120106.24353-6-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220616120106.24353-1-anshuman.gupta@intel.com> References: <20220616120106.24353-1-anshuman.gupta@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tilak.tangudu@intel.com, tvrtko.ursulin@intel.com, Anshuman Gupta , jon.ewins@intel.com, badal.nilawar@intel.com, rodrigo.vivi@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add has_lmem_sr platform specific flag to know, whether platform has VRAM self refresh support. As of now both DG1 and DG2 client platforms supports VRAM self refresh with D3Cold but let it enable first on DG2 as primary lead platform for D3Cold support. Let it get enable on DG1 once this feature is stable. Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_pci.c | 2 ++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 3 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 28eee8088822..7983b36c1720 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1313,6 +1313,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) +#define HAS_LMEM_SR(i915) (INTEL_INFO(i915)->has_lmem_sr) /* * Platform has the dedicated compression control state for each lmem surfaces diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 5e51fc29bb8b..04aad54033dd 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -917,6 +917,7 @@ static const struct intel_device_info dg1_info = { DGFX_FEATURES, .graphics.rel = 10, PLATFORM(INTEL_DG1), + .has_lmem_sr = 0, .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), .require_force_probe = 1, .platform_engine_mask = @@ -1074,6 +1075,7 @@ static const struct intel_device_info xehpsdv_info = { static const struct intel_device_info dg2_info = { DG2_FEATURES, XE_LPD_FEATURES, + .has_lmem_sr = 1, .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_D), .require_force_probe = 1, diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index c929e2d7e59c..db51cdb9e09a 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -157,6 +157,7 @@ enum intel_ppgtt_type { func(has_l3_ccs_read); \ func(has_l3_dpf); \ func(has_llc); \ + func(has_lmem_sr); \ func(has_logical_ring_contexts); \ func(has_logical_ring_elsq); \ func(has_media_ratio_mode); \ From patchwork Thu Jun 16 12:01:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12883782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C890AC43334 for ; Thu, 16 Jun 2022 12:02:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 39BC211A4C7; Thu, 16 Jun 2022 12:02:06 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 24AEC11A4BC; Thu, 16 Jun 2022 12:02:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655380924; x=1686916924; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cdwNXAseuVTM4Y4PeKyaSTc28JONKkgJnhx1JD/8agA=; b=Is1hmpPKOn/IPIjacXgjYVYn2zf0Q9XLJxlYaW3v+igEJA65tYxxTBbd ulAUYlHEmhdO6jBV9vH864Z0uPVQ3X+MNsDmiyK3BqOST37SoVzWWttEb pN2Dhl8pGHVaH42nkU0wEVbmJMSWBLUzGrhToX01HOlcMjKLNVwFcNIj2 gWPPLuRMgtPnBt0UdbcazzBir8aUawAQ6aTPkCe9N4/aizbMi0vZItJ+i vU6xXHMdn8ScydFFxhMhr/yNhGIQTsOT+5AqhCxoq1WIypB2NM5oMWVwW MgHODp9MhtpTA6PZIaibn3tBBmDyz4NGzspfEB5jNjJF1luWbnhfo5fJ3 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10379"; a="343189617" X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="343189617" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:42 -0700 X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="713330932" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:39 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v2 6/9] drm/i915/dgfx: Setup VRAM SR with D3COLD Date: Thu, 16 Jun 2022 17:31:03 +0530 Message-Id: <20220616120106.24353-7-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220616120106.24353-1-anshuman.gupta@intel.com> References: <20220616120106.24353-1-anshuman.gupta@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tilak.tangudu@intel.com, tvrtko.ursulin@intel.com, Jani Nikula , Anshuman Gupta , jon.ewins@intel.com, badal.nilawar@intel.com, rodrigo.vivi@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Setup VRAM Self Refresh with D3COLD state. VRAM Self Refresh will retain the context of VRAM, driver need to save any corresponding hardware state that needs to be restore on D3COLD exit, example PCI state. Cc: Jani Nikula Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_driver.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 7 +++++ drivers/gpu/drm/i915/i915_reg.h | 4 +++ drivers/gpu/drm/i915/intel_pcode.c | 28 +++++++++++++++++++ drivers/gpu/drm/i915/intel_pcode.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 43 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_pm.h | 2 ++ 7 files changed, 88 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index d26dcca7e654..aa1fb15b1f11 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -649,6 +649,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) if (ret) goto err_msi; + intel_pm_vram_sr_setup(dev_priv); + /* * Fill the dram structure to get the system dram info. This will be * used for memory latency calculation. diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7983b36c1720..09f53aeda8d0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -624,6 +624,13 @@ struct drm_i915_private { u32 bxt_phy_grc; u32 suspend_count; + + struct { + /* lock to protect vram_sr flags */ + struct mutex lock; + bool supported; + } vram_sr; + struct i915_suspend_saved_registers regfile; struct vlv_s0ix_state *vlv_s0ix_state; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 932bd6aa4a0a..0e3dc4a8846a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6766,6 +6766,8 @@ #define DG1_PCODE_STATUS 0x7E #define DG1_UNCORE_GET_INIT_STATUS 0x0 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 +#define DG1_PCODE_D3_VRAM_SR 0x71 +#define DG1_ENABLE_SR 0x1 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 #define XEHPSDV_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */ /* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ @@ -6779,6 +6781,8 @@ #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) +#define VRAM_CAPABILITY _MMIO(0x138144) +#define VRAM_SUPPORTED REG_BIT(0) /* IVYBRIDGE DPF */ #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c index a234d9b4ed14..88bd1f44cfb2 100644 --- a/drivers/gpu/drm/i915/intel_pcode.c +++ b/drivers/gpu/drm/i915/intel_pcode.c @@ -246,3 +246,31 @@ int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u3 return err; } + +/** + * intel_pcode_enable_vram_sr - Enable pcode vram_sr. + * @dev_priv: i915 device + * + * This function triggers the required pcode flow to enable vram_sr. + * This function stictly need to call from rpm handlers, as i915 is + * transitioning to rpm idle/suspend, it doesn't require to grab + * rpm wakeref. + * + * Returns: + * returns returned value from pcode mbox write. + */ +int intel_pcode_enable_vram_sr(struct drm_i915_private *i915) +{ + int ret = 0; + + if (!HAS_LMEM_SR(i915)) + return ret; + + ret = snb_pcode_write(&i915->uncore, + REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, + DG1_PCODE_D3_VRAM_SR) | + REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, + DG1_ENABLE_SR), 0); /* no data needed for this cmd */ + + return ret; +} diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h index 8d2198e29422..295594514d49 100644 --- a/drivers/gpu/drm/i915/intel_pcode.h +++ b/drivers/gpu/drm/i915/intel_pcode.h @@ -9,6 +9,7 @@ #include struct intel_uncore; +struct drm_i915_private; int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1); int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val, @@ -26,5 +27,6 @@ int intel_pcode_init(struct intel_uncore *uncore); */ int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val); int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val); +int intel_pcode_enable_vram_sr(struct drm_i915_private *i915); #endif /* _INTEL_PCODE_H */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5a61fc3f26c1..299fbc5375a9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8166,6 +8166,49 @@ void intel_pm_setup(struct drm_i915_private *dev_priv) atomic_set(&dev_priv->runtime_pm.wakeref_count, 0); } +void intel_pm_vram_sr_setup(struct drm_i915_private *i915) +{ + if (!HAS_LMEM_SR(i915)) + return; + + mutex_init(&i915->vram_sr.lock); + + i915->vram_sr.supported = intel_uncore_read(&i915->uncore, + VRAM_CAPABILITY) & VRAM_SUPPORTED; + if (intel_opregion_vram_sr_required(i915)) + i915->vram_sr.supported = i915->vram_sr.supported && + intel_opregion_bios_supports_vram_sr(i915); +} + +int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable) +{ + int ret = 0; + + if (!HAS_LMEM_SR(i915)) + return -EOPNOTSUPP; + + mutex_lock(&i915->vram_sr.lock); + if (!i915->vram_sr.supported) { + drm_dbg(&i915->drm, "VRAM Self Refresh is not supported\n"); + ret = -EOPNOTSUPP; + goto unlock; + } + + drm_dbg(&i915->drm, "VRAM Self Refresh supported\n"); + if (enable) + ret = intel_pcode_enable_vram_sr(i915); + + if (ret) + goto unlock; + + intel_opregion_vram_sr(i915, enable); + +unlock: + mutex_unlock(&i915->vram_sr.lock); + + return ret; +} + static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj) { struct intel_dbuf_state *dbuf_state; diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index 50604cf7398c..0da85d6b9ea7 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -31,6 +31,8 @@ int ilk_wm_max_level(const struct drm_i915_private *dev_priv); void intel_init_pm(struct drm_i915_private *dev_priv); void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); void intel_pm_setup(struct drm_i915_private *dev_priv); +void intel_pm_vram_sr_setup(struct drm_i915_private *i915); +int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable); void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv); void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv); void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv); From patchwork Thu Jun 16 12:01:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12883783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7EB25C433EF for ; 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a="343189623" X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="343189623" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:45 -0700 X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="713330941" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:42 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v2 7/9] drm/i915/rpm: Enable D3Cold VRAM SR Support Date: Thu, 16 Jun 2022 17:31:04 +0530 Message-Id: <20220616120106.24353-8-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220616120106.24353-1-anshuman.gupta@intel.com> References: <20220616120106.24353-1-anshuman.gupta@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tilak.tangudu@intel.com, tvrtko.ursulin@intel.com, Anshuman Gupta , Chris Wilson , jon.ewins@intel.com, badal.nilawar@intel.com, rodrigo.vivi@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Intel Client DGFX card supports D3Cold with two option. D3Cold-off zero watt, D3Cold-VRAM Self Refresh. i915 requires to evict the lmem objects to smem in order to support D3Cold-Off, which increases i915 the suspend/resume latency. Enabling VRAM Self Refresh feature optimize the latency with additional power cost which required to retain the lmem. Adding intel_runtime_idle (runtime_idle callback) to enable VRAM_SR, it will be used for policy to choose between D3Cold-off vs D3Cold-VRAM_SR. Since we have introduced i915 runtime_idle callback. It need to be warranted that Runtime PM Core invokes runtime_idle callback when runtime usages count becomes zero. That requires to use pm_runtime_put instead of pm_runtime_put_autosuspend. TODO: GuC interface state save/restore. Cc: Rodrigo Vivi Cc: Chris Wilson Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_driver.c | 26 +++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index aa1fb15b1f11..fcff5f3fe05e 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -1557,6 +1557,31 @@ static int i915_pm_restore(struct device *kdev) return i915_pm_resume(kdev); } +static int intel_runtime_idle(struct device *kdev) +{ + struct drm_i915_private *dev_priv = kdev_to_i915(kdev); + int ret = 1; + + if (!HAS_LMEM_SR(dev_priv)) { + /*TODO: Prepare for D3Cold-Off */ + goto out; + } + + disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + + ret = intel_pm_vram_sr(dev_priv, true); + if (!ret) + drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n"); + + enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + +out: + pm_runtime_mark_last_busy(kdev); + pm_runtime_autosuspend(kdev); + + return ret; +} + static int intel_runtime_suspend(struct device *kdev) { struct drm_i915_private *dev_priv = kdev_to_i915(kdev); @@ -1742,6 +1767,7 @@ const struct dev_pm_ops i915_pm_ops = { .restore = i915_pm_restore, /* S0ix (via runtime suspend) event handlers */ + .runtime_idle = intel_runtime_idle, .runtime_suspend = intel_runtime_suspend, .runtime_resume = intel_runtime_resume, }; diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 6ed5786bcd29..4dade7e8a795 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -492,8 +492,7 @@ static void __intel_runtime_pm_put(struct intel_runtime_pm *rpm, intel_runtime_pm_release(rpm, wakelock); - pm_runtime_mark_last_busy(kdev); - pm_runtime_put_autosuspend(kdev); + pm_runtime_put(kdev); } /** From patchwork Thu Jun 16 12:01:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12883787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F167C433EF for ; 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a="343189638" X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="343189638" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:49 -0700 X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="713330950" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:45 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v2 8/9] drm/i915/xehpsdv: Store lmem region in gt Date: Thu, 16 Jun 2022 17:31:05 +0530 Message-Id: <20220616120106.24353-9-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220616120106.24353-1-anshuman.gupta@intel.com> References: <20220616120106.24353-1-anshuman.gupta@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tilak.tangudu@intel.com, Andi Shyti , tvrtko.ursulin@intel.com, Anshuman Gupta , jon.ewins@intel.com, badal.nilawar@intel.com, rodrigo.vivi@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tvrtko Ursulin Store a pointer to respective local memory region in intel_gt so it can be used when memory local to a GT needs to be allocated. Cc: Andi Shyti Signed-off-by: Tvrtko Ursulin Signed-off-by: Anshuman Gupta Reviewed-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index f33290358c51..7a535f670ae1 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -91,6 +91,7 @@ static int intel_gt_probe_lmem(struct intel_gt *gt) GEM_BUG_ON(!HAS_REGION(i915, id)); GEM_BUG_ON(i915->mm.regions[id]); i915->mm.regions[id] = mem; + gt->lmem = mem; return 0; } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index df708802889d..cd7744eaaeaa 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -23,6 +23,7 @@ #include "intel_gt_buffer_pool_types.h" #include "intel_hwconfig.h" #include "intel_llc_types.h" +#include "intel_memory_region.h" #include "intel_reset_types.h" #include "intel_rc6_types.h" #include "intel_rps_types.h" @@ -202,6 +203,8 @@ struct intel_gt { */ phys_addr_t phys_addr; + struct intel_memory_region *lmem; + struct intel_gt_info { unsigned int id; From patchwork Thu Jun 16 12:01:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 12883784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8C84C43334 for ; Thu, 16 Jun 2022 12:02:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EB6B911A4CA; Thu, 16 Jun 2022 12:02:13 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4C89011A4CE; Thu, 16 Jun 2022 12:02:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655380928; x=1686916928; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QFsJ+wHIUOBRzEH4ba1IHtPxx98YAbDnWDTPXCBr0gU=; b=LPRy4PQB0dmLM5yGCM5KIFpPD0vE4VGlRp/BJhq5/SwY+Pxa/Yx7jt7C b3dxLiFrPHkMZOt1KSqaTZTqT5FIaL8JQ3ReiA1On+PiXc2RyST7hqg5B XOg0gd1IXp1Ozdq1PJAPybCEzjfY6bg7qTDvIZp+qNy8y0BNLp4Xhj7Zc MGHcDMsKOOiB+K+ngN/Bh0SlJ8rJDcy+cGse6qHQTMVOMggetUakdt8CO ZpNJJHVIPkYmk4ph51Kj2G7j7vZs3TKce4oZ0+182eXY28zM7RND7Gzp+ 3NnOJ3QAp8xX8xIdek8S3QpDM7cxYXGG8NIcV3+qCBZlmfxBNEkk1FjJB Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10379"; a="343189649" X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="343189649" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:52 -0700 X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="713330969" Received: from srr4-3-linux-105-anshuma1.iind.intel.com ([10.223.74.179]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:01:49 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v2 9/9] drm/i915/rpm: d3cold Policy Date: Thu, 16 Jun 2022 17:31:06 +0530 Message-Id: <20220616120106.24353-10-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220616120106.24353-1-anshuman.gupta@intel.com> References: <20220616120106.24353-1-anshuman.gupta@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tilak.tangudu@intel.com, tvrtko.ursulin@intel.com, Anshuman Gupta , jon.ewins@intel.com, badal.nilawar@intel.com, rodrigo.vivi@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add d3cold_sr_lmem_threshold modparam to choose between d3cold-off zero watt and d3cold-VRAM Self Refresh. i915 requires to evict the lmem objects to smem in order to support d3cold-Off. If gfx root port is not capable of sending PME from d3cold then i915 don't need to program d3cold-off/d3cold-vram_sr sequence. FIXME: Eviction of lmem objects in case of D3Cold off is wip. Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_driver.c | 27 ++++++++++++++++++++++++--- drivers/gpu/drm/i915/i915_params.c | 4 ++++ drivers/gpu/drm/i915/i915_params.h | 3 ++- 3 files changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index fcff5f3fe05e..aef4b17efdbe 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -1560,15 +1560,36 @@ static int i915_pm_restore(struct device *kdev) static int intel_runtime_idle(struct device *kdev) { struct drm_i915_private *dev_priv = kdev_to_i915(kdev); + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + u64 lmem_total = to_gt(dev_priv)->lmem->total; + u64 lmem_avail = to_gt(dev_priv)->lmem->avail; + u64 lmem_used = lmem_total - lmem_avail; + struct pci_dev *root_pdev; int ret = 1; - if (!HAS_LMEM_SR(dev_priv)) { - /*TODO: Prepare for D3Cold-Off */ + root_pdev = pcie_find_root_port(pdev); + if (!root_pdev) + goto out; + + if (!pci_pme_capable(root_pdev, PCI_D3cold)) goto out; - } disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + if (lmem_used < dev_priv->params.d3cold_sr_lmem_threshold * 1024 * 1024) { + drm_dbg(&dev_priv->drm, "Prepare for D3Cold off\n"); + pci_d3cold_enable(root_pdev); + /* FIXME: Eviction of lmem objects and guc reset is wip */ + intel_pm_vram_sr(dev_priv, false); + enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + goto out; + } else if (!HAS_LMEM_SR(dev_priv)) { + /* Disable D3Cold to reduce the eviction latency */ + pci_d3cold_disable(root_pdev); + enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + goto out; + } + ret = intel_pm_vram_sr(dev_priv, true); if (!ret) drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n"); diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 701fbc98afa0..6c6b3c372d4d 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -197,6 +197,10 @@ i915_param_named(enable_gvt, bool, 0400, "Enable support for Intel GVT-g graphics virtualization host support(default:false)"); #endif +i915_param_named_unsafe(d3cold_sr_lmem_threshold, int, 0400, + "Enable Vidoe RAM Self refresh when size of lmem is greater to this threshold. " + "It helps to optimize the suspend/resume latecy. (default: 300mb)"); + #if CONFIG_DRM_I915_REQUEST_TIMEOUT i915_param_named_unsafe(request_timeout_ms, uint, 0600, "Default request/fence/batch buffer expiration timeout."); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index b5e7ea45d191..28f20ebaf41f 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -83,7 +83,8 @@ struct drm_printer; param(bool, verbose_state_checks, true, 0) \ param(bool, nuclear_pageflip, false, 0400) \ param(bool, enable_dp_mst, true, 0600) \ - param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) + param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) \ + param(int, d3cold_sr_lmem_threshold, 300, 0600) \ #define MEMBER(T, member, ...) T member; struct i915_params {