From patchwork Mon Jun 20 20:46:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nilawar, Badal" X-Patchwork-Id: 12888237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61787C433EF for ; Mon, 20 Jun 2022 20:47:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DDFAB10E2DE; Mon, 20 Jun 2022 20:47:02 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id AEAB210E2DE for ; Mon, 20 Jun 2022 20:47:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655758021; x=1687294021; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=loYycCINyba3bNa2TjcTyWnkmMBmQt2N1HChwZN/0+0=; b=lJjmw9uOC2liwMt4eNcTdVj2bZecfqDm+RDm3W2n+IlBSfVrQy5xM8gp GW/OKtrhkjnbTRNaFNbbnOgdT0hjE4m9fNDD2oXmzXQE9i6pL+QNxOEcB XSeb2Zr264brYICw8fqEIg6F/FkoJZYLCfepg9fwSA9RtEKwCcY2CLpo4 2IpYRqnuNF92xjgzPXTR7rnnXpMuBBATMC4iuBV4/c/btVJBG2cOL75q+ HAMJMYca0Qe3dBBb1V0DU9gDN3lnDvWtfbNd2VfBXThydSaJ3N4gUsupK d1l+4X2HYEs1fdj2UU5ehE2tBPX2SYnRE2U6LH2VbrLXjQUYEonhzCmE+ A==; X-IronPort-AV: E=McAfee;i="6400,9594,10384"; a="259792752" X-IronPort-AV: E=Sophos;i="5.92,207,1650956400"; d="scan'208";a="259792752" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2022 13:47:01 -0700 X-IronPort-AV: E=Sophos;i="5.92,207,1650956400"; d="scan'208";a="620226946" Received: from bnilawar-desk.iind.intel.com ([10.145.162.36]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2022 13:46:59 -0700 From: Badal Nilawar To: intel-gfx@lists.freedesktop.org Date: Tue, 21 Jun 2022 02:16:46 +0530 Message-Id: <20220620204649.894703-2-badal.nilawar@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220620204649.894703-1-badal.nilawar@intel.com> References: <20220620204649.894703-1-badal.nilawar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/hwmon: Add HWMON infrastructure patch X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-hwmon@vger.kernel.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Dale B Stimson As part of the System Managemenent Interface (SMI), HWMON subsystem can be used to get the raw sensor data. This patch sets up HWMON infrastructure v2: - Create HWMON infra patch (Ashutosh) - Fixed review comments (Jani) - Remove "select HWMON" from i915/Kconfig (Jani) Signed-off-by: Dale B Stimson Signed-off-by: Ashutosh Dixit Signed-off-by: Riana Tauro Signed-off-by: Badal Nilawar --- drivers/gpu/drm/i915/Makefile | 3 + drivers/gpu/drm/i915/i915_driver.c | 7 ++ drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_hwmon.c | 163 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_hwmon.h | 21 ++++ 5 files changed, 196 insertions(+) create mode 100644 drivers/gpu/drm/i915/i915_hwmon.c create mode 100644 drivers/gpu/drm/i915/i915_hwmon.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 6c17d3d6db24..09f5b5c74daf 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -208,6 +208,9 @@ i915-y += gt/uc/intel_uc.o \ # graphics system controller (GSC) support i915-y += gt/intel_gsc.o +# graphics hardware monitoring (HWMON) support +i915-$(CONFIG_HWMON) += i915_hwmon.o + # modesetting core code i915-y += \ display/hsw_ips.o \ diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index 0e224761d0ed..60c5cee41aa3 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -80,6 +80,7 @@ #include "i915_drm_client.h" #include "i915_drv.h" #include "i915_getparam.h" +#include "i915_hwmon.h" #include "i915_ioc32.h" #include "i915_ioctl.h" #include "i915_irq.h" @@ -721,6 +722,9 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) intel_gt_driver_register(to_gt(dev_priv)); +#ifdef CONFIG_HWMON + i915_hwmon_register(dev_priv); +#endif intel_display_driver_register(dev_priv); intel_power_domains_enable(dev_priv); @@ -747,6 +751,9 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) intel_display_driver_unregister(dev_priv); +#ifdef CONFIG_HWMON + i915_hwmon_unregister(dev_priv); +#endif intel_gt_driver_unregister(to_gt(dev_priv)); i915_perf_unregister(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c22f29c3faa0..2357a0295f99 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -705,6 +705,8 @@ struct drm_i915_private { struct i915_perf perf; + struct i915_hwmon *hwmon; + /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ struct intel_gt gt0; diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c new file mode 100644 index 000000000000..2ef40b0c1e70 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2022 Intel Corporation + */ + +/* + * Power-related hwmon entries. + */ + +#include +#include +#include + +#include "i915_hwmon.h" +#include "i915_drv.h" +#include "intel_mchbar_regs.h" + + +struct i915_hwmon_reg { +}; + +struct i915_hwmon_drvdata { + struct i915_hwmon *hwmon; + struct intel_uncore *uncore; + struct device *hwmon_dev; + char name[12]; +}; + +struct i915_hwmon { + struct i915_hwmon_drvdata ddat; + struct mutex hwmon_lock; /* counter overflow logic and rmw */ + struct i915_hwmon_reg rg; +}; + +static struct attribute *hwmon_attributes[] = { + NULL +}; + +static umode_t hwmon_attributes_visible(struct kobject *kobj, + struct attribute *attr, int index) +{ + return 0; +} + +static const struct attribute_group hwmon_attrgroup = { + .attrs = hwmon_attributes, + .is_visible = hwmon_attributes_visible, +}; + +static const struct attribute_group *hwmon_groups[] = { + &hwmon_attrgroup, + NULL +}; + + +static const struct hwmon_channel_info *i915_info[] = { + NULL +}; + +static umode_t +i915_is_visible(const void *drvdata, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + default: + return 0; + } +} + +static int +i915_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, + int channel, long *val) +{ + switch (type) { + default: + return -EOPNOTSUPP; + } +} + +static int +i915_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, + int channel, long val) +{ + switch (type) { + default: + return -EOPNOTSUPP; + } +} + +static const struct hwmon_ops i915_hwmon_ops = { + .is_visible = i915_is_visible, + .read = i915_read, + .write = i915_write, +}; + +static const struct hwmon_chip_info i915_chip_info = { + .ops = &i915_hwmon_ops, + .info = i915_info, +}; + +static void +i915_hwmon_get_preregistration_info(struct drm_i915_private *i915) +{ + +} + +void i915_hwmon_register(struct drm_i915_private *i915) +{ + struct device *dev = i915->drm.dev; + struct i915_hwmon *hwmon; + struct device *hwmon_dev; + struct i915_hwmon_drvdata *ddat; + + hwmon = kzalloc(sizeof(*hwmon), GFP_KERNEL); + if (!hwmon) + return; + + i915->hwmon = hwmon; + + mutex_init(&hwmon->hwmon_lock); + + ddat = &hwmon->ddat; + + ddat->hwmon = hwmon; + ddat->uncore = &i915->uncore; + snprintf(ddat->name, sizeof(ddat->name), "i915"); + + i915_hwmon_get_preregistration_info(i915); + + /* hwmon_dev points to device hwmon */ + hwmon_dev = hwmon_device_register_with_info(dev, ddat->name, + ddat, + &i915_chip_info, + hwmon_groups); + + if (IS_ERR(hwmon_dev)) { + mutex_destroy(&hwmon->hwmon_lock); + i915->hwmon = NULL; + kfree(hwmon); + return; + } + + ddat->hwmon_dev = hwmon_dev; +} + +void i915_hwmon_unregister(struct drm_i915_private *i915) +{ + struct i915_hwmon *hwmon; + struct i915_hwmon_drvdata *ddat; + + hwmon = fetch_and_zero(&i915->hwmon); + if (!hwmon) + return; + + ddat = &hwmon->ddat; + + if (ddat->hwmon_dev) + hwmon_device_unregister(ddat->hwmon_dev); + + mutex_destroy(&hwmon->hwmon_lock); + + kfree(hwmon); +} diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h new file mode 100644 index 000000000000..1e7e2516a981 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_hwmon.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ + +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef __I915_HWMON_H__ +#define __I915_HWMON_H__ + +#include +#include +#include +#include "i915_reg.h" + +struct drm_i915_private; +struct i915_hwmon; + +void i915_hwmon_register(struct drm_i915_private *i915); +void i915_hwmon_unregister(struct drm_i915_private *i915); + +#endif /* __I915_HWMON_H__ */ From patchwork Mon Jun 20 20:46:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nilawar, Badal" X-Patchwork-Id: 12888238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17C0EC433EF for ; Mon, 20 Jun 2022 20:47:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B169110E305; Mon, 20 Jun 2022 20:47:05 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 17E4D10E305 for ; Mon, 20 Jun 2022 20:47:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655758024; x=1687294024; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=y/uNCIZaLz22zf1BxHs33T9ILA4EiCh7IPkE3oYgg8A=; b=ECGVN7NvpdTVdHWUF6xx4EI4/W+VQStumwbpXEOaRwYfrtIFiUtmZJtp CAxcbyHLsUnVruF3Knmh0Q02rpfeTXZH6/3NL/5gIIkb4/Ms1dR+mIoGB FwTbjN6NwLPUySOok7P3F+PiH3EHlg2UTZKzmunkBePSs76pJAa3bten9 JPvNZX6DFuGMAUrumf4owY5lJi4dTVBoJ3dVGStwrkeqoe+uXvBsVema7 BsOoGcBJYohO+/FBIwA0Me8uwycTz0Lcmt37snQGIwtC3YTe4PFiNWO7p r2LsdFNRkFCRp00KDhm+Wx9LvU1MWLhVLT1AxyxokHnVxvcOu30WiHS3E A==; X-IronPort-AV: E=McAfee;i="6400,9594,10384"; a="259792755" X-IronPort-AV: E=Sophos;i="5.92,207,1650956400"; d="scan'208";a="259792755" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2022 13:47:03 -0700 X-IronPort-AV: E=Sophos;i="5.92,207,1650956400"; d="scan'208";a="620226955" Received: from bnilawar-desk.iind.intel.com ([10.145.162.36]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2022 13:47:01 -0700 From: Badal Nilawar To: intel-gfx@lists.freedesktop.org Date: Tue, 21 Jun 2022 02:16:47 +0530 Message-Id: <20220620204649.894703-3-badal.nilawar@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220620204649.894703-1-badal.nilawar@intel.com> References: <20220620204649.894703-1-badal.nilawar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/hwmon: Add HWMON current voltage support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-hwmon@vger.kernel.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Riana Tauro As part of the System Managemenent Interface (SMI), use the HWMON subsystem to display current voltage v2: - Updated date and kernel version in feature description - Fixed review comments (Ashutosh) Cc: Anshuman Gupta Signed-off-by: Riana Tauro Signed-off-by: Badal Nilawar --- .../ABI/testing/sysfs-driver-intel-i915-hwmon | 7 +++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 + drivers/gpu/drm/i915/i915_hwmon.c | 63 +++++++++++++++++++ 3 files changed, 73 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon new file mode 100644 index 000000000000..24c4b7477d51 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon @@ -0,0 +1,7 @@ +What: /sys/devices/.../hwmon/hwmon/in0_input +Date: June 2022 +KernelVersion: 5.19 +Contact: dri-devel@lists.freedesktop.org +Description: RO. Current Voltage in millivolt. + + Only supported for particular Intel i915 graphics platforms. diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 07ef111947b8..63a39e1e00e2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1487,6 +1487,9 @@ #define VLV_RENDER_C0_COUNT _MMIO(0x138118) #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c) +#define GEN12_RPSTAT1 _MMIO(0x1381b4) +#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) + #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) #define GEN11_CSME (31) #define GEN11_GUNIT (28) diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c index 2ef40b0c1e70..fc06db790243 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.c +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -14,9 +14,11 @@ #include "i915_hwmon.h" #include "i915_drv.h" #include "intel_mchbar_regs.h" +#include "gt/intel_gt_regs.h" struct i915_hwmon_reg { + i915_reg_t gt_perf_status; }; struct i915_hwmon_drvdata { @@ -53,15 +55,65 @@ static const struct attribute_group *hwmon_groups[] = { }; +/* + * HWMON SENSOR TYPE = hwmon_in + * - Voltage Input value (in0_input) + */ +static const u32 i915_config_in[] = { + HWMON_I_INPUT, + 0 +}; + +static const struct hwmon_channel_info i915_in = { + .type = hwmon_in, + .config = i915_config_in, +}; + static const struct hwmon_channel_info *i915_info[] = { + &i915_in, NULL }; +static umode_t +i915_in_is_visible(const struct i915_hwmon_drvdata *ddat, u32 attr) +{ + struct drm_i915_private *i915 = ddat->uncore->i915; + + switch (attr) { + case hwmon_in_input: + return (IS_DG1(i915) || IS_DG2(i915)) ? 0444 : 0; + default: + return 0; + } +} + +static int +i915_in_read(struct i915_hwmon_drvdata *ddat, u32 attr, long *val) +{ + struct i915_hwmon *hwmon = ddat->hwmon; + intel_wakeref_t wakeref; + u32 reg_value; + + switch (attr) { + case hwmon_in_input: + with_intel_runtime_pm(ddat->uncore->rpm, wakeref) + reg_value = intel_uncore_read(ddat->uncore, hwmon->rg.gt_perf_status); + *val = DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) * 25, 10); + return 0; + default: + return -EOPNOTSUPP; + } +} + static umode_t i915_is_visible(const void *drvdata, enum hwmon_sensor_types type, u32 attr, int channel) { + struct i915_hwmon_drvdata *ddat = (struct i915_hwmon_drvdata *)drvdata; + switch (type) { + case hwmon_in: + return i915_in_is_visible(ddat, attr); default: return 0; } @@ -71,7 +123,11 @@ static int i915_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long *val) { + struct i915_hwmon_drvdata *ddat = dev_get_drvdata(dev); + switch (type) { + case hwmon_in: + return i915_in_read(ddat, attr, val); default: return -EOPNOTSUPP; } @@ -101,6 +157,13 @@ static const struct hwmon_chip_info i915_chip_info = { static void i915_hwmon_get_preregistration_info(struct drm_i915_private *i915) { + struct i915_hwmon *hwmon = i915->hwmon; + + if (IS_DG1(i915) || IS_DG2(i915)) { + hwmon->rg.gt_perf_status = GEN12_RPSTAT1; + } else { + hwmon->rg.gt_perf_status = INVALID_MMIO_REG; + } } From patchwork Mon Jun 20 20:46:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nilawar, Badal" X-Patchwork-Id: 12888239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F98FC43334 for ; Mon, 20 Jun 2022 20:47:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F3A4C10E391; Mon, 20 Jun 2022 20:47:08 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id C3D8A10E391 for ; Mon, 20 Jun 2022 20:47:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; 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20 Jun 2022 13:47:03 -0700 From: Badal Nilawar To: intel-gfx@lists.freedesktop.org Date: Tue, 21 Jun 2022 02:16:48 +0530 Message-Id: <20220620204649.894703-4-badal.nilawar@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220620204649.894703-1-badal.nilawar@intel.com> References: <20220620204649.894703-1-badal.nilawar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/hwmon: Add HWMON power sensor support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-hwmon@vger.kernel.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Dale B Stimson As part of the System Managemenent Interface (SMI), use the HWMON subsystem to display power utilization. v2: - Fix review comments (Ashutosh) - Do not restore power1_max upon module unload/load sequence because on production systems modules are always loaded and not unloaded/reloaded (Ashutosh) - Fix review comments (Jani) - Remove endianness conversion (Ashutosh) Signed-off-by: Dale B Stimson Signed-off-by: Ashutosh Dixit Signed-off-by: Riana Tauro Signed-off-by: Badal Nilawar --- .../ABI/testing/sysfs-driver-intel-i915-hwmon | 20 ++ drivers/gpu/drm/i915/i915_hwmon.c | 226 +++++++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 15 ++ drivers/gpu/drm/i915/intel_mchbar_regs.h | 7 + 4 files changed, 267 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon index 24c4b7477d51..945f472dd4a2 100644 --- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon @@ -5,3 +5,23 @@ Contact: dri-devel@lists.freedesktop.org Description: RO. Current Voltage in millivolt. Only supported for particular Intel i915 graphics platforms. + +What: /sys/devices/.../hwmon/hwmon/power1_max +Date: June 2022 +KernelVersion: 5.19 +Contact: dri-devel@lists.freedesktop.org +Description: RW. Card reactive sustained (PL1/Tau) power limit in microwatts. + + The power controller will throttle the operating frequency + if the power averaged over a window (typically seconds) + exceeds this limit. + + Only supported for particular Intel i915 graphics platforms. + +What: /sys/devices/.../hwmon/hwmon/power1_max_default +Date: June 2022 +KernelVersion: 5.19 +Contact: dri-devel@lists.freedesktop.org +Description: RO. Card default power limit (default TDP setting). + + Only supported for particular Intel i915 graphics platforms. diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c index fc06db790243..75935a55f573 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.c +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -16,9 +16,22 @@ #include "intel_mchbar_regs.h" #include "gt/intel_gt_regs.h" +/* + * SF_* - scale factors for particular quantities according to hwmon spec. + * - power - microwatts + */ +#define SF_POWER 1000000 + +#define FIELD_SHIFT(__mask) \ + (BUILD_BUG_ON_ZERO(!__builtin_constant_p(__mask)) + \ + BUILD_BUG_ON_ZERO((__mask) == 0) + \ + __bf_shf(__mask)) struct i915_hwmon_reg { i915_reg_t gt_perf_status; + i915_reg_t pkg_power_sku_unit; + i915_reg_t pkg_power_sku; + i915_reg_t pkg_rapl_limit; }; struct i915_hwmon_drvdata { @@ -30,18 +43,127 @@ struct i915_hwmon_drvdata { struct i915_hwmon { struct i915_hwmon_drvdata ddat; + struct mutex hwmon_lock; /* counter overflow logic and rmw */ + struct i915_hwmon_reg rg; + + u32 power_max_initial_value; + + int scl_shift_power; }; +static void +_locked_with_pm_intel_uncore_rmw(struct i915_hwmon_drvdata *ddat, + i915_reg_t reg, u32 clear, u32 set) +{ + struct i915_hwmon *hwmon = ddat->hwmon; + struct intel_uncore *uncore = ddat->uncore; + intel_wakeref_t wakeref; + + mutex_lock(&hwmon->hwmon_lock); + + with_intel_runtime_pm(uncore->rpm, wakeref) + intel_uncore_rmw(uncore, reg, clear, set); + + mutex_unlock(&hwmon->hwmon_lock); +} + +static u64 +_scale_and_shift(u32 in, u32 scale_factor, int nshift) +{ + u64 out = mul_u32_u32(scale_factor, in); + + /* Shift, rounding to nearest */ + if (nshift > 0) + out = (out + (1 << (nshift - 1))) >> nshift; + return out; +} + +/* + * This function's return type of u64 allows for the case where the scaling + * of the field taken from the 32-bit register value might cause a result to + * exceed 32 bits. + */ +static u64 +_field_read_and_scale(struct i915_hwmon_drvdata *ddat, i915_reg_t rgadr, + u32 field_msk, int field_shift, + int nshift, u32 scale_factor) +{ + struct intel_uncore *uncore = ddat->uncore; + intel_wakeref_t wakeref; + u32 reg_value; + + with_intel_runtime_pm(uncore->rpm, wakeref) + reg_value = intel_uncore_read(uncore, rgadr); + + reg_value = (reg_value & field_msk) >> field_shift; + + return _scale_and_shift(reg_value, scale_factor, nshift); +} + +static void +_field_scale_and_write(struct i915_hwmon_drvdata *ddat, i915_reg_t rgadr, + u32 field_msk, int field_shift, + int nshift, unsigned int scale_factor, long lval) +{ + u32 nval; + u32 bits_to_clear; + u32 bits_to_set; + + /* Computation in 64-bits to avoid overflow. Round to nearest. */ + nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor); + + bits_to_clear = field_msk; + bits_to_set = (nval << field_shift) & field_msk; + + _locked_with_pm_intel_uncore_rmw(ddat, rgadr, + bits_to_clear, bits_to_set); +} + +static ssize_t +i915_power1_max_default_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct i915_hwmon_drvdata *ddat = dev_get_drvdata(dev); + struct i915_hwmon *hwmon = ddat->hwmon; + u64 val = 0; /* uapi specifies to keep visible but return 0 if unsupported */ + + if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku)) + val = _field_read_and_scale(ddat, + hwmon->rg.pkg_power_sku, + PKG_PKG_TDP, + FIELD_SHIFT(PKG_PKG_TDP), + hwmon->scl_shift_power, + SF_POWER); + return sysfs_emit(buf, "%llu\n", val); +} + +static SENSOR_DEVICE_ATTR(power1_max_default, 0444, + i915_power1_max_default_show, NULL, 0); + static struct attribute *hwmon_attributes[] = { + &sensor_dev_attr_power1_max_default.dev_attr.attr, NULL }; static umode_t hwmon_attributes_visible(struct kobject *kobj, struct attribute *attr, int index) { - return 0; + struct device *dev = kobj_to_dev(kobj); + struct i915_hwmon_drvdata *ddat = dev_get_drvdata(dev); + struct drm_i915_private *i915 = ddat->uncore->i915; + i915_reg_t rgadr; + + if (attr == &sensor_dev_attr_power1_max_default.dev_attr.attr) + return IS_DGFX(i915) ? attr->mode : 0; + else + return 0; + + if (!i915_mmio_reg_valid(rgadr)) + return 0; + + return attr->mode; } static const struct attribute_group hwmon_attrgroup = { @@ -54,6 +176,19 @@ static const struct attribute_group *hwmon_groups[] = { NULL }; +/* + * HWMON SENSOR TYPE = hwmon_power + * - Sustained Power (power1_max) + */ +static const u32 i915_config_power[] = { + HWMON_P_MAX, + 0 +}; + +static const struct hwmon_channel_info i915_power = { + .type = hwmon_power, + .config = i915_config_power, +}; /* * HWMON SENSOR TYPE = hwmon_in @@ -71,6 +206,7 @@ static const struct hwmon_channel_info i915_in = { static const struct hwmon_channel_info *i915_info[] = { &i915_in, + &i915_power, NULL }; @@ -87,6 +223,21 @@ i915_in_is_visible(const struct i915_hwmon_drvdata *ddat, u32 attr) } } +static umode_t +i915_power_is_visible(const struct i915_hwmon_drvdata *ddat, u32 attr, int chan) +{ + struct i915_hwmon *hwmon = ddat->hwmon; + + switch (attr) { + case hwmon_power_max: + if (i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) + return 0664; + return 0; + default: + return 0; + } +} + static int i915_in_read(struct i915_hwmon_drvdata *ddat, u32 attr, long *val) { @@ -105,6 +256,44 @@ i915_in_read(struct i915_hwmon_drvdata *ddat, u32 attr, long *val) } } +static int +i915_power_read(struct i915_hwmon_drvdata *ddat, u32 attr, int chan, long *val) +{ + struct i915_hwmon *hwmon = ddat->hwmon; + + switch (attr) { + case hwmon_power_max: + *val = _field_read_and_scale(ddat, + hwmon->rg.pkg_rapl_limit, + PKG_PWR_LIM_1, + FIELD_SHIFT(PKG_PWR_LIM_1), + hwmon->scl_shift_power, + SF_POWER); + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int +i915_power_write(struct i915_hwmon_drvdata *ddat, u32 attr, int chan, long val) +{ + struct i915_hwmon *hwmon = ddat->hwmon; + + switch (attr) { + case hwmon_power_max: + _field_scale_and_write(ddat, + hwmon->rg.pkg_rapl_limit, + PKG_PWR_LIM_1, + FIELD_SHIFT(PKG_PWR_LIM_1), + hwmon->scl_shift_power, + SF_POWER, val); + return 0; + default: + return -EOPNOTSUPP; + } +} + static umode_t i915_is_visible(const void *drvdata, enum hwmon_sensor_types type, u32 attr, int channel) @@ -114,6 +303,8 @@ i915_is_visible(const void *drvdata, enum hwmon_sensor_types type, switch (type) { case hwmon_in: return i915_in_is_visible(ddat, attr); + case hwmon_power: + return i915_power_is_visible(ddat, attr, channel); default: return 0; } @@ -128,6 +319,8 @@ i915_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, switch (type) { case hwmon_in: return i915_in_read(ddat, attr, val); + case hwmon_power: + return i915_power_read(ddat, attr, channel, val); default: return -EOPNOTSUPP; } @@ -137,7 +330,11 @@ static int i915_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long val) { + struct i915_hwmon_drvdata *ddat = dev_get_drvdata(dev); + switch (type) { + case hwmon_power: + return i915_power_write(ddat, attr, channel, val); default: return -EOPNOTSUPP; } @@ -158,13 +355,40 @@ static void i915_hwmon_get_preregistration_info(struct drm_i915_private *i915) { struct i915_hwmon *hwmon = i915->hwmon; + struct intel_uncore *uncore = &i915->uncore; + intel_wakeref_t wakeref; + u32 val_sku_unit; if (IS_DG1(i915) || IS_DG2(i915)) { hwmon->rg.gt_perf_status = GEN12_RPSTAT1; + hwmon->rg.pkg_power_sku_unit = PCU_PACKAGE_POWER_SKU_UNIT; + hwmon->rg.pkg_power_sku = INVALID_MMIO_REG; + hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT; } else { hwmon->rg.gt_perf_status = INVALID_MMIO_REG; + hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG; + hwmon->rg.pkg_power_sku = INVALID_MMIO_REG; + hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG; } + + with_intel_runtime_pm(uncore->rpm, wakeref) { + /* + * The contents of register hwmon->rg.pkg_power_sku_unit do not change, + * so read it once and store the shift values. + * + * For some platforms, this value is defined as available "for all + * tiles", with the values consistent across all tiles. + * In this case, use the tile 0 value for all. + */ + if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku_unit)) { + val_sku_unit = intel_uncore_read(uncore, + hwmon->rg.pkg_power_sku_unit); + } else + val_sku_unit = 0; + + hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); + } } void i915_hwmon_register(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 932bd6aa4a0a..4809565a3454 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1866,6 +1866,21 @@ #define POWER_LIMIT_4_MASK REG_BIT(9) #define POWER_LIMIT_1_MASK REG_BIT(11) #define POWER_LIMIT_2_MASK REG_BIT(12) +/* + * *_PACKAGE_POWER_SKU - SKU power and timing parameters. + * Used herein as a 64-bit register. + * These masks are defined using GENMASK_ULL as REG_GENMASK is limited to u32 + * and as GENMASK is "long" and therefore 32-bits on a 32-bit system. + * PKG_PKG_TDP, PKG_MIN_PWR, and PKG_MAX_PWR are scaled in the same way as + * PKG_PWR_LIM_*, above. + * PKG_MAX_WIN has sub-fields for x and y, and has the value: is 1.x * 2^y. + */ +#define PKG_PKG_TDP GENMASK_ULL(14, 0) +#define PKG_MIN_PWR GENMASK_ULL(30, 16) +#define PKG_MAX_PWR GENMASK_ULL(46, 32) +#define PKG_MAX_WIN GENMASK_ULL(54, 48) +#define PKG_MAX_WIN_Y GENMASK_ULL(54, 53) +#define PKG_MAX_WIN_X GENMASK_ULL(52, 48) #define CHV_CLK_CTL1 _MMIO(0x101100) #define VLV_CLK_CTL2 _MMIO(0x101104) diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h index 2aad2f0cc8db..a3eccdee0ca4 100644 --- a/drivers/gpu/drm/i915/intel_mchbar_regs.h +++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h @@ -191,11 +191,18 @@ #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) +#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938) +#define PKG_PWR_UNIT REG_GENMASK(3, 0) +#define PKG_TIME_UNIT REG_GENMASK(19, 16) + #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) #define RP0_CAP_MASK REG_GENMASK(7, 0) #define RP1_CAP_MASK REG_GENMASK(15, 8) #define RPN_CAP_MASK REG_GENMASK(23, 16) +#define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0) +#define PKG_PWR_LIM_1 REG_GENMASK(14, 0) + /* snb MCH registers for priority tuning */ #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56) From patchwork Mon Jun 20 20:46:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nilawar, Badal" X-Patchwork-Id: 12888240 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8DCE9CCA480 for ; Mon, 20 Jun 2022 20:47:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 06C3B10E50F; Mon, 20 Jun 2022 20:47:11 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 432BB10E50F for ; Mon, 20 Jun 2022 20:47:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655758029; x=1687294029; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HDmo7oG5UPLJRAlW40rts+cDQmS0+J0NXy4Frz1F8DY=; b=DuzQKzUN+Y5QusOCpxhRhp5i5Xjhusp01eSfq/oGD3PhnFYpcNklq1Li BCF3E2YAD5l4KBG79jsZwvHjDwEUR3cZEy4AERevOqNYMjKA/IyoNLEiI PCbixYyMiUJT6Wkw+ZX+VE13YM+wgzpfBBM5H0Y/LVpq2YLt6xXz2Xlnu qEr+eE9oCHcElcNfUixyqiPROlLNCV0GAwzKQx/JeYmWH6ZYsSJ09lRqM jes70Uzeu1S5EoUGJfhlGLswbAj/kUx8cj2hS5eyQi9bQcbzzdh5AaYrt bDeLsMENwMVmxY2Qh6/xbBbtIRmUIToLFIy9SRy0OuWKERusjM9zDmnCW Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10384"; a="259792761" X-IronPort-AV: E=Sophos;i="5.92,207,1650956400"; d="scan'208";a="259792761" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2022 13:47:08 -0700 X-IronPort-AV: E=Sophos;i="5.92,207,1650956400"; d="scan'208";a="620226979" Received: from bnilawar-desk.iind.intel.com ([10.145.162.36]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2022 13:47:06 -0700 From: Badal Nilawar To: intel-gfx@lists.freedesktop.org Date: Tue, 21 Jun 2022 02:16:49 +0530 Message-Id: <20220620204649.894703-5-badal.nilawar@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220620204649.894703-1-badal.nilawar@intel.com> References: <20220620204649.894703-1-badal.nilawar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915/hwmon: Add HWMON energy support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-hwmon@vger.kernel.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Dale B Stimson As part of the System Managemenent Interface (SMI), use the HWMON subsystem to display energy utilization v2: - Updated the date and kernel version in feature description Signed-off-by: Dale B Stimson Signed-off-by: Ashutosh Dixit Signed-off-by: Riana Tauro Signed-off-by: Badal Nilawar --- .../ABI/testing/sysfs-driver-intel-i915-hwmon | 16 ++ drivers/gpu/drm/i915/i915_hwmon.c | 174 +++++++++++++++++- drivers/gpu/drm/i915/i915_hwmon.h | 1 + drivers/gpu/drm/i915/intel_mchbar_regs.h | 2 + 4 files changed, 185 insertions(+), 8 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon index 945f472dd4a2..2e87d7422b73 100644 --- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon @@ -25,3 +25,19 @@ Contact: dri-devel@lists.freedesktop.org Description: RO. Card default power limit (default TDP setting). Only supported for particular Intel i915 graphics platforms. + +What: /sys/devices/.../hwmon/hwmon/energy1_input +Date: June 2022 +KernelVersion: 5.19 +Contact: dri-devel@lists.freedesktop.org +Description: RO. Energy input of device in microjoules. + + The returned textual representation is an unsigned integer + number that can be stored in 64-bits. Warning: The hardware + register is 32-bits wide and can overflow by wrapping around. + A single wrap-around between calls to read this value can + be detected and will be accounted for in the returned value. + At a power consumption of 1 watt, the 32-bit hardware register + would wrap-around approximately every 3 days. + + Only supported for particular Intel i915 graphics platforms. diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c index 75935a55f573..77d68f17316a 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.c +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -19,8 +19,10 @@ /* * SF_* - scale factors for particular quantities according to hwmon spec. * - power - microwatts + * - energy - microjoules */ #define SF_POWER 1000000 +#define SF_ENERGY 1000000 #define FIELD_SHIFT(__mask) \ (BUILD_BUG_ON_ZERO(!__builtin_constant_p(__mask)) + \ @@ -32,12 +34,20 @@ struct i915_hwmon_reg { i915_reg_t pkg_power_sku_unit; i915_reg_t pkg_power_sku; i915_reg_t pkg_rapl_limit; + i915_reg_t energy_status_all; + i915_reg_t energy_status_tile; +}; + +struct i915_energy_info { + u32 energy_counter_overflow; + u32 energy_counter_prev; }; struct i915_hwmon_drvdata { struct i915_hwmon *hwmon; struct intel_uncore *uncore; struct device *hwmon_dev; + struct i915_energy_info ei; /* Energy info for energy1_input */ char name[12]; }; @@ -51,6 +61,7 @@ struct i915_hwmon { u32 power_max_initial_value; int scl_shift_power; + int scl_shift_energy; }; static void @@ -121,6 +132,136 @@ _field_scale_and_write(struct i915_hwmon_drvdata *ddat, i915_reg_t rgadr, bits_to_clear, bits_to_set); } +/* + * _i915_energy1_input_sub - A custom function to obtain energy1_input. + * Use a custom function instead of the usual hwmon helpers in order to + * guarantee 64-bits of result to user-space. + * Units are microjoules. + * + * The underlying hardware register is 32-bits and is subject to overflow. + * This function compensates for overflow of the 32-bit register by detecting + * wrap-around and incrementing an overflow counter. + * This only works if the register is sampled often enough to avoid + * missing an instance of overflow - achieved either by repeated + * queries through the API, or via a possible timer (future - TBD) that + * ensures values are read often enough to catch all overflows. + * + * How long before overflow? For example, with an example scaling bit + * shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and a power draw of + * 1000 watts, the 32-bit counter will overflow in approximately 4.36 minutes. + * + * Examples: + * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days + * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes + */ +static int +_i915_energy1_input_sub(struct i915_hwmon_drvdata *ddat, u64 *energy) +{ + struct intel_uncore *uncore = ddat->uncore; + struct i915_hwmon *hwmon = ddat->hwmon; + struct i915_energy_info *pei = &ddat->ei; + int nshift = hwmon->scl_shift_energy; + intel_wakeref_t wakeref; + u32 reg_value; + u64 vlo; + u64 vhi; + i915_reg_t rgaddr; + + rgaddr = hwmon->rg.energy_status_all; + + if (!i915_mmio_reg_valid(rgaddr)) + return -EOPNOTSUPP; + + mutex_lock(&hwmon->hwmon_lock); + + with_intel_runtime_pm(uncore->rpm, wakeref) + reg_value = intel_uncore_read(uncore, rgaddr); + + /* + * The u32 register concatenated with the u32 overflow counter + * gives an effective energy counter size of 64-bits. However, the + * computations below are done modulo 2^96 to avoid overflow during + * scaling in the conversion to microjoules. + * + * The low-order 64-bits of the resulting quantity are returned to + * the caller in units of microjoules, encoded into a decimal string. + * + * For a power of 1000 watts, 64 bits in units of microjoules will + * overflow after 584 years. + */ + + if (pei->energy_counter_prev > reg_value) + pei->energy_counter_overflow++; + + pei->energy_counter_prev = reg_value; + + /* + * 64-bit variables vlo and vhi are used for the scaling process. + * The 96-bit counter value is composed from the two 64-bit variables + * vhi and vlo thusly: counter == vhi << 32 + vlo . + * The 32-bits of overlap between the two variables is convenient for + * handling overflows out of vlo. + */ + + vlo = reg_value; + vhi = pei->energy_counter_overflow; + + mutex_unlock(&hwmon->hwmon_lock); + + vlo = SF_ENERGY * vlo; + + /* Prepare to round to nearest */ + if (nshift > 0) + vlo += 1 << (nshift - 1); + + /* + * Anything in the upper-32 bits of vlo gets added into vhi here, + * and then cleared from vlo. + */ + vhi = (SF_ENERGY * vhi) + (vlo >> 32); + vlo &= 0xffffffffULL; + + /* + * Apply the right shift. + * - vlo shifted by itself. + * - vlo receiving what's shifted out of vhi. + * - vhi shifted by itself + */ + vlo = vlo >> nshift; + vlo |= (vhi << (32 - nshift)) & 0xffffffffULL; + vhi = vhi >> nshift; + + /* Combined to get a 64-bit result in vlo. */ + vlo |= (vhi << 32); + + *energy = vlo; + + return 0; +} + +static ssize_t +i915_energy1_input_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct i915_hwmon_drvdata *ddat = dev_get_drvdata(dev); + ssize_t ret = 0; + u64 energy; + + if (!_i915_energy1_input_sub(ddat, &energy)) + ret = sysfs_emit(buf, "%llu\n", energy); + + return ret; +} + +int +i915_energy_status_get(struct drm_i915_private *i915, u64 *energy) +{ + struct i915_hwmon *hwmon = i915->hwmon; + struct i915_hwmon_drvdata *ddat = &hwmon->ddat; + + return _i915_energy1_input_sub(ddat, energy); +} + static ssize_t i915_power1_max_default_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -141,9 +282,12 @@ i915_power1_max_default_show(struct device *dev, struct device_attribute *attr, static SENSOR_DEVICE_ATTR(power1_max_default, 0444, i915_power1_max_default_show, NULL, 0); +static SENSOR_DEVICE_ATTR(energy1_input, 0444, + i915_energy1_input_show, NULL, 0); static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_power1_max_default.dev_attr.attr, + &sensor_dev_attr_energy1_input.dev_attr.attr, NULL }; @@ -153,17 +297,15 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, struct device *dev = kobj_to_dev(kobj); struct i915_hwmon_drvdata *ddat = dev_get_drvdata(dev); struct drm_i915_private *i915 = ddat->uncore->i915; - i915_reg_t rgadr; + struct i915_hwmon *hwmon = ddat->hwmon; - if (attr == &sensor_dev_attr_power1_max_default.dev_attr.attr) + if (attr == &sensor_dev_attr_energy1_input.dev_attr.attr) + return i915_mmio_reg_valid(hwmon->rg.energy_status_all) ? + attr->mode : 0; + else if (attr == &sensor_dev_attr_power1_max_default.dev_attr.attr) return IS_DGFX(i915) ? attr->mode : 0; else return 0; - - if (!i915_mmio_reg_valid(rgadr)) - return 0; - - return attr->mode; } static const struct attribute_group hwmon_attrgroup = { @@ -356,6 +498,8 @@ i915_hwmon_get_preregistration_info(struct drm_i915_private *i915) { struct i915_hwmon *hwmon = i915->hwmon; struct intel_uncore *uncore = &i915->uncore; + struct i915_hwmon_drvdata *ddat = &hwmon->ddat; + struct i915_energy_info *pei; intel_wakeref_t wakeref; u32 val_sku_unit; @@ -364,11 +508,15 @@ i915_hwmon_get_preregistration_info(struct drm_i915_private *i915) hwmon->rg.pkg_power_sku_unit = PCU_PACKAGE_POWER_SKU_UNIT; hwmon->rg.pkg_power_sku = INVALID_MMIO_REG; hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT; + hwmon->rg.energy_status_all = PCU_PACKAGE_ENERGY_STATUS; + hwmon->rg.energy_status_tile = INVALID_MMIO_REG; } else { hwmon->rg.gt_perf_status = INVALID_MMIO_REG; hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG; hwmon->rg.pkg_power_sku = INVALID_MMIO_REG; hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG; + hwmon->rg.energy_status_all = INVALID_MMIO_REG; + hwmon->rg.energy_status_tile = INVALID_MMIO_REG; } @@ -387,8 +535,18 @@ i915_hwmon_get_preregistration_info(struct drm_i915_private *i915) } else val_sku_unit = 0; - hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); + pei = &ddat->ei; + pei->energy_counter_overflow = 0; + + if (i915_mmio_reg_valid(hwmon->rg.energy_status_all)) + pei->energy_counter_prev = + intel_uncore_read(uncore, hwmon->rg.energy_status_all); + else + pei->energy_counter_prev = 0; } + + hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); + hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit); } void i915_hwmon_register(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h index 1e7e2516a981..5a15c84e4721 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.h +++ b/drivers/gpu/drm/i915/i915_hwmon.h @@ -18,4 +18,5 @@ struct i915_hwmon; void i915_hwmon_register(struct drm_i915_private *i915); void i915_hwmon_unregister(struct drm_i915_private *i915); +int i915_energy_status_get(struct drm_i915_private *i915, u64 *energy); #endif /* __I915_HWMON_H__ */ diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h index a3eccdee0ca4..3f2fc62ebb68 100644 --- a/drivers/gpu/drm/i915/intel_mchbar_regs.h +++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h @@ -193,7 +193,9 @@ #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) #define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938) #define PKG_PWR_UNIT REG_GENMASK(3, 0) +#define PKG_ENERGY_UNIT REG_GENMASK(12, 8) #define PKG_TIME_UNIT REG_GENMASK(19, 16) +#define PCU_PACKAGE_ENERGY_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x593c) #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) #define RP0_CAP_MASK REG_GENMASK(7, 0)