From patchwork Mon Jun 20 20:15:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dao Lu X-Patchwork-Id: 12888248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65830C43334 for ; Mon, 20 Jun 2022 20:51:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=rWAczI3/9QDnk59GMv4rkRcAGaDJv7RqIIPDJ27lNlk=; b=msHcPDLeW9eJLL wCFDZ58v2AkIuIhqi1wUwYW/aHAEApPuCbirsqVTa/tT/JU5tQ8rOngPOda79zPPlnUZtHLvNrXLx 6wx2jdqTIIDeFsCeEQelG3CawvQAcDtZDX0Pmtio6wi5Is6EgkXl+qe5jXW1MpNGpw0dHqW9FZO4H vmhO7+LIhQPeMM0y6b6PGmChDBc3eWZP4QxLjsRdPp06/bl7pkLP/nVYqtsbQrJKs4F4F9CQHLlmK XVbHA/merK7ksMpsnEAsQXR96bLQv1YOGAbvhNYIAn4JhjZVeDVfFiaEniQbGRlh0jiLxgt2QIWI4 lRqxi+2RMPRCNmYjAXog==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3OMO-002Pqy-66; Mon, 20 Jun 2022 20:51:00 +0000 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3NoP-002DCD-L1 for linux-riscv@lists.infradead.org; Mon, 20 Jun 2022 20:15:55 +0000 Received: by mail-pj1-x1032.google.com with SMTP id hv24-20020a17090ae41800b001e33eebdb5dso12709213pjb.0 for ; Mon, 20 Jun 2022 13:15:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/uXSwA0VZB6Kj6viZ1pio+RknHlDBNIYrHuFvQS4534=; b=m0Na8RynXQcTYFciNnM0ONTDVLxYrmfFLuUcIA+c+dIpYZ4o6lmEhs74xjC0zhgkgY evd8ymXCStFOxOWDOX+IbjWCdaVRzBZUozy38WVpd1xSNDgNh5dp3+R9jsw7Qp6CBtao x2CdTeAtBpe4S7ObCy/ylj4SrcKooxyhT2SaGCvneJkoAW2v54noquIqCHb/ZkcMOPIr 2A+Y1ydfVegVG5Bn+JTU1V7qzOLGJAggK5TR4YMBmui6RxjIxZCypDNz3L/Eno/1upzx qeg1mAyc7i7zTAN1BzgVOSPJE1zXASinn/C8V7EfeQ9ySVfDVLFD3AtDSpx0OkbMACjQ mviw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/uXSwA0VZB6Kj6viZ1pio+RknHlDBNIYrHuFvQS4534=; b=fCFpRPaoqt3ejoZOP3+zuvmaLseruFC+4h+UrdVga1VIyoQqVWAoZjfybFeryRHz2Z HWgxR0/7M9F+HVjuTgOqmfh6sZYN68c19pchfkV5+0V0yP7gOh/5mkikAum68QuLbhrV VItbu6l8HIxhfar/bnwlMxTX9QABAZbvLFqKnLLOSUSKMmT8fxqPJh6mZ2ve+57fueWX LLsnKFa9wSBUWiEPDFTz5EjWepEYvAUwQMSYsXdiXcT42qi4oh+hU32URSmgTuuAjD5t 5hNzHRJV0aEFXlwmPUaoA8+NdJ4BPs0LySWv0GveHlaGuo8l37YcDzKEiuSUixY+g5Lx xxbw== X-Gm-Message-State: AJIora+pfA+sQWJFPEB05zfw8tsZ4Z+UgB0f4WW1BkkkxsDL6Y8WCgsJ 23ZEDxE+tOrs001AEfxdDB83hQ== X-Google-Smtp-Source: AGRyM1sAU1g7ytax5AFtdYQfP7PBW7mMd7BoA3S69gJnn8PUyTTUi5mos6/drT1yTiaqtVdKd2Tu5Q== X-Received: by 2002:a17:902:ea12:b0:168:faa0:509b with SMTP id s18-20020a170902ea1200b00168faa0509bmr25351023plg.150.1655756151197; Mon, 20 Jun 2022 13:15:51 -0700 (PDT) Received: from daolu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id p16-20020a170903249000b00163f1831ddfsm9119071plw.40.2022.06.20.13.15.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:15:50 -0700 (PDT) From: Dao Lu To: linux-kernel@vger.kernel.org Cc: Dao Lu , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Guo Ren , Jisheng Zhang , Randy Dunlap , Niklas Cassel , Qinglin Pan , Alexandre Ghiti , Rob Herring , Tsukasa OI , Yury Norov , linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE) Subject: [PATCH v4] arch/riscv: add Zihintpause support Date: Mon, 20 Jun 2022 13:15:25 -0700 Message-Id: <20220620201530.3929352-1-daolu@rivosinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220620_131553_847608_65AF714F X-CRM114-Status: GOOD ( 18.51 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Implement support for the ZiHintPause extension. The PAUSE instruction is a HINT that indicates the current hart’s rate of instruction retirement should be temporarily reduced or paused. Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Signed-off-by: Dao Lu Reviewed-by: Guo Ren Reviewed-by: Atish Patra Reviewed-by: Jisheng Zhang --- v1 -> v2: Remove the usage of static branch, use PAUSE if toolchain supports it v2 -> v3: Added the static branch back, cpu_relax() behavior is kept the same for systems that do not support ZiHintPause v3 -> v4: Adopted the newly added unified static keys for extensions --- arch/riscv/Makefile | 4 ++++ arch/riscv/include/asm/hwcap.h | 5 +++++ arch/riscv/include/asm/vdso/processor.h | 21 ++++++++++++++++++--- arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 1 + 5 files changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 34cf8a598617..6ddacc6f44b9 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei +# Check if the toolchain supports Zihintpause extension +toolchain-supports-zihintpause := $(call cc-option-yn, -march=$(riscv-march-y)_zihintpause) +riscv-march-$(toolchain-supports-zihintpause) := $(riscv-march-y)_zihintpause + KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) KBUILD_AFLAGS += -march=$(riscv-march-y) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e48eebdd2631..dc47019a0b38 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -8,6 +8,7 @@ #ifndef _ASM_RISCV_HWCAP_H #define _ASM_RISCV_HWCAP_H +#include #include #include @@ -54,6 +55,7 @@ extern unsigned long elf_hwcap; enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_SVPBMT, + RISCV_ISA_EXT_ZIHINTPAUSE, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; @@ -64,6 +66,7 @@ enum riscv_isa_ext_id { */ enum riscv_isa_ext_key { RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */ + RISCV_ISA_EXT_KEY_ZIHINTPAUSE, RISCV_ISA_EXT_KEY_MAX, }; @@ -83,6 +86,8 @@ static __always_inline int riscv_isa_ext2key(int num) return RISCV_ISA_EXT_KEY_FPU; case RISCV_ISA_EXT_d: return RISCV_ISA_EXT_KEY_FPU; + case RISCV_ISA_EXT_ZIHINTPAUSE: + return RISCV_ISA_EXT_KEY_ZIHINTPAUSE; default: return -EINVAL; } diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h index 134388cbaaa1..1e4f8b4aef79 100644 --- a/arch/riscv/include/asm/vdso/processor.h +++ b/arch/riscv/include/asm/vdso/processor.h @@ -4,15 +4,30 @@ #ifndef __ASSEMBLY__ +#include #include +#include static inline void cpu_relax(void) { + if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) { #ifdef __riscv_muldiv - int dummy; - /* In lieu of a halt instruction, induce a long-latency stall. */ - __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); + int dummy; + /* In lieu of a halt instruction, induce a long-latency stall. */ + __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); #endif + } else { + /* + * Reduce instruction retirement. + * This assumes the PC changes. + */ +#ifdef __riscv_zihintpause + __asm__ __volatile__ ("pause"); +#else + /* Encoding of the pause instruction */ + __asm__ __volatile__ (".4byte 0x100000F"); +#endif + } barrier(); } diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index fba9e9f46a8c..a123e92b14dd 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node) static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1b3ec44e25f5..708df2c0bc34 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -198,6 +198,7 @@ void __init riscv_fill_hwcap(void) } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); + SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); } #undef SET_ISA_EXT_MAP }