From patchwork Tue Jun 21 16:06:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12889482 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79188C433EF for ; Tue, 21 Jun 2022 16:07:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353553AbiFUQHD (ORCPT ); Tue, 21 Jun 2022 12:07:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353533AbiFUQHC (ORCPT ); Tue, 21 Jun 2022 12:07:02 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9CA3F1E; Tue, 21 Jun 2022 09:07:01 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id z11so13869811edp.9; Tue, 21 Jun 2022 09:07:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YKqPjvnqn/BfVGE7rmt0Y6NyBVZf/KJRsjpNtw4RE3c=; b=dz7WmkSt2aBv/t4ECJFou+3jvdVpb7oFa9WWzezlhyydmuPbHkDsJbQ2sRLJMpDdJv yxpwRK1TU1fkoMjMYYyCUS/MRx4Cb4KbpW2/zpeW7Igk0lVT9ZdKJnF9uoLF1wRvyF/2 4ECWBA4Y/ZlyDICPsbVVzl5EybvL0QVZ0WGUeCTGjCq7G11OSnHVPKBH/cbJpdxFnsSM tPyntE+WbWm6rh+hfvaFkgx0O/5TDOykL4LgPhXvqTKjCavmU4ycTUiypQc5CVHc9xlI YqNbZVWddayGAfD2IzxhxkjimFG3FOIbUv1T2gKV23Pes8l0x26vXtfPpUhc/2kaVUH7 K1DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YKqPjvnqn/BfVGE7rmt0Y6NyBVZf/KJRsjpNtw4RE3c=; b=HSJAa0/TThZnYMRiTJ++fukDGoNVfydJumeM3dSei0cuzFhRNMwFZBucUryRrr87FO +b9GBH2DOk3VnGzfQN02j4xcXqPjIkHgOWkyz9hbTpyfbI22NBMbXGKiMqcsfxlByW+q XGxQaX5UtlKZ3VVIOamr985RlLIGvrlgFtV5IoajYQrGRjUeBtUJs9Rhvrgas5CrPuO2 eR3094jNFHO/ZmdtIwSQP9nS3Py4CvHaIe4VbsEj4fQsgItxoAA08M6A321xyyvRWN+j 0A5zPI+PffVzqZ2/TnpvEOfqFkk2U0vgh5S0MJrVz18OoNRg+xqDRuMM8TQz3kXENMbi MoyQ== X-Gm-Message-State: AJIora/nixjr6q4oI37nHbOKyoPz088WwPzUPj84fTaqLY2ltia341pi 5VHGTu0vLTC57W3ISoX50x0= X-Google-Smtp-Source: AGRyM1tIFkBte3j/c01tIp3DP84GCU+PwJuyxQ0Kq3nlMMo7/s307lU+hI56/3rvRFbM0GnuYukUHQ== X-Received: by 2002:a05:6402:320f:b0:435:7236:e312 with SMTP id g15-20020a056402320f00b004357236e312mr20386929eda.115.1655827620203; Tue, 21 Jun 2022 09:07:00 -0700 (PDT) Received: from localhost.localdomain ([185.107.57.61]) by smtp.gmail.com with ESMTPSA id p6-20020a17090653c600b00722e0b1fa8esm1772943ejo.164.2022.06.21.09.06.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 09:06:59 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Loic Poulain Cc: Yassine Oudjana , Yassine Oudjana , Dmitry Baryshkov , Konrad Dybcio , AngeloGioacchino Del Regno , Martin Botka , Marijn Suijten , Jami Kettunen , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] clk: qcom: msm8996-cpu: Rename DIV_2_INDEX to SMUX_INDEX Date: Tue, 21 Jun 2022 20:06:16 +0400 Message-Id: <20220621160621.24415-2-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220621160621.24415-1-y.oudjana@protonmail.com> References: <20220621160621.24415-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Yassine Oudjana The parent at this index is the secondary mux, which can connect not only to primary PLL/2 but also to XO. Rename the index to SMUX_INDEX to better reflect the parent. Signed-off-by: Yassine Oudjana Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-cpu-8996.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 4a4fde8dd12d..5dc68dc3621f 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -61,7 +61,7 @@ #include "clk-regmap.h" enum _pmux_input { - DIV_2_INDEX = 0, + SMUX_INDEX = 0, PLL_INDEX, ACD_INDEX, ALT_INDEX, @@ -468,7 +468,7 @@ static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, case POST_RATE_CHANGE: if (cnd->new_rate < DIV_2_THRESHOLD) ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, - DIV_2_INDEX); + SMUX_INDEX); else ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ACD_INDEX); From patchwork Tue Jun 21 16:06:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12889483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F94AC43334 for ; Tue, 21 Jun 2022 16:07:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353586AbiFUQHM (ORCPT ); Tue, 21 Jun 2022 12:07:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353533AbiFUQHL (ORCPT ); Tue, 21 Jun 2022 12:07:11 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B3F1F1E; Tue, 21 Jun 2022 09:07:10 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id ej4so16076983edb.7; Tue, 21 Jun 2022 09:07:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3LdhXVBayXK2e6Gfdh/Miku3QTiOMf+8T69vVZwmwlA=; b=oNA6/Va8UeNlBq3nBOHnKyoEY09VwNX0gquv7rHz0G8pJUMK5rw+T5N9F125e4Nv6R eE9pVODJ9XcLtfUyRdwKk7TqqEmAl9JFX+mpLTKvgmurUlOFQsj5VmnZsi0JYqRTRcAZ QEB2QLB0I1dL2pOeOpRmVLuv1j/dAo5b0GfCA/5/BonE/H4vOq/wE0MrU7xDHVq40JVS yxDqA+lXtLbVJ97NdZn0RiSLU7hEKo6U900Y7TxxabOw/oDRNWefFg78xjaGDqmXmeib 67gPmxgaL27SDGfI9C2H0QHENqlRCxBbozwqUTJgQpjmk7DSjNIZrMbXGEelFrtU+4s1 Or5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3LdhXVBayXK2e6Gfdh/Miku3QTiOMf+8T69vVZwmwlA=; b=T9k0V+mfGrEeoIrFFVHI7e7lx+7FB4z9opjOwkkQqPaOoVgTGslWEB92WtGTPRnkGd sq5iJGI/2m4DbLEBEzQymqJKc6JXrNG7ylXdJS9iS7APrFq9NqWisxUjvbp4v7YfW2uP xZiUH4VcLKj4nN8z38dkxBAGtszwQC9Gyt5t5LvJSiy3C2tUHrq/qldRy5/8Ksnx8iKT kkcKoVzE5qK/nM12yJRLvV0xixJ4nUORC+4e+nYU4M7AXzgc+3gtG+699h2bB89+wsV6 XaqrdcNCgA3jtW2FDTGmCmpHE24jEZ8/mttBkCT7hqtBRry49R1ObOTjQgHdGf0vzncT 987A== X-Gm-Message-State: AJIora/1tWvEsNBZOwKBlHhhfDQXUDfIflTHId9N9qxpadkl3iZbpbf+ FEZz4x3sC1e5ym9bYCaGRic= X-Google-Smtp-Source: AGRyM1tSZNwg9gxlJeS6FN1z8jYK+VAxmhC+DdcE9F7d/vK03wrbTpD1uZfRJoUn4DKeuYL3YRViNw== X-Received: by 2002:a05:6402:1386:b0:431:6911:a151 with SMTP id b6-20020a056402138600b004316911a151mr36186645edv.105.1655827628627; Tue, 21 Jun 2022 09:07:08 -0700 (PDT) Received: from localhost.localdomain ([185.107.57.61]) by smtp.gmail.com with ESMTPSA id p6-20020a17090653c600b00722e0b1fa8esm1772943ejo.164.2022.06.21.09.07.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 09:07:08 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Loic Poulain Cc: Yassine Oudjana , Yassine Oudjana , Dmitry Baryshkov , Konrad Dybcio , AngeloGioacchino Del Regno , Martin Botka , Marijn Suijten , Jami Kettunen , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] clk: qcom: msm8996-cpu: Statically define PLL dividers Date: Tue, 21 Jun 2022 20:06:17 +0400 Message-Id: <20220621160621.24415-3-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220621160621.24415-1-y.oudjana@protonmail.com> References: <20220621160621.24415-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Yassine Oudjana This will allow for adding them to clk_parent_data arrays in an upcoming patch. Signed-off-by: Yassine Oudjana Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-cpu-8996.c | 66 +++++++++++++++++++++------------ 1 file changed, 42 insertions(+), 24 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 5dc68dc3621f..217f9392c23d 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -135,6 +135,34 @@ static struct clk_alpha_pll pwrcl_pll = { }, }; +static struct clk_fixed_factor pwrcl_pll_postdiv = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "pwrcl_pll_postdiv", + .parent_data = &(const struct clk_parent_data){ + .hw = &pwrcl_pll.clkr.hw + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor perfcl_pll_postdiv = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "perfcl_pll_postdiv", + .parent_data = &(const struct clk_parent_data){ + .hw = &perfcl_pll.clkr.hw + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + static const struct pll_vco alt_pll_vco_modes[] = { VCO(3, 250000000, 500000000), VCO(2, 500000000, 750000000), @@ -261,7 +289,7 @@ static struct clk_cpu_8996_mux pwrcl_smux = { .name = "pwrcl_smux", .parent_names = (const char *[]){ "xo", - "pwrcl_pll_main", + "pwrcl_pll_postdiv", }, .num_parents = 2, .ops = &clk_cpu_8996_mux_ops, @@ -277,7 +305,7 @@ static struct clk_cpu_8996_mux perfcl_smux = { .name = "perfcl_smux", .parent_names = (const char *[]){ "xo", - "perfcl_pll_main", + "perfcl_pll_postdiv", }, .num_parents = 2, .ops = &clk_cpu_8996_mux_ops, @@ -354,32 +382,25 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, { int i, ret; - perfcl_smux.pll = clk_hw_register_fixed_factor(dev, "perfcl_pll_main", - "perfcl_pll", - CLK_SET_RATE_PARENT, - 1, 2); - if (IS_ERR(perfcl_smux.pll)) { - dev_err(dev, "Failed to initialize perfcl_pll_main\n"); - return PTR_ERR(perfcl_smux.pll); + ret = devm_clk_hw_register(dev, &pwrcl_pll_postdiv.hw); + if (ret) { + dev_err(dev, "Failed to register pwrcl_pll_postdiv: %d", ret); + return ret; } - pwrcl_smux.pll = clk_hw_register_fixed_factor(dev, "pwrcl_pll_main", - "pwrcl_pll", - CLK_SET_RATE_PARENT, - 1, 2); - if (IS_ERR(pwrcl_smux.pll)) { - dev_err(dev, "Failed to initialize pwrcl_pll_main\n"); - clk_hw_unregister(perfcl_smux.pll); - return PTR_ERR(pwrcl_smux.pll); + ret = devm_clk_hw_register(dev, &perfcl_pll_postdiv.hw); + if (ret) { + dev_err(dev, "Failed to register perfcl_pll_postdiv: %d", ret); + return ret; } + pwrcl_smux.pll = &pwrcl_pll_postdiv.hw; + perfcl_smux.pll = &perfcl_pll_postdiv.hw; + for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) { ret = devm_clk_register_regmap(dev, cpu_msm8996_clks[i]); - if (ret) { - clk_hw_unregister(perfcl_smux.pll); - clk_hw_unregister(pwrcl_smux.pll); + if (ret) return ret; - } } clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); @@ -409,9 +430,6 @@ static int qcom_cpu_clk_msm8996_unregister_clks(void) if (ret) return ret; - clk_hw_unregister(perfcl_smux.pll); - clk_hw_unregister(pwrcl_smux.pll); - return 0; } From patchwork Tue Jun 21 16:06:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12889484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B9D3C43334 for ; Tue, 21 Jun 2022 16:07:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353657AbiFUQHU (ORCPT ); Tue, 21 Jun 2022 12:07:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353653AbiFUQHT (ORCPT ); Tue, 21 Jun 2022 12:07:19 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FA069594; Tue, 21 Jun 2022 09:07:17 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id es26so18324714edb.4; Tue, 21 Jun 2022 09:07:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wFX3cKIYPDA5jOA0LlRPg99r8BaDTbP86VBtDe9JGY4=; b=eOCGlLOp4137HpTdNX+AplQr8eL9rHYMo4y9kDeVYWfiPmoW+eCdAi8OqkFhoJN5FS LVqhdPf82WAUWGv4pIGwPNhPKfGDJ7FWLMdIDmkLahPBgEtJ4vYv/KdFTOaqYKhBiw7K PO/hiouZFV8q5n1roLmCuPH9FphjK3Twvc4Ybbmno+qvGwfuc2OcKhY4rN7l0JAtf7U9 exRjhY/2CkiAQb7RiWZnJjTgylBtz/2dxZ61+QC3RbB2RCANUtOap1gFiBbbfyvCiXFn a24PEj7s9+MAWTeqV5pxsNlukejH2LbpGzV4OLob2vgK0WkBNEPzoFK/i2A//vlP/Q4i F1wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wFX3cKIYPDA5jOA0LlRPg99r8BaDTbP86VBtDe9JGY4=; b=Pc/DmDABEEmz1cqWRcx1aOvQ6B5T+PTZvFfBhY91xqRtD4R2lUwxRRIaYCVeJMha/G 83FpRdFXFC3MaGFCNmdFRzNoHdJWIWVBcCdYFv5Lf0BZZN72Dy4eU3uo4CpooyAotGoQ B0oCeuVXuTyAdHPVEq8w0ztSeT9F2NXtZQqN0Oj+M4rrRGGS4/iA4nSUwLwHyIDfYWbE N9YfZRZao2KxezzSYfHLW6AjrDt7Gw0Tpff8aNWJ1cOs2QoIdngwdj7FHqgpahTJ6nKe TxebSM1wix/RNnsOYoMYcUYEjKirLwo5/uDIHuu9gQ+/ZHN8uKeaKUalh40Gof+Jvnwz Bfpw== X-Gm-Message-State: AJIora+ZNc1HNn+vJ2ExHiwV3EB722te6WmNUWCRvsqnrt0kKm/KkuoG u2wmHeLmJJDzZq/NhpPK67g= X-Google-Smtp-Source: AGRyM1se+JEKo32UuANFLMv8SfjHAQ09NoxOLRMy9jxLyNUcEnm+tVGdr8/3MitmLoE0HEQHVt3s7w== X-Received: by 2002:a05:6402:3224:b0:435:80fd:333 with SMTP id g36-20020a056402322400b0043580fd0333mr13154371eda.76.1655827635653; Tue, 21 Jun 2022 09:07:15 -0700 (PDT) Received: from localhost.localdomain ([185.107.57.61]) by smtp.gmail.com with ESMTPSA id p6-20020a17090653c600b00722e0b1fa8esm1772943ejo.164.2022.06.21.09.07.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 09:07:15 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Loic Poulain Cc: Yassine Oudjana , Yassine Oudjana , Dmitry Baryshkov , Konrad Dybcio , AngeloGioacchino Del Regno , Martin Botka , Marijn Suijten , Jami Kettunen , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] clk: qcom: msm8996-cpu: Unify cluster order Date: Tue, 21 Jun 2022 20:06:18 +0400 Message-Id: <20220621160621.24415-4-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220621160621.24415-1-y.oudjana@protonmail.com> References: <20220621160621.24415-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Yassine Oudjana The power cluster comes before the performance cluster. Make everything in the driver follow this order. Signed-off-by: Yassine Oudjana Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-cpu-8996.c | 36 ++++++++++++++++----------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 217f9392c23d..b6761a74d5ac 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -111,24 +111,24 @@ static const struct alpha_pll_config hfpll_config = { .early_output_mask = BIT(3), }; -static struct clk_alpha_pll perfcl_pll = { - .offset = PERFCL_REG_OFFSET, +static struct clk_alpha_pll pwrcl_pll = { + .offset = PWRCL_REG_OFFSET, .regs = prim_pll_regs, .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data){ - .name = "perfcl_pll", + .name = "pwrcl_pll", .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_alpha_pll_huayra_ops, }, }; -static struct clk_alpha_pll pwrcl_pll = { - .offset = PWRCL_REG_OFFSET, +static struct clk_alpha_pll perfcl_pll = { + .offset = PERFCL_REG_OFFSET, .regs = prim_pll_regs, .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data){ - .name = "pwrcl_pll", + .name = "perfcl_pll", .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_alpha_pll_huayra_ops, @@ -181,28 +181,28 @@ static const struct alpha_pll_config altpll_config = { .early_output_mask = BIT(3), }; -static struct clk_alpha_pll perfcl_alt_pll = { - .offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET, +static struct clk_alpha_pll pwrcl_alt_pll = { + .offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET, .regs = alt_pll_regs, .vco_table = alt_pll_vco_modes, .num_vco = ARRAY_SIZE(alt_pll_vco_modes), .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data) { - .name = "perfcl_alt_pll", + .name = "pwrcl_alt_pll", .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_alpha_pll_hwfsm_ops, }, }; -static struct clk_alpha_pll pwrcl_alt_pll = { - .offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET, +static struct clk_alpha_pll perfcl_alt_pll = { + .offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET, .regs = alt_pll_regs, .vco_table = alt_pll_vco_modes, .num_vco = ARRAY_SIZE(alt_pll_vco_modes), .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data) { - .name = "pwrcl_alt_pll", + .name = "perfcl_alt_pll", .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_alpha_pll_hwfsm_ops, @@ -367,14 +367,14 @@ static const struct regmap_config cpu_msm8996_regmap_config = { }; static struct clk_regmap *cpu_msm8996_clks[] = { - &perfcl_pll.clkr, &pwrcl_pll.clkr, - &perfcl_alt_pll.clkr, + &perfcl_pll.clkr, &pwrcl_alt_pll.clkr, - &perfcl_smux.clkr, + &perfcl_alt_pll.clkr, &pwrcl_smux.clkr, - &perfcl_pmux.clkr, + &perfcl_smux.clkr, &pwrcl_pmux.clkr, + &perfcl_pmux.clkr, }; static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, @@ -403,10 +403,10 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, return ret; } - clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); - clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); + clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); + clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); /* Enable alt PLLs */ clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk); From patchwork Tue Jun 21 16:06:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12889485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5D55C43334 for ; Tue, 21 Jun 2022 16:07:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353669AbiFUQH1 (ORCPT ); Tue, 21 Jun 2022 12:07:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353653AbiFUQHZ (ORCPT ); Tue, 21 Jun 2022 12:07:25 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6F639593; Tue, 21 Jun 2022 09:07:24 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id o9so10793715edt.12; Tue, 21 Jun 2022 09:07:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CXPjLPecJruydocgfpfwjtoFmsZbdRkFyw772HfQkOE=; b=D+4g1zumSM8FFfBGWHVhla8AUSTUpeGLjVpnIyUP5fCPIVoq3OxQjzmLK4ELdP08/F 0ZCawGIEjtr8smBURwirqdUgaQaPpphVLl9gq3R+ZWuLg5d/TthlWjd9ovDmgHWOlkL0 CvXMaoQDQWEu8/8tPzOqfbW5+J4OyfbNi171bmgqeeOsen8Q3GpS7Yh1Xywx2d8QzqWk i9MJkMlj/GzC/s9WpPQl36NNX837/nBQFvd/9OrPMvJXTa9G7gi0kPKNWJunilOqmXUr IDW2QLCPnDCTLqsZwKGzpGxFL13Rw9nl12N8y8XxGO86u1BsDpav/Gr8KvEPnUaR8U3M 4eBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CXPjLPecJruydocgfpfwjtoFmsZbdRkFyw772HfQkOE=; b=rtF9jRWGw9DsWUrrTy62YhV/25/7T+4I3DfGYjPOwp1KivOTc1VVwbIS4/NjR6QflI ObflgFXvQoPTqxaVkPafMks3sgymB9f0oCRIXZWDYsJ1D/rwupdJHKjUty7wm3gBVFbj BZf/zOW8PwiOc81XchjgKXE3g98SSRq1/y5UsbegxSNeucFecASZuoy38nIhjticQSr9 JJf80cat2Gt4ywOFsYN4hA6EDwdcQyoelTxiIceh+Vi9rb4W2IoSSItEhew+Odm7UoYH K7O9xPevB2J9MnAiAJQODLUVLoPCRG2NqWbsgOHpWgAqudSoLQuFwm2ppY2Qdd9Q+DGn Jc3w== X-Gm-Message-State: AJIora/+hUfqpPD6Xn3w5QfWpOX+T1eKE5TQXGnMxh2Pi4b5xeUzqOV7 SMRlvvO4VQC69uOKSjOBO/xJEhfbO7ayXrUDk5c= X-Google-Smtp-Source: AGRyM1urWBzh7lugwKJx2neEL0NFi/42kDj2d/B3S0673nKdO55a1YwmvYGV+r78VVQlQaUuryqqWA== X-Received: by 2002:a05:6402:c44:b0:431:52cc:f933 with SMTP id cs4-20020a0564020c4400b0043152ccf933mr36007134edb.41.1655827643264; Tue, 21 Jun 2022 09:07:23 -0700 (PDT) Received: from localhost.localdomain ([185.107.57.61]) by smtp.gmail.com with ESMTPSA id p6-20020a17090653c600b00722e0b1fa8esm1772943ejo.164.2022.06.21.09.07.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 09:07:22 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Loic Poulain Cc: Yassine Oudjana , Yassine Oudjana , Dmitry Baryshkov , Konrad Dybcio , AngeloGioacchino Del Regno , Martin Botka , Marijn Suijten , Jami Kettunen , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] clk: qcom: msm8996-cpu: Convert secondary muxes to clk_regmap_mux Date: Tue, 21 Jun 2022 20:06:19 +0400 Message-Id: <20220621160621.24415-5-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220621160621.24415-1-y.oudjana@protonmail.com> References: <20220621160621.24415-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Yassine Oudjana There is nothing special about the secondary muxes, unlike the primary muxes which need some extra logic to handle ACD and switching between primary PLL and secondary mux sources. Turn them into clk_regmap_mux and rename cpu_clk_msm8996_mux into cpu_clk_msm8996_pmux to make it specific to primary muxes. Signed-off-by: Yassine Oudjana Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-cpu-8996.c | 62 ++++++++++++++++----------------- 1 file changed, 30 insertions(+), 32 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index b6761a74d5ac..b3ad9245874d 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -59,6 +59,7 @@ #include "clk-alpha-pll.h" #include "clk-regmap.h" +#include "clk-regmap-mux.h" enum _pmux_input { SMUX_INDEX = 0, @@ -209,7 +210,7 @@ static struct clk_alpha_pll perfcl_alt_pll = { }, }; -struct clk_cpu_8996_mux { +struct clk_cpu_8996_pmux { u32 reg; u8 shift; u8 width; @@ -222,18 +223,18 @@ struct clk_cpu_8996_mux { static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, void *data); -#define to_clk_cpu_8996_mux_nb(_nb) \ - container_of(_nb, struct clk_cpu_8996_mux, nb) +#define to_clk_cpu_8996_pmux_nb(_nb) \ + container_of(_nb, struct clk_cpu_8996_pmux, nb) -static inline struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw) +static inline struct clk_cpu_8996_pmux *to_clk_cpu_8996_pmux_hw(struct clk_hw *hw) { - return container_of(to_clk_regmap(hw), struct clk_cpu_8996_mux, clkr); + return container_of(to_clk_regmap(hw), struct clk_cpu_8996_pmux, clkr); } -static u8 clk_cpu_8996_mux_get_parent(struct clk_hw *hw) +static u8 clk_cpu_8996_pmux_get_parent(struct clk_hw *hw) { struct clk_regmap *clkr = to_clk_regmap(hw); - struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); + struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); u32 mask = GENMASK(cpuclk->width - 1, 0); u32 val; @@ -243,10 +244,10 @@ static u8 clk_cpu_8996_mux_get_parent(struct clk_hw *hw) return val & mask; } -static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) +static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index) { struct clk_regmap *clkr = to_clk_regmap(hw); - struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); + struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); u32 mask = GENMASK(cpuclk->width + cpuclk->shift - 1, cpuclk->shift); u32 val; @@ -256,10 +257,10 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val); } -static int clk_cpu_8996_mux_determine_rate(struct clk_hw *hw, +static int clk_cpu_8996_pmux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); + struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); struct clk_hw *parent = cpuclk->pll; if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) { @@ -275,13 +276,13 @@ static int clk_cpu_8996_mux_determine_rate(struct clk_hw *hw, return 0; } -static const struct clk_ops clk_cpu_8996_mux_ops = { - .set_parent = clk_cpu_8996_mux_set_parent, - .get_parent = clk_cpu_8996_mux_get_parent, - .determine_rate = clk_cpu_8996_mux_determine_rate, +static const struct clk_ops clk_cpu_8996_pmux_ops = { + .set_parent = clk_cpu_8996_pmux_set_parent, + .get_parent = clk_cpu_8996_pmux_get_parent, + .determine_rate = clk_cpu_8996_pmux_determine_rate, }; -static struct clk_cpu_8996_mux pwrcl_smux = { +static struct clk_regmap_mux pwrcl_smux = { .reg = PWRCL_REG_OFFSET + MUX_OFFSET, .shift = 2, .width = 2, @@ -292,12 +293,12 @@ static struct clk_cpu_8996_mux pwrcl_smux = { "pwrcl_pll_postdiv", }, .num_parents = 2, - .ops = &clk_cpu_8996_mux_ops, + .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, }; -static struct clk_cpu_8996_mux perfcl_smux = { +static struct clk_regmap_mux perfcl_smux = { .reg = PERFCL_REG_OFFSET + MUX_OFFSET, .shift = 2, .width = 2, @@ -308,12 +309,12 @@ static struct clk_cpu_8996_mux perfcl_smux = { "perfcl_pll_postdiv", }, .num_parents = 2, - .ops = &clk_cpu_8996_mux_ops, + .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, }; -static struct clk_cpu_8996_mux pwrcl_pmux = { +static struct clk_cpu_8996_pmux pwrcl_pmux = { .reg = PWRCL_REG_OFFSET + MUX_OFFSET, .shift = 0, .width = 2, @@ -329,13 +330,13 @@ static struct clk_cpu_8996_mux pwrcl_pmux = { "pwrcl_alt_pll", }, .num_parents = 4, - .ops = &clk_cpu_8996_mux_ops, + .ops = &clk_cpu_8996_pmux_ops, /* CPU clock is critical and should never be gated */ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, }, }; -static struct clk_cpu_8996_mux perfcl_pmux = { +static struct clk_cpu_8996_pmux perfcl_pmux = { .reg = PERFCL_REG_OFFSET + MUX_OFFSET, .shift = 0, .width = 2, @@ -351,7 +352,7 @@ static struct clk_cpu_8996_mux perfcl_pmux = { "perfcl_alt_pll", }, .num_parents = 4, - .ops = &clk_cpu_8996_mux_ops, + .ops = &clk_cpu_8996_pmux_ops, /* CPU clock is critical and should never be gated */ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, }, @@ -394,9 +395,6 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, return ret; } - pwrcl_smux.pll = &pwrcl_pll_postdiv.hw; - perfcl_smux.pll = &perfcl_pll_postdiv.hw; - for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) { ret = devm_clk_register_regmap(dev, cpu_msm8996_clks[i]); if (ret) @@ -474,22 +472,22 @@ static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base) static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, void *data) { - struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb); + struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_nb(nb); struct clk_notifier_data *cnd = data; int ret; switch (event) { case PRE_RATE_CHANGE: - ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); + ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); qcom_cpu_clk_msm8996_acd_init(base); break; case POST_RATE_CHANGE: if (cnd->new_rate < DIV_2_THRESHOLD) - ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, - SMUX_INDEX); + ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, + SMUX_INDEX); else - ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, - ACD_INDEX); + ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, + ACD_INDEX); break; default: ret = 0; From patchwork Tue Jun 21 16:06:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12889486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E2C4C433EF for ; Tue, 21 Jun 2022 16:07:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353693AbiFUQHj (ORCPT ); Tue, 21 Jun 2022 12:07:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353686AbiFUQHe (ORCPT ); Tue, 21 Jun 2022 12:07:34 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5DA363B4; Tue, 21 Jun 2022 09:07:32 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id eq6so12694308edb.6; Tue, 21 Jun 2022 09:07:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ogkf5Ukl+CuQggmQ823HfWD79KHuQNHGRJztDxCaGzE=; b=eaSpaNHxFzndeLG8tpbkAL3av5yuAtZYrV0DBIA04sgfEyJVlLvxqfbSxbfUUivFZv 2hGbJL7Iu2KkANliMScg7r3NDNHAAOwdSHqgbyBuSM6w+DyTYkLf3G/grZo+YXdNKBlr giYSrMp9RA2N3HTBr7iJr+6jpVsKNlb25MPliZvzDRuKQbIlI3cEQRLbleY6saJNPCKu 1JsIPX3ochF+9C2cw+Qw4VQlIABNPWs8UQJxgopgJxsR2VEo1GVstSAZUMOm+wOINwad IHf0mw+NpXP+AXoNhg7frOrlpZUEOlwNFHamPx4K8cyMJDbHFfJRzMOZQImnVCesMAeC 6Xbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ogkf5Ukl+CuQggmQ823HfWD79KHuQNHGRJztDxCaGzE=; b=mhqN8PZp60IxP213Xsli4VgJZaKkbYHAWG9EjJm0j39ApQHDy5M+/uJEArUdVppB7y L9hvETGWCq3ONXbOWSgSAK1ReuJZ8ktDjYhtV8CHBH0GJ7+LB85R0Z1Nt5sEOZse1GBK QMGlEpRLUIkgbNbR6YApIhHxuvDOaww8exd99sNeEi7GhMd7qf1R5By9idU2KkHgwZGr eiE5szsIMAXPSSamFJhAHQq4rDr/kZX+1QovWe4vnk2BZVU7FcDW31BgQ14rSj3wQv/e C8Kv6Qjn9VIPEk443+Pd+69LlsjgPQP55N8+Wv2jL/6qRKk0Jj1OhTYIt//krNF6HHQL E7Fw== X-Gm-Message-State: AJIora/SkghBIctSitFDMgtMAJ3UB7tmbt9hLESwT8xeMrHzntcsiC/s i5GazMX4dCROzgyodtk+FK8= X-Google-Smtp-Source: AGRyM1uNVRaBXmfIUfA0uziPrBwe+OcObVEYHAxR9T1Y2dShkmHLDrPUGC//TS6mQiijKioA5yNFfw== X-Received: by 2002:a05:6402:1774:b0:435:7fea:8c02 with SMTP id da20-20020a056402177400b004357fea8c02mr14085854edb.213.1655827651406; Tue, 21 Jun 2022 09:07:31 -0700 (PDT) Received: from localhost.localdomain ([185.107.57.61]) by smtp.gmail.com with ESMTPSA id p6-20020a17090653c600b00722e0b1fa8esm1772943ejo.164.2022.06.21.09.07.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 09:07:31 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Loic Poulain Cc: Yassine Oudjana , Yassine Oudjana , Dmitry Baryshkov , Konrad Dybcio , AngeloGioacchino Del Regno , Martin Botka , Marijn Suijten , Jami Kettunen , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] dt-bindings: clock: qcom,msm8996-apcc: Fix clocks Date: Tue, 21 Jun 2022 20:06:20 +0400 Message-Id: <20220621160621.24415-6-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220621160621.24415-1-y.oudjana@protonmail.com> References: <20220621160621.24415-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Yassine Oudjana The clocks currently listed in clocks and clock-names are the ones supplied by this clock controller, not the ones it consumes. Replace them with the only clock it consumes - the on-board oscillator (XO), and make the properties required. Signed-off-by: Yassine Oudjana Reviewed-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,msm8996-apcc.yaml | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml index a20cb10636dd..c4971234fef8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml @@ -26,22 +26,18 @@ properties: clocks: items: - - description: Primary PLL clock for power cluster (little) - - description: Primary PLL clock for perf cluster (big) - - description: Alternate PLL clock for power cluster (little) - - description: Alternate PLL clock for perf cluster (big) + - description: XO source clock-names: items: - - const: pwrcl_pll - - const: perfcl_pll - - const: pwrcl_alt_pll - - const: perfcl_alt_pll + - const: xo required: - compatible - reg - '#clock-cells' + - clocks + - clock-names additionalProperties: false @@ -51,4 +47,7 @@ examples: compatible = "qcom,msm8996-apcc"; reg = <0x6400000 0x90000>; #clock-cells = <1>; + + clocks = <&xo_board>; + clock-names = "xo"; }; From patchwork Tue Jun 21 16:06:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12889487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E05D0C433EF for ; Tue, 21 Jun 2022 16:07:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353706AbiFUQHm (ORCPT ); Tue, 21 Jun 2022 12:07:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353686AbiFUQHm (ORCPT ); Tue, 21 Jun 2022 12:07:42 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDA66F1E; Tue, 21 Jun 2022 09:07:40 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id cf14so10262881edb.8; Tue, 21 Jun 2022 09:07:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n1RNO5f7pssWPG4fLr9gdAw4eJ32N3P99Wlmi11446o=; b=JO89EeNFZ40UdDOlEKa1vkBnKCof/favGwBF1HBd7qmSmaKWqFGdcCgR4Epcgx+/Q2 RgIg/21jb/qDXqDt4LfYapKAkxH5N3ndT7tpQF6n/QjqeuMn//MVLofYechx5pdKJz/W S0ph4ZMug+P19CbQ5vvtXePHRDCzLvyB0Y8rh/a8FVxJ6LsV1dIqgPQWdDacegSvx+iV TD0+aFw7LyDXVQhg0iyzcxKWaff3U9SqmqlTYWZqfmIbAij0N8azccoDn54KYIMk7oYe /gtG86/Xb9Rw5kVsQb9jAme5YQAKR+an5xHLqTwq/XSJv4irR+LIWne/lxOeDqiQ2RWs RBig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n1RNO5f7pssWPG4fLr9gdAw4eJ32N3P99Wlmi11446o=; b=rh2lVC9boZkP3xpdtJrdmy3CFiPegnPRAAkBDOqrOWeNZol3e+D9IrN+yVtjzD4hog Y1YC1YheAjXGVX3T7KTfVJ+/nH5+qeETDOVYwZUSHkiaEU/XQJS6F2XKzMLBr89INor2 lAuYvHZVn/Thms9y0JrqZOgILXPBlifXmWP9Bu58yYljQEGkg3nJOE4I4Zbb+tP4x0tm 7lWKYCdnuUgFYeTrUXO618FLdHBDHREjxlawqbmABuClv9Wor74TYvW6rHmLRPPAfKOU qBLvhFOfPRle7MsJITgQqI4Ico0XkG/3A+E2iPsjj/3uLGFf+VMlvfO/RaUltScSLaPB u3jA== X-Gm-Message-State: AJIora+b+8rwNYReHOxk69K0TCtDJ4H+rCtSbdf6f2f7F0Z5rYLYADOB u+HvunqkwyWr4JDfdnsLfm0= X-Google-Smtp-Source: AGRyM1uVyDy8Qc2zsSxZEhbGY0aVHaxjcptrDReKKrpX0HRiXCQZ1C0r/FIdLr0CaHZza7EbcR4J3Q== X-Received: by 2002:a05:6402:3708:b0:433:2d3b:ed5 with SMTP id ek8-20020a056402370800b004332d3b0ed5mr36305919edb.246.1655827659371; Tue, 21 Jun 2022 09:07:39 -0700 (PDT) Received: from localhost.localdomain ([185.107.57.61]) by smtp.gmail.com with ESMTPSA id p6-20020a17090653c600b00722e0b1fa8esm1772943ejo.164.2022.06.21.09.07.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 09:07:39 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Loic Poulain Cc: Yassine Oudjana , Yassine Oudjana , Dmitry Baryshkov , Konrad Dybcio , AngeloGioacchino Del Regno , Martin Botka , Marijn Suijten , Jami Kettunen , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] clk: qcom: msm8996-cpu: Use parent_data for all clocks Date: Tue, 21 Jun 2022 20:06:21 +0400 Message-Id: <20220621160621.24415-7-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220621160621.24415-1-y.oudjana@protonmail.com> References: <20220621160621.24415-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Yassine Oudjana Replace parent_names in PLLs, secondary muxes and primary muxes with parent_data. For primary muxes there were never any *cl_pll_acd clocks, so instead of adding them, put the primary PLLs in both PLL_INDEX and ACD_INDEX, then make sure ACD_INDEX is always picked over PLL_INDEX when setting parent since we always want ACD when using the primary PLLs. Signed-off-by: Yassine Oudjana --- drivers/clk/qcom/clk-cpu-8996.c | 79 ++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 32 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index b3ad9245874d..cdb7b2ef3367 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -112,14 +112,18 @@ static const struct alpha_pll_config hfpll_config = { .early_output_mask = BIT(3), }; +static const struct clk_parent_data pll_parent[] = { + { .fw_name = "xo" }, +}; + static struct clk_alpha_pll pwrcl_pll = { .offset = PWRCL_REG_OFFSET, .regs = prim_pll_regs, .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "pwrcl_pll", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, + .parent_data = pll_parent, + .num_parents = ARRAY_SIZE(pll_parent), .ops = &clk_alpha_pll_huayra_ops, }, }; @@ -130,8 +134,8 @@ static struct clk_alpha_pll perfcl_pll = { .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "perfcl_pll", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, + .parent_data = pll_parent, + .num_parents = ARRAY_SIZE(pll_parent), .ops = &clk_alpha_pll_huayra_ops, }, }; @@ -190,8 +194,8 @@ static struct clk_alpha_pll pwrcl_alt_pll = { .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_alt_pll", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, + .parent_data = pll_parent, + .num_parents = ARRAY_SIZE(pll_parent), .ops = &clk_alpha_pll_hwfsm_ops, }, }; @@ -204,8 +208,8 @@ static struct clk_alpha_pll perfcl_alt_pll = { .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_alt_pll", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, + .parent_data = pll_parent, + .num_parents = ARRAY_SIZE(pll_parent), .ops = &clk_alpha_pll_hwfsm_ops, }, }; @@ -252,6 +256,9 @@ static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index) u32 val; val = index; + /* We always want ACD when using the primary PLL */ + if (val == PLL_INDEX) + val = ACD_INDEX; val <<= cpuclk->shift; return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val); @@ -282,17 +289,24 @@ static const struct clk_ops clk_cpu_8996_pmux_ops = { .determine_rate = clk_cpu_8996_pmux_determine_rate, }; +static const struct clk_parent_data pwrcl_smux_parents[] = { + { .fw_name = "xo" }, + { .hw = &pwrcl_pll_postdiv.hw }, +}; + +static const struct clk_parent_data perfcl_smux_parents[] = { + { .fw_name = "xo" }, + { .hw = &perfcl_pll_postdiv.hw }, +}; + static struct clk_regmap_mux pwrcl_smux = { .reg = PWRCL_REG_OFFSET + MUX_OFFSET, .shift = 2, .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_smux", - .parent_names = (const char *[]){ - "xo", - "pwrcl_pll_postdiv", - }, - .num_parents = 2, + .parent_data = pwrcl_smux_parents, + .num_parents = ARRAY_SIZE(pwrcl_smux_parents), .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -304,16 +318,27 @@ static struct clk_regmap_mux perfcl_smux = { .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_smux", - .parent_names = (const char *[]){ - "xo", - "perfcl_pll_postdiv", - }, - .num_parents = 2, + .parent_data = perfcl_smux_parents, + .num_parents = ARRAY_SIZE(perfcl_smux_parents), .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, }; +static const struct clk_parent_data pwrcl_pmux_parents[] = { + [SMUX_INDEX] = { .hw = &pwrcl_smux.clkr.hw }, + [PLL_INDEX] = { .hw = &pwrcl_pll.clkr.hw }, + [ACD_INDEX] = { .hw = &pwrcl_pll.clkr.hw }, + [ALT_INDEX] = { .hw = &pwrcl_alt_pll.clkr.hw }, +}; + +static const struct clk_parent_data perfcl_pmux_parents[] = { + [SMUX_INDEX] = { .hw = &perfcl_smux.clkr.hw }, + [PLL_INDEX] = { .hw = &perfcl_pll.clkr.hw }, + [ACD_INDEX] = { .hw = &perfcl_pll.clkr.hw }, + [ALT_INDEX] = { .hw = &perfcl_alt_pll.clkr.hw }, +}; + static struct clk_cpu_8996_pmux pwrcl_pmux = { .reg = PWRCL_REG_OFFSET + MUX_OFFSET, .shift = 0, @@ -323,13 +348,8 @@ static struct clk_cpu_8996_pmux pwrcl_pmux = { .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_pmux", - .parent_names = (const char *[]){ - "pwrcl_smux", - "pwrcl_pll", - "pwrcl_pll_acd", - "pwrcl_alt_pll", - }, - .num_parents = 4, + .parent_data = pwrcl_pmux_parents, + .num_parents = ARRAY_SIZE(pwrcl_pmux_parents), .ops = &clk_cpu_8996_pmux_ops, /* CPU clock is critical and should never be gated */ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, @@ -345,13 +365,8 @@ static struct clk_cpu_8996_pmux perfcl_pmux = { .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_pmux", - .parent_names = (const char *[]){ - "perfcl_smux", - "perfcl_pll", - "perfcl_pll_acd", - "perfcl_alt_pll", - }, - .num_parents = 4, + .parent_data = perfcl_pmux_parents, + .num_parents = ARRAY_SIZE(perfcl_pmux_parents), .ops = &clk_cpu_8996_pmux_ops, /* CPU clock is critical and should never be gated */ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,